1 /* 2 * GPIO driver for Marvell SoCs 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Andrew Lunn <andrew@lunn.ch> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 * 14 * This driver is a fairly straightforward GPIO driver for the 15 * complete family of Marvell EBU SoC platforms (Orion, Dove, 16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 17 * driver is the different register layout that exists between the 18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 19 * platforms (MV78200 from the Discovery family and the Armada 20 * XP). Therefore, this driver handles three variants of the GPIO 21 * block: 22 * - the basic variant, called "orion-gpio", with the simplest 23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 24 * non-SMP Discovery systems 25 * - the mv78200 variant for MV78200 Discovery systems. This variant 26 * turns the edge mask and level mask registers into CPU0 edge 27 * mask/level mask registers, and adds CPU1 edge mask/level mask 28 * registers. 29 * - the armadaxp variant for Armada XP systems. This variant keeps 30 * the normal cause/edge mask/level mask registers when the global 31 * interrupts are used, but adds per-CPU cause/edge mask/level mask 32 * registers n a separate memory area for the per-CPU GPIO 33 * interrupts. 34 */ 35 36 #include <linux/err.h> 37 #include <linux/init.h> 38 #include <linux/gpio.h> 39 #include <linux/irq.h> 40 #include <linux/slab.h> 41 #include <linux/irqdomain.h> 42 #include <linux/io.h> 43 #include <linux/of_irq.h> 44 #include <linux/of_device.h> 45 #include <linux/pwm.h> 46 #include <linux/clk.h> 47 #include <linux/pinctrl/consumer.h> 48 #include <linux/irqchip/chained_irq.h> 49 #include <linux/platform_device.h> 50 #include <linux/bitops.h> 51 52 #include "gpiolib.h" 53 54 /* 55 * GPIO unit register offsets. 56 */ 57 #define GPIO_OUT_OFF 0x0000 58 #define GPIO_IO_CONF_OFF 0x0004 59 #define GPIO_BLINK_EN_OFF 0x0008 60 #define GPIO_IN_POL_OFF 0x000c 61 #define GPIO_DATA_IN_OFF 0x0010 62 #define GPIO_EDGE_CAUSE_OFF 0x0014 63 #define GPIO_EDGE_MASK_OFF 0x0018 64 #define GPIO_LEVEL_MASK_OFF 0x001c 65 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020 66 67 /* 68 * PWM register offsets. 69 */ 70 #define PWM_BLINK_ON_DURATION_OFF 0x0 71 #define PWM_BLINK_OFF_DURATION_OFF 0x4 72 73 74 /* The MV78200 has per-CPU registers for edge mask and level mask */ 75 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 76 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 77 78 /* 79 * The Armada XP has per-CPU registers for interrupt cause, interrupt 80 * mask and interrupt level mask. Those are relative to the 81 * percpu_membase. 82 */ 83 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 84 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 85 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 86 87 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 88 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 89 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 90 91 #define MVEBU_MAX_GPIO_PER_BANK 32 92 93 struct mvebu_pwm { 94 void __iomem *membase; 95 unsigned long clk_rate; 96 struct gpio_desc *gpiod; 97 struct pwm_chip chip; 98 spinlock_t lock; 99 struct mvebu_gpio_chip *mvchip; 100 101 /* Used to preserve GPIO/PWM registers across suspend/resume */ 102 u32 blink_select; 103 u32 blink_on_duration; 104 u32 blink_off_duration; 105 }; 106 107 struct mvebu_gpio_chip { 108 struct gpio_chip chip; 109 spinlock_t lock; 110 void __iomem *membase; 111 void __iomem *percpu_membase; 112 int irqbase; 113 struct irq_domain *domain; 114 int soc_variant; 115 116 /* Used for PWM support */ 117 struct clk *clk; 118 struct mvebu_pwm *mvpwm; 119 120 /* Used to preserve GPIO registers across suspend/resume */ 121 u32 out_reg; 122 u32 io_conf_reg; 123 u32 blink_en_reg; 124 u32 in_pol_reg; 125 u32 edge_mask_regs[4]; 126 u32 level_mask_regs[4]; 127 }; 128 129 /* 130 * Functions returning addresses of individual registers for a given 131 * GPIO controller. 132 */ 133 static void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip) 134 { 135 return mvchip->membase + GPIO_OUT_OFF; 136 } 137 138 static void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip) 139 { 140 return mvchip->membase + GPIO_BLINK_EN_OFF; 141 } 142 143 static void __iomem *mvebu_gpioreg_blink_counter_select(struct mvebu_gpio_chip 144 *mvchip) 145 { 146 return mvchip->membase + GPIO_BLINK_CNT_SELECT_OFF; 147 } 148 149 static void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) 150 { 151 return mvchip->membase + GPIO_IO_CONF_OFF; 152 } 153 154 static void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip) 155 { 156 return mvchip->membase + GPIO_IN_POL_OFF; 157 } 158 159 static void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) 160 { 161 return mvchip->membase + GPIO_DATA_IN_OFF; 162 } 163 164 static void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) 165 { 166 int cpu; 167 168 switch (mvchip->soc_variant) { 169 case MVEBU_GPIO_SOC_VARIANT_ORION: 170 case MVEBU_GPIO_SOC_VARIANT_MV78200: 171 return mvchip->membase + GPIO_EDGE_CAUSE_OFF; 172 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 173 cpu = smp_processor_id(); 174 return mvchip->percpu_membase + 175 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 176 default: 177 BUG(); 178 } 179 } 180 181 static void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) 182 { 183 int cpu; 184 185 switch (mvchip->soc_variant) { 186 case MVEBU_GPIO_SOC_VARIANT_ORION: 187 return mvchip->membase + GPIO_EDGE_MASK_OFF; 188 case MVEBU_GPIO_SOC_VARIANT_MV78200: 189 cpu = smp_processor_id(); 190 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); 191 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 192 cpu = smp_processor_id(); 193 return mvchip->percpu_membase + 194 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 195 default: 196 BUG(); 197 } 198 } 199 200 static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) 201 { 202 int cpu; 203 204 switch (mvchip->soc_variant) { 205 case MVEBU_GPIO_SOC_VARIANT_ORION: 206 return mvchip->membase + GPIO_LEVEL_MASK_OFF; 207 case MVEBU_GPIO_SOC_VARIANT_MV78200: 208 cpu = smp_processor_id(); 209 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); 210 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 211 cpu = smp_processor_id(); 212 return mvchip->percpu_membase + 213 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 214 default: 215 BUG(); 216 } 217 } 218 219 /* 220 * Functions returning addresses of individual registers for a given 221 * PWM controller. 222 */ 223 static void __iomem *mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) 224 { 225 return mvpwm->membase + PWM_BLINK_ON_DURATION_OFF; 226 } 227 228 static void __iomem *mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) 229 { 230 return mvpwm->membase + PWM_BLINK_OFF_DURATION_OFF; 231 } 232 233 /* 234 * Functions implementing the gpio_chip methods 235 */ 236 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 237 { 238 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 239 unsigned long flags; 240 u32 u; 241 242 spin_lock_irqsave(&mvchip->lock, flags); 243 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); 244 if (value) 245 u |= BIT(pin); 246 else 247 u &= ~BIT(pin); 248 writel_relaxed(u, mvebu_gpioreg_out(mvchip)); 249 spin_unlock_irqrestore(&mvchip->lock, flags); 250 } 251 252 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) 253 { 254 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 255 u32 u; 256 257 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin)) { 258 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ 259 readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 260 } else { 261 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); 262 } 263 264 return (u >> pin) & 1; 265 } 266 267 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, 268 int value) 269 { 270 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 271 unsigned long flags; 272 u32 u; 273 274 spin_lock_irqsave(&mvchip->lock, flags); 275 u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); 276 if (value) 277 u |= BIT(pin); 278 else 279 u &= ~BIT(pin); 280 writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); 281 spin_unlock_irqrestore(&mvchip->lock, flags); 282 } 283 284 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) 285 { 286 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 287 unsigned long flags; 288 int ret; 289 u32 u; 290 291 /* 292 * Check with the pinctrl driver whether this pin is usable as 293 * an input GPIO 294 */ 295 ret = pinctrl_gpio_direction_input(chip->base + pin); 296 if (ret) 297 return ret; 298 299 spin_lock_irqsave(&mvchip->lock, flags); 300 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 301 u |= BIT(pin); 302 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 303 spin_unlock_irqrestore(&mvchip->lock, flags); 304 305 return 0; 306 } 307 308 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, 309 int value) 310 { 311 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 312 unsigned long flags; 313 int ret; 314 u32 u; 315 316 /* 317 * Check with the pinctrl driver whether this pin is usable as 318 * an output GPIO 319 */ 320 ret = pinctrl_gpio_direction_output(chip->base + pin); 321 if (ret) 322 return ret; 323 324 mvebu_gpio_blink(chip, pin, 0); 325 mvebu_gpio_set(chip, pin, value); 326 327 spin_lock_irqsave(&mvchip->lock, flags); 328 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 329 u &= ~BIT(pin); 330 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 331 spin_unlock_irqrestore(&mvchip->lock, flags); 332 333 return 0; 334 } 335 336 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) 337 { 338 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 339 340 return irq_create_mapping(mvchip->domain, pin); 341 } 342 343 /* 344 * Functions implementing the irq_chip methods 345 */ 346 static void mvebu_gpio_irq_ack(struct irq_data *d) 347 { 348 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 349 struct mvebu_gpio_chip *mvchip = gc->private; 350 u32 mask = d->mask; 351 352 irq_gc_lock(gc); 353 writel_relaxed(~mask, mvebu_gpioreg_edge_cause(mvchip)); 354 irq_gc_unlock(gc); 355 } 356 357 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 358 { 359 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 360 struct mvebu_gpio_chip *mvchip = gc->private; 361 struct irq_chip_type *ct = irq_data_get_chip_type(d); 362 u32 mask = d->mask; 363 364 irq_gc_lock(gc); 365 ct->mask_cache_priv &= ~mask; 366 367 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); 368 irq_gc_unlock(gc); 369 } 370 371 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 372 { 373 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 374 struct mvebu_gpio_chip *mvchip = gc->private; 375 struct irq_chip_type *ct = irq_data_get_chip_type(d); 376 u32 mask = d->mask; 377 378 irq_gc_lock(gc); 379 ct->mask_cache_priv |= mask; 380 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_edge_mask(mvchip)); 381 irq_gc_unlock(gc); 382 } 383 384 static void mvebu_gpio_level_irq_mask(struct irq_data *d) 385 { 386 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 387 struct mvebu_gpio_chip *mvchip = gc->private; 388 struct irq_chip_type *ct = irq_data_get_chip_type(d); 389 u32 mask = d->mask; 390 391 irq_gc_lock(gc); 392 ct->mask_cache_priv &= ~mask; 393 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); 394 irq_gc_unlock(gc); 395 } 396 397 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 398 { 399 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 400 struct mvebu_gpio_chip *mvchip = gc->private; 401 struct irq_chip_type *ct = irq_data_get_chip_type(d); 402 u32 mask = d->mask; 403 404 irq_gc_lock(gc); 405 ct->mask_cache_priv |= mask; 406 writel_relaxed(ct->mask_cache_priv, mvebu_gpioreg_level_mask(mvchip)); 407 irq_gc_unlock(gc); 408 } 409 410 /***************************************************************************** 411 * MVEBU GPIO IRQ 412 * 413 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 414 * value of the line or the opposite value. 415 * 416 * Level IRQ handlers: DATA_IN is used directly as cause register. 417 * Interrupt are masked by LEVEL_MASK registers. 418 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 419 * Interrupt are masked by EDGE_MASK registers. 420 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 421 * the polarity to catch the next line transaction. 422 * This is a race condition that might not perfectly 423 * work on some use cases. 424 * 425 * Every eight GPIO lines are grouped (OR'ed) before going up to main 426 * cause register. 427 * 428 * EDGE cause mask 429 * data-in /--------| |-----| |----\ 430 * -----| |----- ---- to main cause reg 431 * X \----------------| |----/ 432 * polarity LEVEL mask 433 * 434 ****************************************************************************/ 435 436 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 437 { 438 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 439 struct irq_chip_type *ct = irq_data_get_chip_type(d); 440 struct mvebu_gpio_chip *mvchip = gc->private; 441 int pin; 442 u32 u; 443 444 pin = d->hwirq; 445 446 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & BIT(pin); 447 if (!u) 448 return -EINVAL; 449 450 type &= IRQ_TYPE_SENSE_MASK; 451 if (type == IRQ_TYPE_NONE) 452 return -EINVAL; 453 454 /* Check if we need to change chip and handler */ 455 if (!(ct->type & type)) 456 if (irq_setup_alt_chip(d, type)) 457 return -EINVAL; 458 459 /* 460 * Configure interrupt polarity. 461 */ 462 switch (type) { 463 case IRQ_TYPE_EDGE_RISING: 464 case IRQ_TYPE_LEVEL_HIGH: 465 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 466 u &= ~BIT(pin); 467 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 468 break; 469 case IRQ_TYPE_EDGE_FALLING: 470 case IRQ_TYPE_LEVEL_LOW: 471 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 472 u |= BIT(pin); 473 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 474 break; 475 case IRQ_TYPE_EDGE_BOTH: { 476 u32 v; 477 478 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^ 479 readl_relaxed(mvebu_gpioreg_data_in(mvchip)); 480 481 /* 482 * set initial polarity based on current input level 483 */ 484 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 485 if (v & BIT(pin)) 486 u |= BIT(pin); /* falling */ 487 else 488 u &= ~BIT(pin); /* rising */ 489 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 490 break; 491 } 492 } 493 return 0; 494 } 495 496 static void mvebu_gpio_irq_handler(struct irq_desc *desc) 497 { 498 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); 499 struct irq_chip *chip = irq_desc_get_chip(desc); 500 u32 cause, type; 501 int i; 502 503 if (mvchip == NULL) 504 return; 505 506 chained_irq_enter(chip, desc); 507 508 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & 509 readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); 510 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & 511 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); 512 513 for (i = 0; i < mvchip->chip.ngpio; i++) { 514 int irq; 515 516 irq = irq_find_mapping(mvchip->domain, i); 517 518 if (!(cause & BIT(i))) 519 continue; 520 521 type = irq_get_trigger_type(irq); 522 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 523 /* Swap polarity (race with GPIO line) */ 524 u32 polarity; 525 526 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 527 polarity ^= BIT(i); 528 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); 529 } 530 531 generic_handle_irq(irq); 532 } 533 534 chained_irq_exit(chip, desc); 535 } 536 537 /* 538 * Functions implementing the pwm_chip methods 539 */ 540 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) 541 { 542 return container_of(chip, struct mvebu_pwm, chip); 543 } 544 545 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 546 { 547 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 548 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 549 struct gpio_desc *desc; 550 unsigned long flags; 551 int ret = 0; 552 553 spin_lock_irqsave(&mvpwm->lock, flags); 554 555 if (mvpwm->gpiod) { 556 ret = -EBUSY; 557 } else { 558 desc = gpio_to_desc(mvchip->chip.base + pwm->hwpwm); 559 if (!desc) { 560 ret = -ENODEV; 561 goto out; 562 } 563 564 ret = gpiod_request(desc, "mvebu-pwm"); 565 if (ret) 566 goto out; 567 568 ret = gpiod_direction_output(desc, 0); 569 if (ret) { 570 gpiod_free(desc); 571 goto out; 572 } 573 574 mvpwm->gpiod = desc; 575 } 576 out: 577 spin_unlock_irqrestore(&mvpwm->lock, flags); 578 return ret; 579 } 580 581 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 582 { 583 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 584 unsigned long flags; 585 586 spin_lock_irqsave(&mvpwm->lock, flags); 587 gpiod_free(mvpwm->gpiod); 588 mvpwm->gpiod = NULL; 589 spin_unlock_irqrestore(&mvpwm->lock, flags); 590 } 591 592 static void mvebu_pwm_get_state(struct pwm_chip *chip, 593 struct pwm_device *pwm, 594 struct pwm_state *state) { 595 596 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 597 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 598 unsigned long long val; 599 unsigned long flags; 600 u32 u; 601 602 spin_lock_irqsave(&mvpwm->lock, flags); 603 604 val = (unsigned long long) 605 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm)); 606 val *= NSEC_PER_SEC; 607 do_div(val, mvpwm->clk_rate); 608 if (val > UINT_MAX) 609 state->duty_cycle = UINT_MAX; 610 else if (val) 611 state->duty_cycle = val; 612 else 613 state->duty_cycle = 1; 614 615 val = (unsigned long long) 616 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm)); 617 val *= NSEC_PER_SEC; 618 do_div(val, mvpwm->clk_rate); 619 if (val < state->duty_cycle) { 620 state->period = 1; 621 } else { 622 val -= state->duty_cycle; 623 if (val > UINT_MAX) 624 state->period = UINT_MAX; 625 else if (val) 626 state->period = val; 627 else 628 state->period = 1; 629 } 630 631 u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); 632 if (u) 633 state->enabled = true; 634 else 635 state->enabled = false; 636 637 spin_unlock_irqrestore(&mvpwm->lock, flags); 638 } 639 640 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 641 struct pwm_state *state) 642 { 643 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 644 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 645 unsigned long long val; 646 unsigned long flags; 647 unsigned int on, off; 648 649 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; 650 do_div(val, NSEC_PER_SEC); 651 if (val > UINT_MAX) 652 return -EINVAL; 653 if (val) 654 on = val; 655 else 656 on = 1; 657 658 val = (unsigned long long) mvpwm->clk_rate * 659 (state->period - state->duty_cycle); 660 do_div(val, NSEC_PER_SEC); 661 if (val > UINT_MAX) 662 return -EINVAL; 663 if (val) 664 off = val; 665 else 666 off = 1; 667 668 spin_lock_irqsave(&mvpwm->lock, flags); 669 670 writel_relaxed(on, mvebu_pwmreg_blink_on_duration(mvpwm)); 671 writel_relaxed(off, mvebu_pwmreg_blink_off_duration(mvpwm)); 672 if (state->enabled) 673 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); 674 else 675 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); 676 677 spin_unlock_irqrestore(&mvpwm->lock, flags); 678 679 return 0; 680 } 681 682 static const struct pwm_ops mvebu_pwm_ops = { 683 .request = mvebu_pwm_request, 684 .free = mvebu_pwm_free, 685 .get_state = mvebu_pwm_get_state, 686 .apply = mvebu_pwm_apply, 687 .owner = THIS_MODULE, 688 }; 689 690 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) 691 { 692 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 693 694 mvpwm->blink_select = 695 readl_relaxed(mvebu_gpioreg_blink_counter_select(mvchip)); 696 mvpwm->blink_on_duration = 697 readl_relaxed(mvebu_pwmreg_blink_on_duration(mvpwm)); 698 mvpwm->blink_off_duration = 699 readl_relaxed(mvebu_pwmreg_blink_off_duration(mvpwm)); 700 } 701 702 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) 703 { 704 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 705 706 writel_relaxed(mvpwm->blink_select, 707 mvebu_gpioreg_blink_counter_select(mvchip)); 708 writel_relaxed(mvpwm->blink_on_duration, 709 mvebu_pwmreg_blink_on_duration(mvpwm)); 710 writel_relaxed(mvpwm->blink_off_duration, 711 mvebu_pwmreg_blink_off_duration(mvpwm)); 712 } 713 714 static int mvebu_pwm_probe(struct platform_device *pdev, 715 struct mvebu_gpio_chip *mvchip, 716 int id) 717 { 718 struct device *dev = &pdev->dev; 719 struct mvebu_pwm *mvpwm; 720 struct resource *res; 721 u32 set; 722 723 if (!of_device_is_compatible(mvchip->chip.of_node, 724 "marvell,armada-370-xp-gpio")) 725 return 0; 726 727 if (IS_ERR(mvchip->clk)) 728 return PTR_ERR(mvchip->clk); 729 730 /* 731 * There are only two sets of PWM configuration registers for 732 * all the GPIO lines on those SoCs which this driver reserves 733 * for the first two GPIO chips. So if the resource is missing 734 * we can't treat it as an error. 735 */ 736 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm"); 737 if (!res) 738 return 0; 739 740 /* 741 * Use set A for lines of GPIO chip with id 0, B for GPIO chip 742 * with id 1. Don't allow further GPIO chips to be used for PWM. 743 */ 744 if (id == 0) 745 set = 0; 746 else if (id == 1) 747 set = U32_MAX; 748 else 749 return -EINVAL; 750 writel_relaxed(0, mvebu_gpioreg_blink_counter_select(mvchip)); 751 752 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); 753 if (!mvpwm) 754 return -ENOMEM; 755 mvchip->mvpwm = mvpwm; 756 mvpwm->mvchip = mvchip; 757 758 mvpwm->membase = devm_ioremap_resource(dev, res); 759 if (IS_ERR(mvpwm->membase)) 760 return PTR_ERR(mvpwm->membase); 761 762 mvpwm->clk_rate = clk_get_rate(mvchip->clk); 763 if (!mvpwm->clk_rate) { 764 dev_err(dev, "failed to get clock rate\n"); 765 return -EINVAL; 766 } 767 768 mvpwm->chip.dev = dev; 769 mvpwm->chip.ops = &mvebu_pwm_ops; 770 mvpwm->chip.npwm = mvchip->chip.ngpio; 771 772 spin_lock_init(&mvpwm->lock); 773 774 return pwmchip_add(&mvpwm->chip); 775 } 776 777 #ifdef CONFIG_DEBUG_FS 778 #include <linux/seq_file.h> 779 780 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 781 { 782 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 783 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 784 int i; 785 786 out = readl_relaxed(mvebu_gpioreg_out(mvchip)); 787 io_conf = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 788 blink = readl_relaxed(mvebu_gpioreg_blink(mvchip)); 789 in_pol = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 790 data_in = readl_relaxed(mvebu_gpioreg_data_in(mvchip)); 791 cause = readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)); 792 edg_msk = readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); 793 lvl_msk = readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); 794 795 for (i = 0; i < chip->ngpio; i++) { 796 const char *label; 797 u32 msk; 798 bool is_out; 799 800 label = gpiochip_is_requested(chip, i); 801 if (!label) 802 continue; 803 804 msk = BIT(i); 805 is_out = !(io_conf & msk); 806 807 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 808 809 if (is_out) { 810 seq_printf(s, " out %s %s\n", 811 out & msk ? "hi" : "lo", 812 blink & msk ? "(blink )" : ""); 813 continue; 814 } 815 816 seq_printf(s, " in %s (act %s) - IRQ", 817 (data_in ^ in_pol) & msk ? "hi" : "lo", 818 in_pol & msk ? "lo" : "hi"); 819 if (!((edg_msk | lvl_msk) & msk)) { 820 seq_puts(s, " disabled\n"); 821 continue; 822 } 823 if (edg_msk & msk) 824 seq_puts(s, " edge "); 825 if (lvl_msk & msk) 826 seq_puts(s, " level"); 827 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 828 } 829 } 830 #else 831 #define mvebu_gpio_dbg_show NULL 832 #endif 833 834 static const struct of_device_id mvebu_gpio_of_match[] = { 835 { 836 .compatible = "marvell,orion-gpio", 837 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 838 }, 839 { 840 .compatible = "marvell,mv78200-gpio", 841 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, 842 }, 843 { 844 .compatible = "marvell,armadaxp-gpio", 845 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 846 }, 847 { 848 .compatible = "marvell,armada-370-xp-gpio", 849 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 850 }, 851 { 852 /* sentinel */ 853 }, 854 }; 855 856 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) 857 { 858 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 859 int i; 860 861 mvchip->out_reg = readl(mvebu_gpioreg_out(mvchip)); 862 mvchip->io_conf_reg = readl(mvebu_gpioreg_io_conf(mvchip)); 863 mvchip->blink_en_reg = readl(mvebu_gpioreg_blink(mvchip)); 864 mvchip->in_pol_reg = readl(mvebu_gpioreg_in_pol(mvchip)); 865 866 switch (mvchip->soc_variant) { 867 case MVEBU_GPIO_SOC_VARIANT_ORION: 868 mvchip->edge_mask_regs[0] = 869 readl(mvchip->membase + GPIO_EDGE_MASK_OFF); 870 mvchip->level_mask_regs[0] = 871 readl(mvchip->membase + GPIO_LEVEL_MASK_OFF); 872 break; 873 case MVEBU_GPIO_SOC_VARIANT_MV78200: 874 for (i = 0; i < 2; i++) { 875 mvchip->edge_mask_regs[i] = 876 readl(mvchip->membase + 877 GPIO_EDGE_MASK_MV78200_OFF(i)); 878 mvchip->level_mask_regs[i] = 879 readl(mvchip->membase + 880 GPIO_LEVEL_MASK_MV78200_OFF(i)); 881 } 882 break; 883 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 884 for (i = 0; i < 4; i++) { 885 mvchip->edge_mask_regs[i] = 886 readl(mvchip->membase + 887 GPIO_EDGE_MASK_ARMADAXP_OFF(i)); 888 mvchip->level_mask_regs[i] = 889 readl(mvchip->membase + 890 GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); 891 } 892 break; 893 default: 894 BUG(); 895 } 896 897 if (IS_ENABLED(CONFIG_PWM)) 898 mvebu_pwm_suspend(mvchip); 899 900 return 0; 901 } 902 903 static int mvebu_gpio_resume(struct platform_device *pdev) 904 { 905 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 906 int i; 907 908 writel(mvchip->out_reg, mvebu_gpioreg_out(mvchip)); 909 writel(mvchip->io_conf_reg, mvebu_gpioreg_io_conf(mvchip)); 910 writel(mvchip->blink_en_reg, mvebu_gpioreg_blink(mvchip)); 911 writel(mvchip->in_pol_reg, mvebu_gpioreg_in_pol(mvchip)); 912 913 switch (mvchip->soc_variant) { 914 case MVEBU_GPIO_SOC_VARIANT_ORION: 915 writel(mvchip->edge_mask_regs[0], 916 mvchip->membase + GPIO_EDGE_MASK_OFF); 917 writel(mvchip->level_mask_regs[0], 918 mvchip->membase + GPIO_LEVEL_MASK_OFF); 919 break; 920 case MVEBU_GPIO_SOC_VARIANT_MV78200: 921 for (i = 0; i < 2; i++) { 922 writel(mvchip->edge_mask_regs[i], 923 mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(i)); 924 writel(mvchip->level_mask_regs[i], 925 mvchip->membase + 926 GPIO_LEVEL_MASK_MV78200_OFF(i)); 927 } 928 break; 929 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 930 for (i = 0; i < 4; i++) { 931 writel(mvchip->edge_mask_regs[i], 932 mvchip->membase + 933 GPIO_EDGE_MASK_ARMADAXP_OFF(i)); 934 writel(mvchip->level_mask_regs[i], 935 mvchip->membase + 936 GPIO_LEVEL_MASK_ARMADAXP_OFF(i)); 937 } 938 break; 939 default: 940 BUG(); 941 } 942 943 if (IS_ENABLED(CONFIG_PWM)) 944 mvebu_pwm_resume(mvchip); 945 946 return 0; 947 } 948 949 static int mvebu_gpio_probe(struct platform_device *pdev) 950 { 951 struct mvebu_gpio_chip *mvchip; 952 const struct of_device_id *match; 953 struct device_node *np = pdev->dev.of_node; 954 struct resource *res; 955 struct irq_chip_generic *gc; 956 struct irq_chip_type *ct; 957 unsigned int ngpios; 958 bool have_irqs; 959 int soc_variant; 960 int i, cpu, id; 961 int err; 962 963 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); 964 if (match) 965 soc_variant = (unsigned long) match->data; 966 else 967 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; 968 969 /* Some gpio controllers do not provide irq support */ 970 have_irqs = of_irq_count(np) != 0; 971 972 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), 973 GFP_KERNEL); 974 if (!mvchip) 975 return -ENOMEM; 976 977 platform_set_drvdata(pdev, mvchip); 978 979 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 980 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 981 return -ENODEV; 982 } 983 984 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 985 if (id < 0) { 986 dev_err(&pdev->dev, "Couldn't get OF id\n"); 987 return id; 988 } 989 990 mvchip->clk = devm_clk_get(&pdev->dev, NULL); 991 /* Not all SoCs require a clock.*/ 992 if (!IS_ERR(mvchip->clk)) 993 clk_prepare_enable(mvchip->clk); 994 995 mvchip->soc_variant = soc_variant; 996 mvchip->chip.label = dev_name(&pdev->dev); 997 mvchip->chip.parent = &pdev->dev; 998 mvchip->chip.request = gpiochip_generic_request; 999 mvchip->chip.free = gpiochip_generic_free; 1000 mvchip->chip.direction_input = mvebu_gpio_direction_input; 1001 mvchip->chip.get = mvebu_gpio_get; 1002 mvchip->chip.direction_output = mvebu_gpio_direction_output; 1003 mvchip->chip.set = mvebu_gpio_set; 1004 if (have_irqs) 1005 mvchip->chip.to_irq = mvebu_gpio_to_irq; 1006 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 1007 mvchip->chip.ngpio = ngpios; 1008 mvchip->chip.can_sleep = false; 1009 mvchip->chip.of_node = np; 1010 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; 1011 1012 spin_lock_init(&mvchip->lock); 1013 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1014 mvchip->membase = devm_ioremap_resource(&pdev->dev, res); 1015 if (IS_ERR(mvchip->membase)) 1016 return PTR_ERR(mvchip->membase); 1017 1018 /* 1019 * The Armada XP has a second range of registers for the 1020 * per-CPU registers 1021 */ 1022 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 1023 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1024 mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev, 1025 res); 1026 if (IS_ERR(mvchip->percpu_membase)) 1027 return PTR_ERR(mvchip->percpu_membase); 1028 } 1029 1030 /* 1031 * Mask and clear GPIO interrupts. 1032 */ 1033 switch (soc_variant) { 1034 case MVEBU_GPIO_SOC_VARIANT_ORION: 1035 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 1036 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); 1037 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); 1038 break; 1039 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1040 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 1041 for (cpu = 0; cpu < 2; cpu++) { 1042 writel_relaxed(0, mvchip->membase + 1043 GPIO_EDGE_MASK_MV78200_OFF(cpu)); 1044 writel_relaxed(0, mvchip->membase + 1045 GPIO_LEVEL_MASK_MV78200_OFF(cpu)); 1046 } 1047 break; 1048 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1049 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 1050 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); 1051 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); 1052 for (cpu = 0; cpu < 4; cpu++) { 1053 writel_relaxed(0, mvchip->percpu_membase + 1054 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu)); 1055 writel_relaxed(0, mvchip->percpu_membase + 1056 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)); 1057 writel_relaxed(0, mvchip->percpu_membase + 1058 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu)); 1059 } 1060 break; 1061 default: 1062 BUG(); 1063 } 1064 1065 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); 1066 1067 /* Some gpio controllers do not provide irq support */ 1068 if (!have_irqs) 1069 return 0; 1070 1071 mvchip->domain = 1072 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); 1073 if (!mvchip->domain) { 1074 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 1075 mvchip->chip.label); 1076 return -ENODEV; 1077 } 1078 1079 err = irq_alloc_domain_generic_chips( 1080 mvchip->domain, ngpios, 2, np->name, handle_level_irq, 1081 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); 1082 if (err) { 1083 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", 1084 mvchip->chip.label); 1085 goto err_domain; 1086 } 1087 1088 /* 1089 * NOTE: The common accessors cannot be used because of the percpu 1090 * access to the mask registers 1091 */ 1092 gc = irq_get_domain_generic_chip(mvchip->domain, 0); 1093 gc->private = mvchip; 1094 ct = &gc->chip_types[0]; 1095 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 1096 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 1097 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 1098 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1099 ct->chip.name = mvchip->chip.label; 1100 1101 ct = &gc->chip_types[1]; 1102 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 1103 ct->chip.irq_ack = mvebu_gpio_irq_ack; 1104 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 1105 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 1106 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1107 ct->handler = handle_edge_irq; 1108 ct->chip.name = mvchip->chip.label; 1109 1110 /* 1111 * Setup the interrupt handlers. Each chip can have up to 4 1112 * interrupt handlers, with each handler dealing with 8 GPIO 1113 * pins. 1114 */ 1115 for (i = 0; i < 4; i++) { 1116 int irq = platform_get_irq(pdev, i); 1117 1118 if (irq < 0) 1119 continue; 1120 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, 1121 mvchip); 1122 } 1123 1124 /* Armada 370/XP has simple PWM support for GPIO lines */ 1125 if (IS_ENABLED(CONFIG_PWM)) 1126 return mvebu_pwm_probe(pdev, mvchip, id); 1127 1128 return 0; 1129 1130 err_domain: 1131 irq_domain_remove(mvchip->domain); 1132 1133 return err; 1134 } 1135 1136 static struct platform_driver mvebu_gpio_driver = { 1137 .driver = { 1138 .name = "mvebu-gpio", 1139 .of_match_table = mvebu_gpio_of_match, 1140 }, 1141 .probe = mvebu_gpio_probe, 1142 .suspend = mvebu_gpio_suspend, 1143 .resume = mvebu_gpio_resume, 1144 }; 1145 builtin_platform_driver(mvebu_gpio_driver); 1146