1 /* 2 * GPIO driver for Marvell SoCs 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Andrew Lunn <andrew@lunn.ch> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 * 14 * This driver is a fairly straightforward GPIO driver for the 15 * complete family of Marvell EBU SoC platforms (Orion, Dove, 16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 17 * driver is the different register layout that exists between the 18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 19 * platforms (MV78200 from the Discovery family and the Armada 20 * XP). Therefore, this driver handles three variants of the GPIO 21 * block: 22 * - the basic variant, called "orion-gpio", with the simplest 23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 24 * non-SMP Discovery systems 25 * - the mv78200 variant for MV78200 Discovery systems. This variant 26 * turns the edge mask and level mask registers into CPU0 edge 27 * mask/level mask registers, and adds CPU1 edge mask/level mask 28 * registers. 29 * - the armadaxp variant for Armada XP systems. This variant keeps 30 * the normal cause/edge mask/level mask registers when the global 31 * interrupts are used, but adds per-CPU cause/edge mask/level mask 32 * registers n a separate memory area for the per-CPU GPIO 33 * interrupts. 34 */ 35 36 #include <linux/bitops.h> 37 #include <linux/clk.h> 38 #include <linux/err.h> 39 #include <linux/gpio/driver.h> 40 #include <linux/gpio/consumer.h> 41 #include <linux/gpio/machine.h> 42 #include <linux/init.h> 43 #include <linux/io.h> 44 #include <linux/irq.h> 45 #include <linux/irqchip/chained_irq.h> 46 #include <linux/irqdomain.h> 47 #include <linux/mfd/syscon.h> 48 #include <linux/of_device.h> 49 #include <linux/pinctrl/consumer.h> 50 #include <linux/platform_device.h> 51 #include <linux/pwm.h> 52 #include <linux/regmap.h> 53 #include <linux/slab.h> 54 55 /* 56 * GPIO unit register offsets. 57 */ 58 #define GPIO_OUT_OFF 0x0000 59 #define GPIO_IO_CONF_OFF 0x0004 60 #define GPIO_BLINK_EN_OFF 0x0008 61 #define GPIO_IN_POL_OFF 0x000c 62 #define GPIO_DATA_IN_OFF 0x0010 63 #define GPIO_EDGE_CAUSE_OFF 0x0014 64 #define GPIO_EDGE_MASK_OFF 0x0018 65 #define GPIO_LEVEL_MASK_OFF 0x001c 66 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020 67 68 /* 69 * PWM register offsets. 70 */ 71 #define PWM_BLINK_ON_DURATION_OFF 0x0 72 #define PWM_BLINK_OFF_DURATION_OFF 0x4 73 #define PWM_BLINK_COUNTER_B_OFF 0x8 74 75 /* Armada 8k variant gpios register offsets */ 76 #define AP80X_GPIO0_OFF_A8K 0x1040 77 #define CP11X_GPIO0_OFF_A8K 0x100 78 #define CP11X_GPIO1_OFF_A8K 0x140 79 80 /* The MV78200 has per-CPU registers for edge mask and level mask */ 81 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 82 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 83 84 /* 85 * The Armada XP has per-CPU registers for interrupt cause, interrupt 86 * mask and interrupt level mask. Those are in percpu_regs range. 87 */ 88 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 89 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 90 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 91 92 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 93 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 94 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 95 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4 96 97 #define MVEBU_MAX_GPIO_PER_BANK 32 98 99 struct mvebu_pwm { 100 struct regmap *regs; 101 u32 offset; 102 unsigned long clk_rate; 103 struct gpio_desc *gpiod; 104 struct pwm_chip chip; 105 spinlock_t lock; 106 struct mvebu_gpio_chip *mvchip; 107 108 /* Used to preserve GPIO/PWM registers across suspend/resume */ 109 u32 blink_select; 110 u32 blink_on_duration; 111 u32 blink_off_duration; 112 }; 113 114 struct mvebu_gpio_chip { 115 struct gpio_chip chip; 116 struct regmap *regs; 117 u32 offset; 118 struct regmap *percpu_regs; 119 int irqbase; 120 struct irq_domain *domain; 121 int soc_variant; 122 123 /* Used for PWM support */ 124 struct clk *clk; 125 struct mvebu_pwm *mvpwm; 126 127 /* Used to preserve GPIO registers across suspend/resume */ 128 u32 out_reg; 129 u32 io_conf_reg; 130 u32 blink_en_reg; 131 u32 in_pol_reg; 132 u32 edge_mask_regs[4]; 133 u32 level_mask_regs[4]; 134 }; 135 136 /* 137 * Functions returning addresses of individual registers for a given 138 * GPIO controller. 139 */ 140 141 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip, 142 struct regmap **map, unsigned int *offset) 143 { 144 int cpu; 145 146 switch (mvchip->soc_variant) { 147 case MVEBU_GPIO_SOC_VARIANT_ORION: 148 case MVEBU_GPIO_SOC_VARIANT_MV78200: 149 case MVEBU_GPIO_SOC_VARIANT_A8K: 150 *map = mvchip->regs; 151 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; 152 break; 153 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 154 cpu = smp_processor_id(); 155 *map = mvchip->percpu_regs; 156 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 157 break; 158 default: 159 BUG(); 160 } 161 } 162 163 static u32 164 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip) 165 { 166 struct regmap *map; 167 unsigned int offset; 168 u32 val; 169 170 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 171 regmap_read(map, offset, &val); 172 173 return val; 174 } 175 176 static void 177 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) 178 { 179 struct regmap *map; 180 unsigned int offset; 181 182 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 183 regmap_write(map, offset, val); 184 } 185 186 static inline void 187 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip, 188 struct regmap **map, unsigned int *offset) 189 { 190 int cpu; 191 192 switch (mvchip->soc_variant) { 193 case MVEBU_GPIO_SOC_VARIANT_ORION: 194 case MVEBU_GPIO_SOC_VARIANT_A8K: 195 *map = mvchip->regs; 196 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; 197 break; 198 case MVEBU_GPIO_SOC_VARIANT_MV78200: 199 cpu = smp_processor_id(); 200 *map = mvchip->regs; 201 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); 202 break; 203 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 204 cpu = smp_processor_id(); 205 *map = mvchip->percpu_regs; 206 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 207 break; 208 default: 209 BUG(); 210 } 211 } 212 213 static u32 214 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip) 215 { 216 struct regmap *map; 217 unsigned int offset; 218 u32 val; 219 220 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 221 regmap_read(map, offset, &val); 222 223 return val; 224 } 225 226 static void 227 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) 228 { 229 struct regmap *map; 230 unsigned int offset; 231 232 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 233 regmap_write(map, offset, val); 234 } 235 236 static void 237 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip, 238 struct regmap **map, unsigned int *offset) 239 { 240 int cpu; 241 242 switch (mvchip->soc_variant) { 243 case MVEBU_GPIO_SOC_VARIANT_ORION: 244 case MVEBU_GPIO_SOC_VARIANT_A8K: 245 *map = mvchip->regs; 246 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; 247 break; 248 case MVEBU_GPIO_SOC_VARIANT_MV78200: 249 cpu = smp_processor_id(); 250 *map = mvchip->regs; 251 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); 252 break; 253 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 254 cpu = smp_processor_id(); 255 *map = mvchip->percpu_regs; 256 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 257 break; 258 default: 259 BUG(); 260 } 261 } 262 263 static u32 264 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip) 265 { 266 struct regmap *map; 267 unsigned int offset; 268 u32 val; 269 270 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 271 regmap_read(map, offset, &val); 272 273 return val; 274 } 275 276 static void 277 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) 278 { 279 struct regmap *map; 280 unsigned int offset; 281 282 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 283 regmap_write(map, offset, val); 284 } 285 286 /* 287 * Functions returning offsets of individual registers for a given 288 * PWM controller. 289 */ 290 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) 291 { 292 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; 293 } 294 295 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) 296 { 297 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; 298 } 299 300 /* 301 * Functions implementing the gpio_chip methods 302 */ 303 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 304 { 305 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 306 307 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 308 BIT(pin), value ? BIT(pin) : 0); 309 } 310 311 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) 312 { 313 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 314 u32 u; 315 316 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 317 318 if (u & BIT(pin)) { 319 u32 data_in, in_pol; 320 321 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, 322 &data_in); 323 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 324 &in_pol); 325 u = data_in ^ in_pol; 326 } else { 327 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); 328 } 329 330 return (u >> pin) & 1; 331 } 332 333 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, 334 int value) 335 { 336 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 337 338 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 339 BIT(pin), value ? BIT(pin) : 0); 340 } 341 342 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) 343 { 344 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 345 int ret; 346 347 /* 348 * Check with the pinctrl driver whether this pin is usable as 349 * an input GPIO 350 */ 351 ret = pinctrl_gpio_direction_input(chip->base + pin); 352 if (ret) 353 return ret; 354 355 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 356 BIT(pin), BIT(pin)); 357 358 return 0; 359 } 360 361 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, 362 int value) 363 { 364 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 365 int ret; 366 367 /* 368 * Check with the pinctrl driver whether this pin is usable as 369 * an output GPIO 370 */ 371 ret = pinctrl_gpio_direction_output(chip->base + pin); 372 if (ret) 373 return ret; 374 375 mvebu_gpio_blink(chip, pin, 0); 376 mvebu_gpio_set(chip, pin, value); 377 378 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 379 BIT(pin), 0); 380 381 return 0; 382 } 383 384 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 385 { 386 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 387 u32 u; 388 389 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 390 391 if (u & BIT(pin)) 392 return GPIO_LINE_DIRECTION_IN; 393 394 return GPIO_LINE_DIRECTION_OUT; 395 } 396 397 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) 398 { 399 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 400 401 return irq_create_mapping(mvchip->domain, pin); 402 } 403 404 /* 405 * Functions implementing the irq_chip methods 406 */ 407 static void mvebu_gpio_irq_ack(struct irq_data *d) 408 { 409 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 410 struct mvebu_gpio_chip *mvchip = gc->private; 411 u32 mask = d->mask; 412 413 irq_gc_lock(gc); 414 mvebu_gpio_write_edge_cause(mvchip, ~mask); 415 irq_gc_unlock(gc); 416 } 417 418 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 419 { 420 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 421 struct mvebu_gpio_chip *mvchip = gc->private; 422 struct irq_chip_type *ct = irq_data_get_chip_type(d); 423 u32 mask = d->mask; 424 425 irq_gc_lock(gc); 426 ct->mask_cache_priv &= ~mask; 427 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 428 irq_gc_unlock(gc); 429 } 430 431 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 432 { 433 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 434 struct mvebu_gpio_chip *mvchip = gc->private; 435 struct irq_chip_type *ct = irq_data_get_chip_type(d); 436 u32 mask = d->mask; 437 438 irq_gc_lock(gc); 439 mvebu_gpio_write_edge_cause(mvchip, ~mask); 440 ct->mask_cache_priv |= mask; 441 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 442 irq_gc_unlock(gc); 443 } 444 445 static void mvebu_gpio_level_irq_mask(struct irq_data *d) 446 { 447 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 448 struct mvebu_gpio_chip *mvchip = gc->private; 449 struct irq_chip_type *ct = irq_data_get_chip_type(d); 450 u32 mask = d->mask; 451 452 irq_gc_lock(gc); 453 ct->mask_cache_priv &= ~mask; 454 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 455 irq_gc_unlock(gc); 456 } 457 458 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 459 { 460 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 461 struct mvebu_gpio_chip *mvchip = gc->private; 462 struct irq_chip_type *ct = irq_data_get_chip_type(d); 463 u32 mask = d->mask; 464 465 irq_gc_lock(gc); 466 ct->mask_cache_priv |= mask; 467 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 468 irq_gc_unlock(gc); 469 } 470 471 /***************************************************************************** 472 * MVEBU GPIO IRQ 473 * 474 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 475 * value of the line or the opposite value. 476 * 477 * Level IRQ handlers: DATA_IN is used directly as cause register. 478 * Interrupt are masked by LEVEL_MASK registers. 479 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 480 * Interrupt are masked by EDGE_MASK registers. 481 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 482 * the polarity to catch the next line transaction. 483 * This is a race condition that might not perfectly 484 * work on some use cases. 485 * 486 * Every eight GPIO lines are grouped (OR'ed) before going up to main 487 * cause register. 488 * 489 * EDGE cause mask 490 * data-in /--------| |-----| |----\ 491 * -----| |----- ---- to main cause reg 492 * X \----------------| |----/ 493 * polarity LEVEL mask 494 * 495 ****************************************************************************/ 496 497 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 498 { 499 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 500 struct irq_chip_type *ct = irq_data_get_chip_type(d); 501 struct mvebu_gpio_chip *mvchip = gc->private; 502 int pin; 503 u32 u; 504 505 pin = d->hwirq; 506 507 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 508 if ((u & BIT(pin)) == 0) 509 return -EINVAL; 510 511 type &= IRQ_TYPE_SENSE_MASK; 512 if (type == IRQ_TYPE_NONE) 513 return -EINVAL; 514 515 /* Check if we need to change chip and handler */ 516 if (!(ct->type & type)) 517 if (irq_setup_alt_chip(d, type)) 518 return -EINVAL; 519 520 /* 521 * Configure interrupt polarity. 522 */ 523 switch (type) { 524 case IRQ_TYPE_EDGE_RISING: 525 case IRQ_TYPE_LEVEL_HIGH: 526 regmap_update_bits(mvchip->regs, 527 GPIO_IN_POL_OFF + mvchip->offset, 528 BIT(pin), 0); 529 break; 530 case IRQ_TYPE_EDGE_FALLING: 531 case IRQ_TYPE_LEVEL_LOW: 532 regmap_update_bits(mvchip->regs, 533 GPIO_IN_POL_OFF + mvchip->offset, 534 BIT(pin), BIT(pin)); 535 break; 536 case IRQ_TYPE_EDGE_BOTH: { 537 u32 data_in, in_pol, val; 538 539 regmap_read(mvchip->regs, 540 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 541 regmap_read(mvchip->regs, 542 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 543 544 /* 545 * set initial polarity based on current input level 546 */ 547 if ((data_in ^ in_pol) & BIT(pin)) 548 val = BIT(pin); /* falling */ 549 else 550 val = 0; /* raising */ 551 552 regmap_update_bits(mvchip->regs, 553 GPIO_IN_POL_OFF + mvchip->offset, 554 BIT(pin), val); 555 break; 556 } 557 } 558 return 0; 559 } 560 561 static void mvebu_gpio_irq_handler(struct irq_desc *desc) 562 { 563 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); 564 struct irq_chip *chip = irq_desc_get_chip(desc); 565 u32 cause, type, data_in, level_mask, edge_cause, edge_mask; 566 int i; 567 568 if (mvchip == NULL) 569 return; 570 571 chained_irq_enter(chip, desc); 572 573 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 574 level_mask = mvebu_gpio_read_level_mask(mvchip); 575 edge_cause = mvebu_gpio_read_edge_cause(mvchip); 576 edge_mask = mvebu_gpio_read_edge_mask(mvchip); 577 578 cause = (data_in & level_mask) | (edge_cause & edge_mask); 579 580 for (i = 0; i < mvchip->chip.ngpio; i++) { 581 int irq; 582 583 irq = irq_find_mapping(mvchip->domain, i); 584 585 if (!(cause & BIT(i))) 586 continue; 587 588 type = irq_get_trigger_type(irq); 589 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 590 /* Swap polarity (race with GPIO line) */ 591 u32 polarity; 592 593 regmap_read(mvchip->regs, 594 GPIO_IN_POL_OFF + mvchip->offset, 595 &polarity); 596 polarity ^= BIT(i); 597 regmap_write(mvchip->regs, 598 GPIO_IN_POL_OFF + mvchip->offset, 599 polarity); 600 } 601 602 generic_handle_irq(irq); 603 } 604 605 chained_irq_exit(chip, desc); 606 } 607 608 static const struct regmap_config mvebu_gpio_regmap_config = { 609 .reg_bits = 32, 610 .reg_stride = 4, 611 .val_bits = 32, 612 .fast_io = true, 613 }; 614 615 /* 616 * Functions implementing the pwm_chip methods 617 */ 618 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) 619 { 620 return container_of(chip, struct mvebu_pwm, chip); 621 } 622 623 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 624 { 625 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 626 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 627 struct gpio_desc *desc; 628 unsigned long flags; 629 int ret = 0; 630 631 spin_lock_irqsave(&mvpwm->lock, flags); 632 633 if (mvpwm->gpiod) { 634 ret = -EBUSY; 635 } else { 636 desc = gpiochip_request_own_desc(&mvchip->chip, 637 pwm->hwpwm, "mvebu-pwm", 638 GPIO_ACTIVE_HIGH, 639 GPIOD_OUT_LOW); 640 if (IS_ERR(desc)) { 641 ret = PTR_ERR(desc); 642 goto out; 643 } 644 645 mvpwm->gpiod = desc; 646 } 647 out: 648 spin_unlock_irqrestore(&mvpwm->lock, flags); 649 return ret; 650 } 651 652 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 653 { 654 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 655 unsigned long flags; 656 657 spin_lock_irqsave(&mvpwm->lock, flags); 658 gpiochip_free_own_desc(mvpwm->gpiod); 659 mvpwm->gpiod = NULL; 660 spin_unlock_irqrestore(&mvpwm->lock, flags); 661 } 662 663 static void mvebu_pwm_get_state(struct pwm_chip *chip, 664 struct pwm_device *pwm, 665 struct pwm_state *state) { 666 667 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 668 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 669 unsigned long long val; 670 unsigned long flags; 671 u32 u; 672 673 spin_lock_irqsave(&mvpwm->lock, flags); 674 675 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); 676 /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */ 677 if (u > 0) 678 val = u; 679 else 680 val = UINT_MAX + 1ULL; 681 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, 682 mvpwm->clk_rate); 683 684 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); 685 /* period = on + off duration */ 686 if (u > 0) 687 val += u; 688 else 689 val += UINT_MAX + 1ULL; 690 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); 691 692 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); 693 if (u) 694 state->enabled = true; 695 else 696 state->enabled = false; 697 698 spin_unlock_irqrestore(&mvpwm->lock, flags); 699 } 700 701 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 702 const struct pwm_state *state) 703 { 704 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 705 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 706 unsigned long long val; 707 unsigned long flags; 708 unsigned int on, off; 709 710 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; 711 do_div(val, NSEC_PER_SEC); 712 if (val > UINT_MAX + 1ULL) 713 return -EINVAL; 714 /* 715 * Zero on/off values don't work as expected. Experimentation shows 716 * that zero value is treated as 2^32. This behavior is not documented. 717 */ 718 if (val == UINT_MAX + 1ULL) 719 on = 0; 720 else if (val) 721 on = val; 722 else 723 on = 1; 724 725 val = (unsigned long long) mvpwm->clk_rate * state->period; 726 do_div(val, NSEC_PER_SEC); 727 val -= on; 728 if (val > UINT_MAX + 1ULL) 729 return -EINVAL; 730 if (val == UINT_MAX + 1ULL) 731 off = 0; 732 else if (val) 733 off = val; 734 else 735 off = 1; 736 737 spin_lock_irqsave(&mvpwm->lock, flags); 738 739 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); 740 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); 741 if (state->enabled) 742 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); 743 else 744 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); 745 746 spin_unlock_irqrestore(&mvpwm->lock, flags); 747 748 return 0; 749 } 750 751 static const struct pwm_ops mvebu_pwm_ops = { 752 .request = mvebu_pwm_request, 753 .free = mvebu_pwm_free, 754 .get_state = mvebu_pwm_get_state, 755 .apply = mvebu_pwm_apply, 756 .owner = THIS_MODULE, 757 }; 758 759 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) 760 { 761 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 762 763 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 764 &mvpwm->blink_select); 765 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), 766 &mvpwm->blink_on_duration); 767 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), 768 &mvpwm->blink_off_duration); 769 } 770 771 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) 772 { 773 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 774 775 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 776 mvpwm->blink_select); 777 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), 778 mvpwm->blink_on_duration); 779 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), 780 mvpwm->blink_off_duration); 781 } 782 783 static int mvebu_pwm_probe(struct platform_device *pdev, 784 struct mvebu_gpio_chip *mvchip, 785 int id) 786 { 787 struct device *dev = &pdev->dev; 788 struct mvebu_pwm *mvpwm; 789 void __iomem *base; 790 u32 offset; 791 u32 set; 792 793 if (of_device_is_compatible(mvchip->chip.of_node, 794 "marvell,armada-370-gpio")) { 795 /* 796 * There are only two sets of PWM configuration registers for 797 * all the GPIO lines on those SoCs which this driver reserves 798 * for the first two GPIO chips. So if the resource is missing 799 * we can't treat it as an error. 800 */ 801 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) 802 return 0; 803 offset = 0; 804 } else if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { 805 int ret = of_property_read_u32(dev->of_node, 806 "marvell,pwm-offset", &offset); 807 if (ret < 0) 808 return 0; 809 } else { 810 return 0; 811 } 812 813 if (IS_ERR(mvchip->clk)) 814 return PTR_ERR(mvchip->clk); 815 816 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); 817 if (!mvpwm) 818 return -ENOMEM; 819 mvchip->mvpwm = mvpwm; 820 mvpwm->mvchip = mvchip; 821 mvpwm->offset = offset; 822 823 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { 824 mvpwm->regs = mvchip->regs; 825 826 switch (mvchip->offset) { 827 case AP80X_GPIO0_OFF_A8K: 828 case CP11X_GPIO0_OFF_A8K: 829 /* Blink counter A */ 830 set = 0; 831 break; 832 case CP11X_GPIO1_OFF_A8K: 833 /* Blink counter B */ 834 set = U32_MAX; 835 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; 836 break; 837 default: 838 return -EINVAL; 839 } 840 } else { 841 base = devm_platform_ioremap_resource_byname(pdev, "pwm"); 842 if (IS_ERR(base)) 843 return PTR_ERR(base); 844 845 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, 846 &mvebu_gpio_regmap_config); 847 if (IS_ERR(mvpwm->regs)) 848 return PTR_ERR(mvpwm->regs); 849 850 /* 851 * Use set A for lines of GPIO chip with id 0, B for GPIO chip 852 * with id 1. Don't allow further GPIO chips to be used for PWM. 853 */ 854 if (id == 0) 855 set = 0; 856 else if (id == 1) 857 set = U32_MAX; 858 else 859 return -EINVAL; 860 } 861 862 regmap_write(mvchip->regs, 863 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); 864 865 mvpwm->clk_rate = clk_get_rate(mvchip->clk); 866 if (!mvpwm->clk_rate) { 867 dev_err(dev, "failed to get clock rate\n"); 868 return -EINVAL; 869 } 870 871 mvpwm->chip.dev = dev; 872 mvpwm->chip.ops = &mvebu_pwm_ops; 873 mvpwm->chip.npwm = mvchip->chip.ngpio; 874 /* 875 * There may already be some PWM allocated, so we can't force 876 * mvpwm->chip.base to a fixed point like mvchip->chip.base. 877 * So, we let pwmchip_add() do the numbering and take the next free 878 * region. 879 */ 880 mvpwm->chip.base = -1; 881 882 spin_lock_init(&mvpwm->lock); 883 884 return pwmchip_add(&mvpwm->chip); 885 } 886 887 #ifdef CONFIG_DEBUG_FS 888 #include <linux/seq_file.h> 889 890 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 891 { 892 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 893 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 894 const char *label; 895 int i; 896 897 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); 898 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); 899 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); 900 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 901 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 902 cause = mvebu_gpio_read_edge_cause(mvchip); 903 edg_msk = mvebu_gpio_read_edge_mask(mvchip); 904 lvl_msk = mvebu_gpio_read_level_mask(mvchip); 905 906 for_each_requested_gpio(chip, i, label) { 907 u32 msk; 908 bool is_out; 909 910 msk = BIT(i); 911 is_out = !(io_conf & msk); 912 913 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 914 915 if (is_out) { 916 seq_printf(s, " out %s %s\n", 917 out & msk ? "hi" : "lo", 918 blink & msk ? "(blink )" : ""); 919 continue; 920 } 921 922 seq_printf(s, " in %s (act %s) - IRQ", 923 (data_in ^ in_pol) & msk ? "hi" : "lo", 924 in_pol & msk ? "lo" : "hi"); 925 if (!((edg_msk | lvl_msk) & msk)) { 926 seq_puts(s, " disabled\n"); 927 continue; 928 } 929 if (edg_msk & msk) 930 seq_puts(s, " edge "); 931 if (lvl_msk & msk) 932 seq_puts(s, " level"); 933 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 934 } 935 } 936 #else 937 #define mvebu_gpio_dbg_show NULL 938 #endif 939 940 static const struct of_device_id mvebu_gpio_of_match[] = { 941 { 942 .compatible = "marvell,orion-gpio", 943 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 944 }, 945 { 946 .compatible = "marvell,mv78200-gpio", 947 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, 948 }, 949 { 950 .compatible = "marvell,armadaxp-gpio", 951 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 952 }, 953 { 954 .compatible = "marvell,armada-370-gpio", 955 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 956 }, 957 { 958 .compatible = "marvell,armada-8k-gpio", 959 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K, 960 }, 961 { 962 /* sentinel */ 963 }, 964 }; 965 966 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) 967 { 968 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 969 int i; 970 971 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 972 &mvchip->out_reg); 973 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 974 &mvchip->io_conf_reg); 975 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 976 &mvchip->blink_en_reg); 977 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 978 &mvchip->in_pol_reg); 979 980 switch (mvchip->soc_variant) { 981 case MVEBU_GPIO_SOC_VARIANT_ORION: 982 case MVEBU_GPIO_SOC_VARIANT_A8K: 983 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 984 &mvchip->edge_mask_regs[0]); 985 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 986 &mvchip->level_mask_regs[0]); 987 break; 988 case MVEBU_GPIO_SOC_VARIANT_MV78200: 989 for (i = 0; i < 2; i++) { 990 regmap_read(mvchip->regs, 991 GPIO_EDGE_MASK_MV78200_OFF(i), 992 &mvchip->edge_mask_regs[i]); 993 regmap_read(mvchip->regs, 994 GPIO_LEVEL_MASK_MV78200_OFF(i), 995 &mvchip->level_mask_regs[i]); 996 } 997 break; 998 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 999 for (i = 0; i < 4; i++) { 1000 regmap_read(mvchip->regs, 1001 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 1002 &mvchip->edge_mask_regs[i]); 1003 regmap_read(mvchip->regs, 1004 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 1005 &mvchip->level_mask_regs[i]); 1006 } 1007 break; 1008 default: 1009 BUG(); 1010 } 1011 1012 if (IS_ENABLED(CONFIG_PWM)) 1013 mvebu_pwm_suspend(mvchip); 1014 1015 return 0; 1016 } 1017 1018 static int mvebu_gpio_resume(struct platform_device *pdev) 1019 { 1020 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 1021 int i; 1022 1023 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 1024 mvchip->out_reg); 1025 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 1026 mvchip->io_conf_reg); 1027 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 1028 mvchip->blink_en_reg); 1029 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 1030 mvchip->in_pol_reg); 1031 1032 switch (mvchip->soc_variant) { 1033 case MVEBU_GPIO_SOC_VARIANT_ORION: 1034 case MVEBU_GPIO_SOC_VARIANT_A8K: 1035 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 1036 mvchip->edge_mask_regs[0]); 1037 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 1038 mvchip->level_mask_regs[0]); 1039 break; 1040 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1041 for (i = 0; i < 2; i++) { 1042 regmap_write(mvchip->regs, 1043 GPIO_EDGE_MASK_MV78200_OFF(i), 1044 mvchip->edge_mask_regs[i]); 1045 regmap_write(mvchip->regs, 1046 GPIO_LEVEL_MASK_MV78200_OFF(i), 1047 mvchip->level_mask_regs[i]); 1048 } 1049 break; 1050 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1051 for (i = 0; i < 4; i++) { 1052 regmap_write(mvchip->regs, 1053 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 1054 mvchip->edge_mask_regs[i]); 1055 regmap_write(mvchip->regs, 1056 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 1057 mvchip->level_mask_regs[i]); 1058 } 1059 break; 1060 default: 1061 BUG(); 1062 } 1063 1064 if (IS_ENABLED(CONFIG_PWM)) 1065 mvebu_pwm_resume(mvchip); 1066 1067 return 0; 1068 } 1069 1070 static int mvebu_gpio_probe_raw(struct platform_device *pdev, 1071 struct mvebu_gpio_chip *mvchip) 1072 { 1073 void __iomem *base; 1074 1075 base = devm_platform_ioremap_resource(pdev, 0); 1076 if (IS_ERR(base)) 1077 return PTR_ERR(base); 1078 1079 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, 1080 &mvebu_gpio_regmap_config); 1081 if (IS_ERR(mvchip->regs)) 1082 return PTR_ERR(mvchip->regs); 1083 1084 /* 1085 * For the legacy SoCs, the regmap directly maps to the GPIO 1086 * registers, so no offset is needed. 1087 */ 1088 mvchip->offset = 0; 1089 1090 /* 1091 * The Armada XP has a second range of registers for the 1092 * per-CPU registers 1093 */ 1094 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 1095 base = devm_platform_ioremap_resource(pdev, 1); 1096 if (IS_ERR(base)) 1097 return PTR_ERR(base); 1098 1099 mvchip->percpu_regs = 1100 devm_regmap_init_mmio(&pdev->dev, base, 1101 &mvebu_gpio_regmap_config); 1102 if (IS_ERR(mvchip->percpu_regs)) 1103 return PTR_ERR(mvchip->percpu_regs); 1104 } 1105 1106 return 0; 1107 } 1108 1109 static int mvebu_gpio_probe_syscon(struct platform_device *pdev, 1110 struct mvebu_gpio_chip *mvchip) 1111 { 1112 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); 1113 if (IS_ERR(mvchip->regs)) 1114 return PTR_ERR(mvchip->regs); 1115 1116 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) 1117 return -EINVAL; 1118 1119 return 0; 1120 } 1121 1122 static int mvebu_gpio_probe(struct platform_device *pdev) 1123 { 1124 struct mvebu_gpio_chip *mvchip; 1125 const struct of_device_id *match; 1126 struct device_node *np = pdev->dev.of_node; 1127 struct irq_chip_generic *gc; 1128 struct irq_chip_type *ct; 1129 unsigned int ngpios; 1130 bool have_irqs; 1131 int soc_variant; 1132 int i, cpu, id; 1133 int err; 1134 1135 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); 1136 if (match) 1137 soc_variant = (unsigned long) match->data; 1138 else 1139 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; 1140 1141 /* Some gpio controllers do not provide irq support */ 1142 err = platform_irq_count(pdev); 1143 if (err < 0) 1144 return err; 1145 1146 have_irqs = err != 0; 1147 1148 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), 1149 GFP_KERNEL); 1150 if (!mvchip) 1151 return -ENOMEM; 1152 1153 platform_set_drvdata(pdev, mvchip); 1154 1155 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 1156 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 1157 return -ENODEV; 1158 } 1159 1160 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 1161 if (id < 0) { 1162 dev_err(&pdev->dev, "Couldn't get OF id\n"); 1163 return id; 1164 } 1165 1166 mvchip->clk = devm_clk_get(&pdev->dev, NULL); 1167 /* Not all SoCs require a clock.*/ 1168 if (!IS_ERR(mvchip->clk)) 1169 clk_prepare_enable(mvchip->clk); 1170 1171 mvchip->soc_variant = soc_variant; 1172 mvchip->chip.label = dev_name(&pdev->dev); 1173 mvchip->chip.parent = &pdev->dev; 1174 mvchip->chip.request = gpiochip_generic_request; 1175 mvchip->chip.free = gpiochip_generic_free; 1176 mvchip->chip.get_direction = mvebu_gpio_get_direction; 1177 mvchip->chip.direction_input = mvebu_gpio_direction_input; 1178 mvchip->chip.get = mvebu_gpio_get; 1179 mvchip->chip.direction_output = mvebu_gpio_direction_output; 1180 mvchip->chip.set = mvebu_gpio_set; 1181 if (have_irqs) 1182 mvchip->chip.to_irq = mvebu_gpio_to_irq; 1183 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 1184 mvchip->chip.ngpio = ngpios; 1185 mvchip->chip.can_sleep = false; 1186 mvchip->chip.of_node = np; 1187 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; 1188 1189 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) 1190 err = mvebu_gpio_probe_syscon(pdev, mvchip); 1191 else 1192 err = mvebu_gpio_probe_raw(pdev, mvchip); 1193 1194 if (err) 1195 return err; 1196 1197 /* 1198 * Mask and clear GPIO interrupts. 1199 */ 1200 switch (soc_variant) { 1201 case MVEBU_GPIO_SOC_VARIANT_ORION: 1202 case MVEBU_GPIO_SOC_VARIANT_A8K: 1203 regmap_write(mvchip->regs, 1204 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); 1205 regmap_write(mvchip->regs, 1206 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); 1207 regmap_write(mvchip->regs, 1208 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); 1209 break; 1210 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1211 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1212 for (cpu = 0; cpu < 2; cpu++) { 1213 regmap_write(mvchip->regs, 1214 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); 1215 regmap_write(mvchip->regs, 1216 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); 1217 } 1218 break; 1219 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1220 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1221 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); 1222 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); 1223 for (cpu = 0; cpu < 4; cpu++) { 1224 regmap_write(mvchip->percpu_regs, 1225 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); 1226 regmap_write(mvchip->percpu_regs, 1227 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); 1228 regmap_write(mvchip->percpu_regs, 1229 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); 1230 } 1231 break; 1232 default: 1233 BUG(); 1234 } 1235 1236 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); 1237 1238 /* Some MVEBU SoCs have simple PWM support for GPIO lines */ 1239 if (IS_ENABLED(CONFIG_PWM)) { 1240 err = mvebu_pwm_probe(pdev, mvchip, id); 1241 if (err) 1242 return err; 1243 } 1244 1245 /* Some gpio controllers do not provide irq support */ 1246 if (!have_irqs) 1247 return 0; 1248 1249 mvchip->domain = 1250 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); 1251 if (!mvchip->domain) { 1252 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 1253 mvchip->chip.label); 1254 err = -ENODEV; 1255 goto err_pwm; 1256 } 1257 1258 err = irq_alloc_domain_generic_chips( 1259 mvchip->domain, ngpios, 2, np->name, handle_level_irq, 1260 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); 1261 if (err) { 1262 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", 1263 mvchip->chip.label); 1264 goto err_domain; 1265 } 1266 1267 /* 1268 * NOTE: The common accessors cannot be used because of the percpu 1269 * access to the mask registers 1270 */ 1271 gc = irq_get_domain_generic_chip(mvchip->domain, 0); 1272 gc->private = mvchip; 1273 ct = &gc->chip_types[0]; 1274 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 1275 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 1276 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 1277 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1278 ct->chip.name = mvchip->chip.label; 1279 1280 ct = &gc->chip_types[1]; 1281 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 1282 ct->chip.irq_ack = mvebu_gpio_irq_ack; 1283 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 1284 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 1285 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1286 ct->handler = handle_edge_irq; 1287 ct->chip.name = mvchip->chip.label; 1288 1289 /* 1290 * Setup the interrupt handlers. Each chip can have up to 4 1291 * interrupt handlers, with each handler dealing with 8 GPIO 1292 * pins. 1293 */ 1294 for (i = 0; i < 4; i++) { 1295 int irq = platform_get_irq_optional(pdev, i); 1296 1297 if (irq < 0) 1298 continue; 1299 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, 1300 mvchip); 1301 } 1302 1303 return 0; 1304 1305 err_domain: 1306 irq_domain_remove(mvchip->domain); 1307 err_pwm: 1308 pwmchip_remove(&mvchip->mvpwm->chip); 1309 1310 return err; 1311 } 1312 1313 static struct platform_driver mvebu_gpio_driver = { 1314 .driver = { 1315 .name = "mvebu-gpio", 1316 .of_match_table = mvebu_gpio_of_match, 1317 }, 1318 .probe = mvebu_gpio_probe, 1319 .suspend = mvebu_gpio_suspend, 1320 .resume = mvebu_gpio_resume, 1321 }; 1322 builtin_platform_driver(mvebu_gpio_driver); 1323