1 /* 2 * GPIO driver for Marvell SoCs 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Andrew Lunn <andrew@lunn.ch> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 * 14 * This driver is a fairly straightforward GPIO driver for the 15 * complete family of Marvell EBU SoC platforms (Orion, Dove, 16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 17 * driver is the different register layout that exists between the 18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 19 * platforms (MV78200 from the Discovery family and the Armada 20 * XP). Therefore, this driver handles three variants of the GPIO 21 * block: 22 * - the basic variant, called "orion-gpio", with the simplest 23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 24 * non-SMP Discovery systems 25 * - the mv78200 variant for MV78200 Discovery systems. This variant 26 * turns the edge mask and level mask registers into CPU0 edge 27 * mask/level mask registers, and adds CPU1 edge mask/level mask 28 * registers. 29 * - the armadaxp variant for Armada XP systems. This variant keeps 30 * the normal cause/edge mask/level mask registers when the global 31 * interrupts are used, but adds per-CPU cause/edge mask/level mask 32 * registers n a separate memory area for the per-CPU GPIO 33 * interrupts. 34 */ 35 36 #include <linux/bitops.h> 37 #include <linux/clk.h> 38 #include <linux/err.h> 39 #include <linux/gpio/driver.h> 40 #include <linux/gpio/consumer.h> 41 #include <linux/gpio/machine.h> 42 #include <linux/init.h> 43 #include <linux/io.h> 44 #include <linux/irq.h> 45 #include <linux/irqchip/chained_irq.h> 46 #include <linux/irqdomain.h> 47 #include <linux/mfd/syscon.h> 48 #include <linux/of_device.h> 49 #include <linux/pinctrl/consumer.h> 50 #include <linux/platform_device.h> 51 #include <linux/pwm.h> 52 #include <linux/regmap.h> 53 #include <linux/slab.h> 54 55 /* 56 * GPIO unit register offsets. 57 */ 58 #define GPIO_OUT_OFF 0x0000 59 #define GPIO_IO_CONF_OFF 0x0004 60 #define GPIO_BLINK_EN_OFF 0x0008 61 #define GPIO_IN_POL_OFF 0x000c 62 #define GPIO_DATA_IN_OFF 0x0010 63 #define GPIO_EDGE_CAUSE_OFF 0x0014 64 #define GPIO_EDGE_MASK_OFF 0x0018 65 #define GPIO_LEVEL_MASK_OFF 0x001c 66 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020 67 68 /* 69 * PWM register offsets. 70 */ 71 #define PWM_BLINK_ON_DURATION_OFF 0x0 72 #define PWM_BLINK_OFF_DURATION_OFF 0x4 73 #define PWM_BLINK_COUNTER_B_OFF 0x8 74 75 /* Armada 8k variant gpios register offsets */ 76 #define AP80X_GPIO0_OFF_A8K 0x1040 77 #define CP11X_GPIO0_OFF_A8K 0x100 78 #define CP11X_GPIO1_OFF_A8K 0x140 79 80 /* The MV78200 has per-CPU registers for edge mask and level mask */ 81 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 82 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 83 84 /* 85 * The Armada XP has per-CPU registers for interrupt cause, interrupt 86 * mask and interrupt level mask. Those are in percpu_regs range. 87 */ 88 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 89 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 90 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 91 92 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 93 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 94 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 95 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4 96 97 #define MVEBU_MAX_GPIO_PER_BANK 32 98 99 struct mvebu_pwm { 100 struct regmap *regs; 101 u32 offset; 102 unsigned long clk_rate; 103 struct gpio_desc *gpiod; 104 struct pwm_chip chip; 105 spinlock_t lock; 106 struct mvebu_gpio_chip *mvchip; 107 108 /* Used to preserve GPIO/PWM registers across suspend/resume */ 109 u32 blink_select; 110 u32 blink_on_duration; 111 u32 blink_off_duration; 112 }; 113 114 struct mvebu_gpio_chip { 115 struct gpio_chip chip; 116 struct regmap *regs; 117 u32 offset; 118 struct regmap *percpu_regs; 119 int irqbase; 120 struct irq_domain *domain; 121 int soc_variant; 122 123 /* Used for PWM support */ 124 struct clk *clk; 125 struct mvebu_pwm *mvpwm; 126 127 /* Used to preserve GPIO registers across suspend/resume */ 128 u32 out_reg; 129 u32 io_conf_reg; 130 u32 blink_en_reg; 131 u32 in_pol_reg; 132 u32 edge_mask_regs[4]; 133 u32 level_mask_regs[4]; 134 }; 135 136 /* 137 * Functions returning addresses of individual registers for a given 138 * GPIO controller. 139 */ 140 141 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip, 142 struct regmap **map, unsigned int *offset) 143 { 144 int cpu; 145 146 switch (mvchip->soc_variant) { 147 case MVEBU_GPIO_SOC_VARIANT_ORION: 148 case MVEBU_GPIO_SOC_VARIANT_MV78200: 149 case MVEBU_GPIO_SOC_VARIANT_A8K: 150 *map = mvchip->regs; 151 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; 152 break; 153 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 154 cpu = smp_processor_id(); 155 *map = mvchip->percpu_regs; 156 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 157 break; 158 default: 159 BUG(); 160 } 161 } 162 163 static u32 164 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip) 165 { 166 struct regmap *map; 167 unsigned int offset; 168 u32 val; 169 170 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 171 regmap_read(map, offset, &val); 172 173 return val; 174 } 175 176 static void 177 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) 178 { 179 struct regmap *map; 180 unsigned int offset; 181 182 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 183 regmap_write(map, offset, val); 184 } 185 186 static inline void 187 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip, 188 struct regmap **map, unsigned int *offset) 189 { 190 int cpu; 191 192 switch (mvchip->soc_variant) { 193 case MVEBU_GPIO_SOC_VARIANT_ORION: 194 case MVEBU_GPIO_SOC_VARIANT_A8K: 195 *map = mvchip->regs; 196 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; 197 break; 198 case MVEBU_GPIO_SOC_VARIANT_MV78200: 199 cpu = smp_processor_id(); 200 *map = mvchip->regs; 201 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); 202 break; 203 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 204 cpu = smp_processor_id(); 205 *map = mvchip->percpu_regs; 206 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 207 break; 208 default: 209 BUG(); 210 } 211 } 212 213 static u32 214 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip) 215 { 216 struct regmap *map; 217 unsigned int offset; 218 u32 val; 219 220 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 221 regmap_read(map, offset, &val); 222 223 return val; 224 } 225 226 static void 227 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) 228 { 229 struct regmap *map; 230 unsigned int offset; 231 232 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 233 regmap_write(map, offset, val); 234 } 235 236 static void 237 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip, 238 struct regmap **map, unsigned int *offset) 239 { 240 int cpu; 241 242 switch (mvchip->soc_variant) { 243 case MVEBU_GPIO_SOC_VARIANT_ORION: 244 case MVEBU_GPIO_SOC_VARIANT_A8K: 245 *map = mvchip->regs; 246 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; 247 break; 248 case MVEBU_GPIO_SOC_VARIANT_MV78200: 249 cpu = smp_processor_id(); 250 *map = mvchip->regs; 251 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); 252 break; 253 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 254 cpu = smp_processor_id(); 255 *map = mvchip->percpu_regs; 256 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 257 break; 258 default: 259 BUG(); 260 } 261 } 262 263 static u32 264 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip) 265 { 266 struct regmap *map; 267 unsigned int offset; 268 u32 val; 269 270 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 271 regmap_read(map, offset, &val); 272 273 return val; 274 } 275 276 static void 277 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) 278 { 279 struct regmap *map; 280 unsigned int offset; 281 282 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 283 regmap_write(map, offset, val); 284 } 285 286 /* 287 * Functions returning offsets of individual registers for a given 288 * PWM controller. 289 */ 290 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) 291 { 292 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; 293 } 294 295 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) 296 { 297 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; 298 } 299 300 /* 301 * Functions implementing the gpio_chip methods 302 */ 303 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 304 { 305 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 306 307 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 308 BIT(pin), value ? BIT(pin) : 0); 309 } 310 311 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) 312 { 313 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 314 u32 u; 315 316 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 317 318 if (u & BIT(pin)) { 319 u32 data_in, in_pol; 320 321 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, 322 &data_in); 323 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 324 &in_pol); 325 u = data_in ^ in_pol; 326 } else { 327 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); 328 } 329 330 return (u >> pin) & 1; 331 } 332 333 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, 334 int value) 335 { 336 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 337 338 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 339 BIT(pin), value ? BIT(pin) : 0); 340 } 341 342 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) 343 { 344 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 345 int ret; 346 347 /* 348 * Check with the pinctrl driver whether this pin is usable as 349 * an input GPIO 350 */ 351 ret = pinctrl_gpio_direction_input(chip->base + pin); 352 if (ret) 353 return ret; 354 355 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 356 BIT(pin), BIT(pin)); 357 358 return 0; 359 } 360 361 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, 362 int value) 363 { 364 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 365 int ret; 366 367 /* 368 * Check with the pinctrl driver whether this pin is usable as 369 * an output GPIO 370 */ 371 ret = pinctrl_gpio_direction_output(chip->base + pin); 372 if (ret) 373 return ret; 374 375 mvebu_gpio_blink(chip, pin, 0); 376 mvebu_gpio_set(chip, pin, value); 377 378 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 379 BIT(pin), 0); 380 381 return 0; 382 } 383 384 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 385 { 386 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 387 u32 u; 388 389 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 390 391 if (u & BIT(pin)) 392 return GPIO_LINE_DIRECTION_IN; 393 394 return GPIO_LINE_DIRECTION_OUT; 395 } 396 397 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) 398 { 399 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 400 401 return irq_create_mapping(mvchip->domain, pin); 402 } 403 404 /* 405 * Functions implementing the irq_chip methods 406 */ 407 static void mvebu_gpio_irq_ack(struct irq_data *d) 408 { 409 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 410 struct mvebu_gpio_chip *mvchip = gc->private; 411 u32 mask = d->mask; 412 413 irq_gc_lock(gc); 414 mvebu_gpio_write_edge_cause(mvchip, ~mask); 415 irq_gc_unlock(gc); 416 } 417 418 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 419 { 420 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 421 struct mvebu_gpio_chip *mvchip = gc->private; 422 struct irq_chip_type *ct = irq_data_get_chip_type(d); 423 u32 mask = d->mask; 424 425 irq_gc_lock(gc); 426 ct->mask_cache_priv &= ~mask; 427 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 428 irq_gc_unlock(gc); 429 } 430 431 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 432 { 433 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 434 struct mvebu_gpio_chip *mvchip = gc->private; 435 struct irq_chip_type *ct = irq_data_get_chip_type(d); 436 u32 mask = d->mask; 437 438 irq_gc_lock(gc); 439 mvebu_gpio_write_edge_cause(mvchip, ~mask); 440 ct->mask_cache_priv |= mask; 441 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 442 irq_gc_unlock(gc); 443 } 444 445 static void mvebu_gpio_level_irq_mask(struct irq_data *d) 446 { 447 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 448 struct mvebu_gpio_chip *mvchip = gc->private; 449 struct irq_chip_type *ct = irq_data_get_chip_type(d); 450 u32 mask = d->mask; 451 452 irq_gc_lock(gc); 453 ct->mask_cache_priv &= ~mask; 454 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 455 irq_gc_unlock(gc); 456 } 457 458 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 459 { 460 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 461 struct mvebu_gpio_chip *mvchip = gc->private; 462 struct irq_chip_type *ct = irq_data_get_chip_type(d); 463 u32 mask = d->mask; 464 465 irq_gc_lock(gc); 466 ct->mask_cache_priv |= mask; 467 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 468 irq_gc_unlock(gc); 469 } 470 471 /***************************************************************************** 472 * MVEBU GPIO IRQ 473 * 474 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 475 * value of the line or the opposite value. 476 * 477 * Level IRQ handlers: DATA_IN is used directly as cause register. 478 * Interrupt are masked by LEVEL_MASK registers. 479 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 480 * Interrupt are masked by EDGE_MASK registers. 481 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 482 * the polarity to catch the next line transaction. 483 * This is a race condition that might not perfectly 484 * work on some use cases. 485 * 486 * Every eight GPIO lines are grouped (OR'ed) before going up to main 487 * cause register. 488 * 489 * EDGE cause mask 490 * data-in /--------| |-----| |----\ 491 * -----| |----- ---- to main cause reg 492 * X \----------------| |----/ 493 * polarity LEVEL mask 494 * 495 ****************************************************************************/ 496 497 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 498 { 499 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 500 struct irq_chip_type *ct = irq_data_get_chip_type(d); 501 struct mvebu_gpio_chip *mvchip = gc->private; 502 int pin; 503 u32 u; 504 505 pin = d->hwirq; 506 507 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 508 if ((u & BIT(pin)) == 0) 509 return -EINVAL; 510 511 type &= IRQ_TYPE_SENSE_MASK; 512 if (type == IRQ_TYPE_NONE) 513 return -EINVAL; 514 515 /* Check if we need to change chip and handler */ 516 if (!(ct->type & type)) 517 if (irq_setup_alt_chip(d, type)) 518 return -EINVAL; 519 520 /* 521 * Configure interrupt polarity. 522 */ 523 switch (type) { 524 case IRQ_TYPE_EDGE_RISING: 525 case IRQ_TYPE_LEVEL_HIGH: 526 regmap_update_bits(mvchip->regs, 527 GPIO_IN_POL_OFF + mvchip->offset, 528 BIT(pin), 0); 529 break; 530 case IRQ_TYPE_EDGE_FALLING: 531 case IRQ_TYPE_LEVEL_LOW: 532 regmap_update_bits(mvchip->regs, 533 GPIO_IN_POL_OFF + mvchip->offset, 534 BIT(pin), BIT(pin)); 535 break; 536 case IRQ_TYPE_EDGE_BOTH: { 537 u32 data_in, in_pol, val; 538 539 regmap_read(mvchip->regs, 540 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 541 regmap_read(mvchip->regs, 542 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 543 544 /* 545 * set initial polarity based on current input level 546 */ 547 if ((data_in ^ in_pol) & BIT(pin)) 548 val = BIT(pin); /* falling */ 549 else 550 val = 0; /* raising */ 551 552 regmap_update_bits(mvchip->regs, 553 GPIO_IN_POL_OFF + mvchip->offset, 554 BIT(pin), val); 555 break; 556 } 557 } 558 return 0; 559 } 560 561 static void mvebu_gpio_irq_handler(struct irq_desc *desc) 562 { 563 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); 564 struct irq_chip *chip = irq_desc_get_chip(desc); 565 u32 cause, type, data_in, level_mask, edge_cause, edge_mask; 566 int i; 567 568 if (mvchip == NULL) 569 return; 570 571 chained_irq_enter(chip, desc); 572 573 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 574 level_mask = mvebu_gpio_read_level_mask(mvchip); 575 edge_cause = mvebu_gpio_read_edge_cause(mvchip); 576 edge_mask = mvebu_gpio_read_edge_mask(mvchip); 577 578 cause = (data_in & level_mask) | (edge_cause & edge_mask); 579 580 for (i = 0; i < mvchip->chip.ngpio; i++) { 581 int irq; 582 583 irq = irq_find_mapping(mvchip->domain, i); 584 585 if (!(cause & BIT(i))) 586 continue; 587 588 type = irq_get_trigger_type(irq); 589 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 590 /* Swap polarity (race with GPIO line) */ 591 u32 polarity; 592 593 regmap_read(mvchip->regs, 594 GPIO_IN_POL_OFF + mvchip->offset, 595 &polarity); 596 polarity ^= BIT(i); 597 regmap_write(mvchip->regs, 598 GPIO_IN_POL_OFF + mvchip->offset, 599 polarity); 600 } 601 602 generic_handle_irq(irq); 603 } 604 605 chained_irq_exit(chip, desc); 606 } 607 608 static const struct regmap_config mvebu_gpio_regmap_config = { 609 .reg_bits = 32, 610 .reg_stride = 4, 611 .val_bits = 32, 612 .fast_io = true, 613 }; 614 615 /* 616 * Functions implementing the pwm_chip methods 617 */ 618 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) 619 { 620 return container_of(chip, struct mvebu_pwm, chip); 621 } 622 623 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 624 { 625 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 626 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 627 struct gpio_desc *desc; 628 unsigned long flags; 629 int ret = 0; 630 631 spin_lock_irqsave(&mvpwm->lock, flags); 632 633 if (mvpwm->gpiod) { 634 ret = -EBUSY; 635 } else { 636 desc = gpiochip_request_own_desc(&mvchip->chip, 637 pwm->hwpwm, "mvebu-pwm", 638 GPIO_ACTIVE_HIGH, 639 GPIOD_OUT_LOW); 640 if (IS_ERR(desc)) { 641 ret = PTR_ERR(desc); 642 goto out; 643 } 644 645 mvpwm->gpiod = desc; 646 } 647 out: 648 spin_unlock_irqrestore(&mvpwm->lock, flags); 649 return ret; 650 } 651 652 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 653 { 654 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 655 unsigned long flags; 656 657 spin_lock_irqsave(&mvpwm->lock, flags); 658 gpiochip_free_own_desc(mvpwm->gpiod); 659 mvpwm->gpiod = NULL; 660 spin_unlock_irqrestore(&mvpwm->lock, flags); 661 } 662 663 static void mvebu_pwm_get_state(struct pwm_chip *chip, 664 struct pwm_device *pwm, 665 struct pwm_state *state) { 666 667 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 668 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 669 unsigned long long val; 670 unsigned long flags; 671 u32 u; 672 673 spin_lock_irqsave(&mvpwm->lock, flags); 674 675 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); 676 /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */ 677 if (u > 0) 678 val = u; 679 else 680 val = UINT_MAX + 1ULL; 681 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, 682 mvpwm->clk_rate); 683 684 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); 685 /* period = on + off duration */ 686 if (u > 0) 687 val += u; 688 else 689 val += UINT_MAX + 1ULL; 690 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); 691 692 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); 693 if (u) 694 state->enabled = true; 695 else 696 state->enabled = false; 697 698 spin_unlock_irqrestore(&mvpwm->lock, flags); 699 } 700 701 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 702 const struct pwm_state *state) 703 { 704 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 705 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 706 unsigned long long val; 707 unsigned long flags; 708 unsigned int on, off; 709 710 if (state->polarity != PWM_POLARITY_NORMAL) 711 return -EINVAL; 712 713 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; 714 do_div(val, NSEC_PER_SEC); 715 if (val > UINT_MAX + 1ULL) 716 return -EINVAL; 717 /* 718 * Zero on/off values don't work as expected. Experimentation shows 719 * that zero value is treated as 2^32. This behavior is not documented. 720 */ 721 if (val == UINT_MAX + 1ULL) 722 on = 0; 723 else if (val) 724 on = val; 725 else 726 on = 1; 727 728 val = (unsigned long long) mvpwm->clk_rate * state->period; 729 do_div(val, NSEC_PER_SEC); 730 val -= on; 731 if (val > UINT_MAX + 1ULL) 732 return -EINVAL; 733 if (val == UINT_MAX + 1ULL) 734 off = 0; 735 else if (val) 736 off = val; 737 else 738 off = 1; 739 740 spin_lock_irqsave(&mvpwm->lock, flags); 741 742 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); 743 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); 744 if (state->enabled) 745 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); 746 else 747 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); 748 749 spin_unlock_irqrestore(&mvpwm->lock, flags); 750 751 return 0; 752 } 753 754 static const struct pwm_ops mvebu_pwm_ops = { 755 .request = mvebu_pwm_request, 756 .free = mvebu_pwm_free, 757 .get_state = mvebu_pwm_get_state, 758 .apply = mvebu_pwm_apply, 759 .owner = THIS_MODULE, 760 }; 761 762 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) 763 { 764 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 765 766 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 767 &mvpwm->blink_select); 768 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), 769 &mvpwm->blink_on_duration); 770 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), 771 &mvpwm->blink_off_duration); 772 } 773 774 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) 775 { 776 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 777 778 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 779 mvpwm->blink_select); 780 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), 781 mvpwm->blink_on_duration); 782 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), 783 mvpwm->blink_off_duration); 784 } 785 786 static int mvebu_pwm_probe(struct platform_device *pdev, 787 struct mvebu_gpio_chip *mvchip, 788 int id) 789 { 790 struct device *dev = &pdev->dev; 791 struct mvebu_pwm *mvpwm; 792 void __iomem *base; 793 u32 offset; 794 u32 set; 795 796 if (of_device_is_compatible(mvchip->chip.of_node, 797 "marvell,armada-370-gpio")) { 798 /* 799 * There are only two sets of PWM configuration registers for 800 * all the GPIO lines on those SoCs which this driver reserves 801 * for the first two GPIO chips. So if the resource is missing 802 * we can't treat it as an error. 803 */ 804 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) 805 return 0; 806 offset = 0; 807 } else if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { 808 int ret = of_property_read_u32(dev->of_node, 809 "marvell,pwm-offset", &offset); 810 if (ret < 0) 811 return 0; 812 } else { 813 return 0; 814 } 815 816 if (IS_ERR(mvchip->clk)) 817 return PTR_ERR(mvchip->clk); 818 819 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); 820 if (!mvpwm) 821 return -ENOMEM; 822 mvchip->mvpwm = mvpwm; 823 mvpwm->mvchip = mvchip; 824 mvpwm->offset = offset; 825 826 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { 827 mvpwm->regs = mvchip->regs; 828 829 switch (mvchip->offset) { 830 case AP80X_GPIO0_OFF_A8K: 831 case CP11X_GPIO0_OFF_A8K: 832 /* Blink counter A */ 833 set = 0; 834 break; 835 case CP11X_GPIO1_OFF_A8K: 836 /* Blink counter B */ 837 set = U32_MAX; 838 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; 839 break; 840 default: 841 return -EINVAL; 842 } 843 } else { 844 base = devm_platform_ioremap_resource_byname(pdev, "pwm"); 845 if (IS_ERR(base)) 846 return PTR_ERR(base); 847 848 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, 849 &mvebu_gpio_regmap_config); 850 if (IS_ERR(mvpwm->regs)) 851 return PTR_ERR(mvpwm->regs); 852 853 /* 854 * Use set A for lines of GPIO chip with id 0, B for GPIO chip 855 * with id 1. Don't allow further GPIO chips to be used for PWM. 856 */ 857 if (id == 0) 858 set = 0; 859 else if (id == 1) 860 set = U32_MAX; 861 else 862 return -EINVAL; 863 } 864 865 regmap_write(mvchip->regs, 866 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); 867 868 mvpwm->clk_rate = clk_get_rate(mvchip->clk); 869 if (!mvpwm->clk_rate) { 870 dev_err(dev, "failed to get clock rate\n"); 871 return -EINVAL; 872 } 873 874 mvpwm->chip.dev = dev; 875 mvpwm->chip.ops = &mvebu_pwm_ops; 876 mvpwm->chip.npwm = mvchip->chip.ngpio; 877 878 spin_lock_init(&mvpwm->lock); 879 880 return pwmchip_add(&mvpwm->chip); 881 } 882 883 #ifdef CONFIG_DEBUG_FS 884 #include <linux/seq_file.h> 885 886 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 887 { 888 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 889 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 890 const char *label; 891 int i; 892 893 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); 894 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); 895 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); 896 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 897 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 898 cause = mvebu_gpio_read_edge_cause(mvchip); 899 edg_msk = mvebu_gpio_read_edge_mask(mvchip); 900 lvl_msk = mvebu_gpio_read_level_mask(mvchip); 901 902 for_each_requested_gpio(chip, i, label) { 903 u32 msk; 904 bool is_out; 905 906 msk = BIT(i); 907 is_out = !(io_conf & msk); 908 909 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 910 911 if (is_out) { 912 seq_printf(s, " out %s %s\n", 913 out & msk ? "hi" : "lo", 914 blink & msk ? "(blink )" : ""); 915 continue; 916 } 917 918 seq_printf(s, " in %s (act %s) - IRQ", 919 (data_in ^ in_pol) & msk ? "hi" : "lo", 920 in_pol & msk ? "lo" : "hi"); 921 if (!((edg_msk | lvl_msk) & msk)) { 922 seq_puts(s, " disabled\n"); 923 continue; 924 } 925 if (edg_msk & msk) 926 seq_puts(s, " edge "); 927 if (lvl_msk & msk) 928 seq_puts(s, " level"); 929 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 930 } 931 } 932 #else 933 #define mvebu_gpio_dbg_show NULL 934 #endif 935 936 static const struct of_device_id mvebu_gpio_of_match[] = { 937 { 938 .compatible = "marvell,orion-gpio", 939 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 940 }, 941 { 942 .compatible = "marvell,mv78200-gpio", 943 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, 944 }, 945 { 946 .compatible = "marvell,armadaxp-gpio", 947 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 948 }, 949 { 950 .compatible = "marvell,armada-370-gpio", 951 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 952 }, 953 { 954 .compatible = "marvell,armada-8k-gpio", 955 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K, 956 }, 957 { 958 /* sentinel */ 959 }, 960 }; 961 962 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) 963 { 964 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 965 int i; 966 967 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 968 &mvchip->out_reg); 969 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 970 &mvchip->io_conf_reg); 971 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 972 &mvchip->blink_en_reg); 973 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 974 &mvchip->in_pol_reg); 975 976 switch (mvchip->soc_variant) { 977 case MVEBU_GPIO_SOC_VARIANT_ORION: 978 case MVEBU_GPIO_SOC_VARIANT_A8K: 979 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 980 &mvchip->edge_mask_regs[0]); 981 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 982 &mvchip->level_mask_regs[0]); 983 break; 984 case MVEBU_GPIO_SOC_VARIANT_MV78200: 985 for (i = 0; i < 2; i++) { 986 regmap_read(mvchip->regs, 987 GPIO_EDGE_MASK_MV78200_OFF(i), 988 &mvchip->edge_mask_regs[i]); 989 regmap_read(mvchip->regs, 990 GPIO_LEVEL_MASK_MV78200_OFF(i), 991 &mvchip->level_mask_regs[i]); 992 } 993 break; 994 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 995 for (i = 0; i < 4; i++) { 996 regmap_read(mvchip->regs, 997 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 998 &mvchip->edge_mask_regs[i]); 999 regmap_read(mvchip->regs, 1000 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 1001 &mvchip->level_mask_regs[i]); 1002 } 1003 break; 1004 default: 1005 BUG(); 1006 } 1007 1008 if (IS_ENABLED(CONFIG_PWM)) 1009 mvebu_pwm_suspend(mvchip); 1010 1011 return 0; 1012 } 1013 1014 static int mvebu_gpio_resume(struct platform_device *pdev) 1015 { 1016 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 1017 int i; 1018 1019 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 1020 mvchip->out_reg); 1021 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 1022 mvchip->io_conf_reg); 1023 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 1024 mvchip->blink_en_reg); 1025 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 1026 mvchip->in_pol_reg); 1027 1028 switch (mvchip->soc_variant) { 1029 case MVEBU_GPIO_SOC_VARIANT_ORION: 1030 case MVEBU_GPIO_SOC_VARIANT_A8K: 1031 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 1032 mvchip->edge_mask_regs[0]); 1033 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 1034 mvchip->level_mask_regs[0]); 1035 break; 1036 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1037 for (i = 0; i < 2; i++) { 1038 regmap_write(mvchip->regs, 1039 GPIO_EDGE_MASK_MV78200_OFF(i), 1040 mvchip->edge_mask_regs[i]); 1041 regmap_write(mvchip->regs, 1042 GPIO_LEVEL_MASK_MV78200_OFF(i), 1043 mvchip->level_mask_regs[i]); 1044 } 1045 break; 1046 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1047 for (i = 0; i < 4; i++) { 1048 regmap_write(mvchip->regs, 1049 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 1050 mvchip->edge_mask_regs[i]); 1051 regmap_write(mvchip->regs, 1052 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 1053 mvchip->level_mask_regs[i]); 1054 } 1055 break; 1056 default: 1057 BUG(); 1058 } 1059 1060 if (IS_ENABLED(CONFIG_PWM)) 1061 mvebu_pwm_resume(mvchip); 1062 1063 return 0; 1064 } 1065 1066 static int mvebu_gpio_probe_raw(struct platform_device *pdev, 1067 struct mvebu_gpio_chip *mvchip) 1068 { 1069 void __iomem *base; 1070 1071 base = devm_platform_ioremap_resource(pdev, 0); 1072 if (IS_ERR(base)) 1073 return PTR_ERR(base); 1074 1075 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, 1076 &mvebu_gpio_regmap_config); 1077 if (IS_ERR(mvchip->regs)) 1078 return PTR_ERR(mvchip->regs); 1079 1080 /* 1081 * For the legacy SoCs, the regmap directly maps to the GPIO 1082 * registers, so no offset is needed. 1083 */ 1084 mvchip->offset = 0; 1085 1086 /* 1087 * The Armada XP has a second range of registers for the 1088 * per-CPU registers 1089 */ 1090 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 1091 base = devm_platform_ioremap_resource(pdev, 1); 1092 if (IS_ERR(base)) 1093 return PTR_ERR(base); 1094 1095 mvchip->percpu_regs = 1096 devm_regmap_init_mmio(&pdev->dev, base, 1097 &mvebu_gpio_regmap_config); 1098 if (IS_ERR(mvchip->percpu_regs)) 1099 return PTR_ERR(mvchip->percpu_regs); 1100 } 1101 1102 return 0; 1103 } 1104 1105 static int mvebu_gpio_probe_syscon(struct platform_device *pdev, 1106 struct mvebu_gpio_chip *mvchip) 1107 { 1108 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); 1109 if (IS_ERR(mvchip->regs)) 1110 return PTR_ERR(mvchip->regs); 1111 1112 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) 1113 return -EINVAL; 1114 1115 return 0; 1116 } 1117 1118 static int mvebu_gpio_probe(struct platform_device *pdev) 1119 { 1120 struct mvebu_gpio_chip *mvchip; 1121 const struct of_device_id *match; 1122 struct device_node *np = pdev->dev.of_node; 1123 struct irq_chip_generic *gc; 1124 struct irq_chip_type *ct; 1125 unsigned int ngpios; 1126 bool have_irqs; 1127 int soc_variant; 1128 int i, cpu, id; 1129 int err; 1130 1131 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); 1132 if (match) 1133 soc_variant = (unsigned long) match->data; 1134 else 1135 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; 1136 1137 /* Some gpio controllers do not provide irq support */ 1138 err = platform_irq_count(pdev); 1139 if (err < 0) 1140 return err; 1141 1142 have_irqs = err != 0; 1143 1144 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), 1145 GFP_KERNEL); 1146 if (!mvchip) 1147 return -ENOMEM; 1148 1149 platform_set_drvdata(pdev, mvchip); 1150 1151 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 1152 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 1153 return -ENODEV; 1154 } 1155 1156 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 1157 if (id < 0) { 1158 dev_err(&pdev->dev, "Couldn't get OF id\n"); 1159 return id; 1160 } 1161 1162 mvchip->clk = devm_clk_get(&pdev->dev, NULL); 1163 /* Not all SoCs require a clock.*/ 1164 if (!IS_ERR(mvchip->clk)) 1165 clk_prepare_enable(mvchip->clk); 1166 1167 mvchip->soc_variant = soc_variant; 1168 mvchip->chip.label = dev_name(&pdev->dev); 1169 mvchip->chip.parent = &pdev->dev; 1170 mvchip->chip.request = gpiochip_generic_request; 1171 mvchip->chip.free = gpiochip_generic_free; 1172 mvchip->chip.get_direction = mvebu_gpio_get_direction; 1173 mvchip->chip.direction_input = mvebu_gpio_direction_input; 1174 mvchip->chip.get = mvebu_gpio_get; 1175 mvchip->chip.direction_output = mvebu_gpio_direction_output; 1176 mvchip->chip.set = mvebu_gpio_set; 1177 if (have_irqs) 1178 mvchip->chip.to_irq = mvebu_gpio_to_irq; 1179 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 1180 mvchip->chip.ngpio = ngpios; 1181 mvchip->chip.can_sleep = false; 1182 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; 1183 1184 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) 1185 err = mvebu_gpio_probe_syscon(pdev, mvchip); 1186 else 1187 err = mvebu_gpio_probe_raw(pdev, mvchip); 1188 1189 if (err) 1190 return err; 1191 1192 /* 1193 * Mask and clear GPIO interrupts. 1194 */ 1195 switch (soc_variant) { 1196 case MVEBU_GPIO_SOC_VARIANT_ORION: 1197 case MVEBU_GPIO_SOC_VARIANT_A8K: 1198 regmap_write(mvchip->regs, 1199 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); 1200 regmap_write(mvchip->regs, 1201 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); 1202 regmap_write(mvchip->regs, 1203 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); 1204 break; 1205 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1206 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1207 for (cpu = 0; cpu < 2; cpu++) { 1208 regmap_write(mvchip->regs, 1209 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); 1210 regmap_write(mvchip->regs, 1211 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); 1212 } 1213 break; 1214 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1215 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1216 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); 1217 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); 1218 for (cpu = 0; cpu < 4; cpu++) { 1219 regmap_write(mvchip->percpu_regs, 1220 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); 1221 regmap_write(mvchip->percpu_regs, 1222 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); 1223 regmap_write(mvchip->percpu_regs, 1224 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); 1225 } 1226 break; 1227 default: 1228 BUG(); 1229 } 1230 1231 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); 1232 1233 /* Some MVEBU SoCs have simple PWM support for GPIO lines */ 1234 if (IS_ENABLED(CONFIG_PWM)) { 1235 err = mvebu_pwm_probe(pdev, mvchip, id); 1236 if (err) 1237 return err; 1238 } 1239 1240 /* Some gpio controllers do not provide irq support */ 1241 if (!have_irqs) 1242 return 0; 1243 1244 mvchip->domain = 1245 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); 1246 if (!mvchip->domain) { 1247 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 1248 mvchip->chip.label); 1249 err = -ENODEV; 1250 goto err_pwm; 1251 } 1252 1253 err = irq_alloc_domain_generic_chips( 1254 mvchip->domain, ngpios, 2, np->name, handle_level_irq, 1255 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); 1256 if (err) { 1257 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", 1258 mvchip->chip.label); 1259 goto err_domain; 1260 } 1261 1262 /* 1263 * NOTE: The common accessors cannot be used because of the percpu 1264 * access to the mask registers 1265 */ 1266 gc = irq_get_domain_generic_chip(mvchip->domain, 0); 1267 gc->private = mvchip; 1268 ct = &gc->chip_types[0]; 1269 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 1270 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 1271 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 1272 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1273 ct->chip.name = mvchip->chip.label; 1274 1275 ct = &gc->chip_types[1]; 1276 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 1277 ct->chip.irq_ack = mvebu_gpio_irq_ack; 1278 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 1279 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 1280 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1281 ct->handler = handle_edge_irq; 1282 ct->chip.name = mvchip->chip.label; 1283 1284 /* 1285 * Setup the interrupt handlers. Each chip can have up to 4 1286 * interrupt handlers, with each handler dealing with 8 GPIO 1287 * pins. 1288 */ 1289 for (i = 0; i < 4; i++) { 1290 int irq = platform_get_irq_optional(pdev, i); 1291 1292 if (irq < 0) 1293 continue; 1294 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, 1295 mvchip); 1296 } 1297 1298 return 0; 1299 1300 err_domain: 1301 irq_domain_remove(mvchip->domain); 1302 err_pwm: 1303 pwmchip_remove(&mvchip->mvpwm->chip); 1304 1305 return err; 1306 } 1307 1308 static struct platform_driver mvebu_gpio_driver = { 1309 .driver = { 1310 .name = "mvebu-gpio", 1311 .of_match_table = mvebu_gpio_of_match, 1312 }, 1313 .probe = mvebu_gpio_probe, 1314 .suspend = mvebu_gpio_suspend, 1315 .resume = mvebu_gpio_resume, 1316 }; 1317 builtin_platform_driver(mvebu_gpio_driver); 1318