1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 4 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 5 */ 6 7 #include <linux/err.h> 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of_irq.h> 13 #include <linux/platform_device.h> 14 #include <linux/spinlock.h> 15 16 #define MTK_BANK_CNT 3 17 #define MTK_BANK_WIDTH 32 18 19 #define GPIO_BANK_STRIDE 0x04 20 #define GPIO_REG_CTRL 0x00 21 #define GPIO_REG_POL 0x10 22 #define GPIO_REG_DATA 0x20 23 #define GPIO_REG_DSET 0x30 24 #define GPIO_REG_DCLR 0x40 25 #define GPIO_REG_REDGE 0x50 26 #define GPIO_REG_FEDGE 0x60 27 #define GPIO_REG_HLVL 0x70 28 #define GPIO_REG_LLVL 0x80 29 #define GPIO_REG_STAT 0x90 30 #define GPIO_REG_EDGE 0xA0 31 32 struct mtk_gc { 33 struct irq_chip irq_chip; 34 struct gpio_chip chip; 35 spinlock_t lock; 36 int bank; 37 u32 rising; 38 u32 falling; 39 u32 hlevel; 40 u32 llevel; 41 }; 42 43 /** 44 * struct mtk - state container for 45 * data of the platform driver. It is 3 46 * separate gpio-chip each one with its 47 * own irq_chip. 48 * @dev: device instance 49 * @base: memory base address 50 * @gpio_irq: irq number from the device tree 51 * @gc_map: array of the gpio chips 52 */ 53 struct mtk { 54 struct device *dev; 55 void __iomem *base; 56 int gpio_irq; 57 struct mtk_gc gc_map[MTK_BANK_CNT]; 58 }; 59 60 static inline struct mtk_gc * 61 to_mediatek_gpio(struct gpio_chip *chip) 62 { 63 return container_of(chip, struct mtk_gc, chip); 64 } 65 66 static inline void 67 mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val) 68 { 69 struct gpio_chip *gc = &rg->chip; 70 struct mtk *mtk = gpiochip_get_data(gc); 71 72 offset = (rg->bank * GPIO_BANK_STRIDE) + offset; 73 gc->write_reg(mtk->base + offset, val); 74 } 75 76 static inline u32 77 mtk_gpio_r32(struct mtk_gc *rg, u32 offset) 78 { 79 struct gpio_chip *gc = &rg->chip; 80 struct mtk *mtk = gpiochip_get_data(gc); 81 82 offset = (rg->bank * GPIO_BANK_STRIDE) + offset; 83 return gc->read_reg(mtk->base + offset); 84 } 85 86 static irqreturn_t 87 mediatek_gpio_irq_handler(int irq, void *data) 88 { 89 struct gpio_chip *gc = data; 90 struct mtk_gc *rg = to_mediatek_gpio(gc); 91 irqreturn_t ret = IRQ_NONE; 92 unsigned long pending; 93 int bit; 94 95 pending = mtk_gpio_r32(rg, GPIO_REG_STAT); 96 97 for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) { 98 generic_handle_domain_irq(gc->irq.domain, bit); 99 mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); 100 ret |= IRQ_HANDLED; 101 } 102 103 return ret; 104 } 105 106 static void 107 mediatek_gpio_irq_unmask(struct irq_data *d) 108 { 109 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 110 struct mtk_gc *rg = to_mediatek_gpio(gc); 111 int pin = d->hwirq; 112 unsigned long flags; 113 u32 rise, fall, high, low; 114 115 gpiochip_enable_irq(gc, d->hwirq); 116 117 spin_lock_irqsave(&rg->lock, flags); 118 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); 119 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); 120 high = mtk_gpio_r32(rg, GPIO_REG_HLVL); 121 low = mtk_gpio_r32(rg, GPIO_REG_LLVL); 122 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising)); 123 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling)); 124 mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel)); 125 mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel)); 126 spin_unlock_irqrestore(&rg->lock, flags); 127 } 128 129 static void 130 mediatek_gpio_irq_mask(struct irq_data *d) 131 { 132 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 133 struct mtk_gc *rg = to_mediatek_gpio(gc); 134 int pin = d->hwirq; 135 unsigned long flags; 136 u32 rise, fall, high, low; 137 138 spin_lock_irqsave(&rg->lock, flags); 139 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); 140 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); 141 high = mtk_gpio_r32(rg, GPIO_REG_HLVL); 142 low = mtk_gpio_r32(rg, GPIO_REG_LLVL); 143 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin)); 144 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin)); 145 mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin)); 146 mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin)); 147 spin_unlock_irqrestore(&rg->lock, flags); 148 149 gpiochip_disable_irq(gc, d->hwirq); 150 } 151 152 static int 153 mediatek_gpio_irq_type(struct irq_data *d, unsigned int type) 154 { 155 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 156 struct mtk_gc *rg = to_mediatek_gpio(gc); 157 int pin = d->hwirq; 158 u32 mask = BIT(pin); 159 160 if (type == IRQ_TYPE_PROBE) { 161 if ((rg->rising | rg->falling | 162 rg->hlevel | rg->llevel) & mask) 163 return 0; 164 165 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 166 } 167 168 rg->rising &= ~mask; 169 rg->falling &= ~mask; 170 rg->hlevel &= ~mask; 171 rg->llevel &= ~mask; 172 173 switch (type & IRQ_TYPE_SENSE_MASK) { 174 case IRQ_TYPE_EDGE_BOTH: 175 rg->rising |= mask; 176 rg->falling |= mask; 177 break; 178 case IRQ_TYPE_EDGE_RISING: 179 rg->rising |= mask; 180 break; 181 case IRQ_TYPE_EDGE_FALLING: 182 rg->falling |= mask; 183 break; 184 case IRQ_TYPE_LEVEL_HIGH: 185 rg->hlevel |= mask; 186 break; 187 case IRQ_TYPE_LEVEL_LOW: 188 rg->llevel |= mask; 189 break; 190 } 191 192 return 0; 193 } 194 195 static int 196 mediatek_gpio_xlate(struct gpio_chip *chip, 197 const struct of_phandle_args *spec, u32 *flags) 198 { 199 int gpio = spec->args[0]; 200 struct mtk_gc *rg = to_mediatek_gpio(chip); 201 202 if (rg->bank != gpio / MTK_BANK_WIDTH) 203 return -EINVAL; 204 205 if (flags) 206 *flags = spec->args[1]; 207 208 return gpio % MTK_BANK_WIDTH; 209 } 210 211 static const struct irq_chip mt7621_irq_chip = { 212 .name = "mt7621-gpio", 213 .irq_mask_ack = mediatek_gpio_irq_mask, 214 .irq_mask = mediatek_gpio_irq_mask, 215 .irq_unmask = mediatek_gpio_irq_unmask, 216 .irq_set_type = mediatek_gpio_irq_type, 217 .flags = IRQCHIP_IMMUTABLE, 218 GPIOCHIP_IRQ_RESOURCE_HELPERS, 219 }; 220 221 static int 222 mediatek_gpio_bank_probe(struct device *dev, int bank) 223 { 224 struct mtk *mtk = dev_get_drvdata(dev); 225 struct mtk_gc *rg; 226 void __iomem *dat, *set, *ctrl, *diro; 227 int ret; 228 229 rg = &mtk->gc_map[bank]; 230 memset(rg, 0, sizeof(*rg)); 231 232 spin_lock_init(&rg->lock); 233 rg->bank = bank; 234 235 dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE); 236 set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE); 237 ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); 238 diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); 239 240 ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL, 241 BGPIOF_NO_SET_ON_INPUT); 242 if (ret) { 243 dev_err(dev, "bgpio_init() failed\n"); 244 return ret; 245 } 246 247 rg->chip.of_gpio_n_cells = 2; 248 rg->chip.of_xlate = mediatek_gpio_xlate; 249 rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", 250 dev_name(dev), bank); 251 if (!rg->chip.label) 252 return -ENOMEM; 253 254 rg->chip.offset = bank * MTK_BANK_WIDTH; 255 256 if (mtk->gpio_irq) { 257 struct gpio_irq_chip *girq; 258 259 /* 260 * Directly request the irq here instead of passing 261 * a flow-handler because the irq is shared. 262 */ 263 ret = devm_request_irq(dev, mtk->gpio_irq, 264 mediatek_gpio_irq_handler, IRQF_SHARED, 265 rg->chip.label, &rg->chip); 266 267 if (ret) { 268 dev_err(dev, "Error requesting IRQ %d: %d\n", 269 mtk->gpio_irq, ret); 270 return ret; 271 } 272 273 girq = &rg->chip.irq; 274 gpio_irq_chip_set_chip(girq, &mt7621_irq_chip); 275 /* This will let us handle the parent IRQ in the driver */ 276 girq->parent_handler = NULL; 277 girq->num_parents = 0; 278 girq->parents = NULL; 279 girq->default_type = IRQ_TYPE_NONE; 280 girq->handler = handle_simple_irq; 281 } 282 283 ret = devm_gpiochip_add_data(dev, &rg->chip, mtk); 284 if (ret < 0) { 285 dev_err(dev, "Could not register gpio %d, ret=%d\n", 286 rg->chip.ngpio, ret); 287 return ret; 288 } 289 290 /* set polarity to low for all gpios */ 291 mtk_gpio_w32(rg, GPIO_REG_POL, 0); 292 293 dev_info(dev, "registering %d gpios\n", rg->chip.ngpio); 294 295 return 0; 296 } 297 298 static int 299 mediatek_gpio_probe(struct platform_device *pdev) 300 { 301 struct device *dev = &pdev->dev; 302 struct device_node *np = dev->of_node; 303 struct mtk *mtk; 304 int i; 305 int ret; 306 307 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); 308 if (!mtk) 309 return -ENOMEM; 310 311 mtk->base = devm_platform_ioremap_resource(pdev, 0); 312 if (IS_ERR(mtk->base)) 313 return PTR_ERR(mtk->base); 314 315 mtk->gpio_irq = irq_of_parse_and_map(np, 0); 316 mtk->dev = dev; 317 platform_set_drvdata(pdev, mtk); 318 319 for (i = 0; i < MTK_BANK_CNT; i++) { 320 ret = mediatek_gpio_bank_probe(dev, i); 321 if (ret) 322 return ret; 323 } 324 325 return 0; 326 } 327 328 static const struct of_device_id mediatek_gpio_match[] = { 329 { .compatible = "mediatek,mt7621-gpio" }, 330 {}, 331 }; 332 MODULE_DEVICE_TABLE(of, mediatek_gpio_match); 333 334 static struct platform_driver mediatek_gpio_driver = { 335 .probe = mediatek_gpio_probe, 336 .driver = { 337 .name = "mt7621_gpio", 338 .of_match_table = mediatek_gpio_match, 339 }, 340 }; 341 342 builtin_platform_driver(mediatek_gpio_driver); 343