1 /* 2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible 3 * 4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> 5 * Copyright (C) 2016 Freescale Semiconductor Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/spinlock.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/of_gpio.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/slab.h> 22 #include <linux/irq.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/bitops.h> 25 #include <linux/interrupt.h> 26 27 #define MPC8XXX_GPIO_PINS 32 28 29 #define GPIO_DIR 0x00 30 #define GPIO_ODR 0x04 31 #define GPIO_DAT 0x08 32 #define GPIO_IER 0x0c 33 #define GPIO_IMR 0x10 34 #define GPIO_ICR 0x14 35 #define GPIO_ICR2 0x18 36 #define GPIO_IBE 0x18 37 38 struct mpc8xxx_gpio_chip { 39 struct gpio_chip gc; 40 void __iomem *regs; 41 raw_spinlock_t lock; 42 43 int (*direction_output)(struct gpio_chip *chip, 44 unsigned offset, int value); 45 46 struct irq_domain *irq; 47 unsigned int irqn; 48 }; 49 50 /* The GPIO Input Buffer Enable register(GPIO_IBE) is used to 51 * control the input enable of each individual GPIO port. 52 * When an individual GPIO port’s direction is set to 53 * input (GPIO_GPDIR[DRn=0]), the associated input enable must be 54 * set (GPIOxGPIE[IEn]=1) to propagate the port value to the GPIO 55 * Data Register. 56 */ 57 static int ls1028a_gpio_dir_in_init(struct gpio_chip *gc) 58 { 59 unsigned long flags; 60 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 61 62 spin_lock_irqsave(&gc->bgpio_lock, flags); 63 64 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); 65 66 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 67 68 return 0; 69 } 70 71 /* 72 * This hardware has a big endian bit assignment such that GPIO line 0 is 73 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0. 74 * This inline helper give the right bitmask for a certain line. 75 */ 76 static inline u32 mpc_pin2mask(unsigned int offset) 77 { 78 return BIT(31 - offset); 79 } 80 81 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs 82 * defined as output cannot be determined by reading GPDAT register, 83 * so we use shadow data register instead. The status of input pins 84 * is determined by reading GPDAT register. 85 */ 86 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) 87 { 88 u32 val; 89 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 90 u32 out_mask, out_shadow; 91 92 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); 93 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; 94 out_shadow = gc->bgpio_data & out_mask; 95 96 return !!((val | out_shadow) & mpc_pin2mask(gpio)); 97 } 98 99 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, 100 unsigned int gpio, int val) 101 { 102 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 103 /* GPIO 28..31 are input only on MPC5121 */ 104 if (gpio >= 28) 105 return -EINVAL; 106 107 return mpc8xxx_gc->direction_output(gc, gpio, val); 108 } 109 110 static int mpc5125_gpio_dir_out(struct gpio_chip *gc, 111 unsigned int gpio, int val) 112 { 113 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 114 /* GPIO 0..3 are input only on MPC5125 */ 115 if (gpio <= 3) 116 return -EINVAL; 117 118 return mpc8xxx_gc->direction_output(gc, gpio, val); 119 } 120 121 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 122 { 123 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 124 125 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) 126 return irq_create_mapping(mpc8xxx_gc->irq, offset); 127 else 128 return -ENXIO; 129 } 130 131 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data) 132 { 133 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data; 134 struct gpio_chip *gc = &mpc8xxx_gc->gc; 135 unsigned long mask; 136 int i; 137 138 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) 139 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); 140 for_each_set_bit(i, &mask, 32) 141 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 31 - i)); 142 143 return IRQ_HANDLED; 144 } 145 146 static void mpc8xxx_irq_unmask(struct irq_data *d) 147 { 148 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 149 struct gpio_chip *gc = &mpc8xxx_gc->gc; 150 unsigned long flags; 151 152 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 153 154 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 155 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) 156 | mpc_pin2mask(irqd_to_hwirq(d))); 157 158 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 159 } 160 161 static void mpc8xxx_irq_mask(struct irq_data *d) 162 { 163 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 164 struct gpio_chip *gc = &mpc8xxx_gc->gc; 165 unsigned long flags; 166 167 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 168 169 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 170 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) 171 & ~mpc_pin2mask(irqd_to_hwirq(d))); 172 173 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 174 } 175 176 static void mpc8xxx_irq_ack(struct irq_data *d) 177 { 178 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 179 struct gpio_chip *gc = &mpc8xxx_gc->gc; 180 181 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 182 mpc_pin2mask(irqd_to_hwirq(d))); 183 } 184 185 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) 186 { 187 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 188 struct gpio_chip *gc = &mpc8xxx_gc->gc; 189 unsigned long flags; 190 191 switch (flow_type) { 192 case IRQ_TYPE_EDGE_FALLING: 193 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 194 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, 195 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) 196 | mpc_pin2mask(irqd_to_hwirq(d))); 197 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 198 break; 199 200 case IRQ_TYPE_EDGE_BOTH: 201 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 202 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, 203 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) 204 & ~mpc_pin2mask(irqd_to_hwirq(d))); 205 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 206 break; 207 208 default: 209 return -EINVAL; 210 } 211 212 return 0; 213 } 214 215 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) 216 { 217 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 218 struct gpio_chip *gc = &mpc8xxx_gc->gc; 219 unsigned long gpio = irqd_to_hwirq(d); 220 void __iomem *reg; 221 unsigned int shift; 222 unsigned long flags; 223 224 if (gpio < 16) { 225 reg = mpc8xxx_gc->regs + GPIO_ICR; 226 shift = (15 - gpio) * 2; 227 } else { 228 reg = mpc8xxx_gc->regs + GPIO_ICR2; 229 shift = (15 - (gpio % 16)) * 2; 230 } 231 232 switch (flow_type) { 233 case IRQ_TYPE_EDGE_FALLING: 234 case IRQ_TYPE_LEVEL_LOW: 235 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 236 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) 237 | (2 << shift)); 238 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 239 break; 240 241 case IRQ_TYPE_EDGE_RISING: 242 case IRQ_TYPE_LEVEL_HIGH: 243 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 244 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) 245 | (1 << shift)); 246 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 247 break; 248 249 case IRQ_TYPE_EDGE_BOTH: 250 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 251 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); 252 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 253 break; 254 255 default: 256 return -EINVAL; 257 } 258 259 return 0; 260 } 261 262 static struct irq_chip mpc8xxx_irq_chip = { 263 .name = "mpc8xxx-gpio", 264 .irq_unmask = mpc8xxx_irq_unmask, 265 .irq_mask = mpc8xxx_irq_mask, 266 .irq_ack = mpc8xxx_irq_ack, 267 /* this might get overwritten in mpc8xxx_probe() */ 268 .irq_set_type = mpc8xxx_irq_set_type, 269 }; 270 271 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, 272 irq_hw_number_t hwirq) 273 { 274 irq_set_chip_data(irq, h->host_data); 275 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq); 276 277 return 0; 278 } 279 280 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = { 281 .map = mpc8xxx_gpio_irq_map, 282 .xlate = irq_domain_xlate_twocell, 283 }; 284 285 struct mpc8xxx_gpio_devtype { 286 int (*gpio_dir_in_init)(struct gpio_chip *chip); 287 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int); 288 int (*gpio_get)(struct gpio_chip *, unsigned int); 289 int (*irq_set_type)(struct irq_data *, unsigned int); 290 }; 291 292 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = { 293 .gpio_dir_out = mpc5121_gpio_dir_out, 294 .irq_set_type = mpc512x_irq_set_type, 295 }; 296 297 static const struct mpc8xxx_gpio_devtype ls1028a_gpio_devtype = { 298 .gpio_dir_in_init = ls1028a_gpio_dir_in_init, 299 .irq_set_type = mpc8xxx_irq_set_type, 300 }; 301 302 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = { 303 .gpio_dir_out = mpc5125_gpio_dir_out, 304 .irq_set_type = mpc512x_irq_set_type, 305 }; 306 307 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = { 308 .gpio_get = mpc8572_gpio_get, 309 }; 310 311 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = { 312 .irq_set_type = mpc8xxx_irq_set_type, 313 }; 314 315 static const struct of_device_id mpc8xxx_gpio_ids[] = { 316 { .compatible = "fsl,mpc8349-gpio", }, 317 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, }, 318 { .compatible = "fsl,mpc8610-gpio", }, 319 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, }, 320 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, }, 321 { .compatible = "fsl,pq3-gpio", }, 322 { .compatible = "fsl,ls1028a-gpio", .data = &ls1028a_gpio_devtype, }, 323 { .compatible = "fsl,ls1088a-gpio", .data = &ls1028a_gpio_devtype, }, 324 { .compatible = "fsl,qoriq-gpio", }, 325 {} 326 }; 327 328 static int mpc8xxx_probe(struct platform_device *pdev) 329 { 330 struct device_node *np = pdev->dev.of_node; 331 struct mpc8xxx_gpio_chip *mpc8xxx_gc; 332 struct gpio_chip *gc; 333 const struct mpc8xxx_gpio_devtype *devtype = 334 of_device_get_match_data(&pdev->dev); 335 int ret; 336 337 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); 338 if (!mpc8xxx_gc) 339 return -ENOMEM; 340 341 platform_set_drvdata(pdev, mpc8xxx_gc); 342 343 raw_spin_lock_init(&mpc8xxx_gc->lock); 344 345 mpc8xxx_gc->regs = of_iomap(np, 0); 346 if (!mpc8xxx_gc->regs) 347 return -ENOMEM; 348 349 gc = &mpc8xxx_gc->gc; 350 gc->parent = &pdev->dev; 351 352 if (of_property_read_bool(np, "little-endian")) { 353 ret = bgpio_init(gc, &pdev->dev, 4, 354 mpc8xxx_gc->regs + GPIO_DAT, 355 NULL, NULL, 356 mpc8xxx_gc->regs + GPIO_DIR, NULL, 357 BGPIOF_BIG_ENDIAN); 358 if (ret) 359 goto err; 360 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n"); 361 } else { 362 ret = bgpio_init(gc, &pdev->dev, 4, 363 mpc8xxx_gc->regs + GPIO_DAT, 364 NULL, NULL, 365 mpc8xxx_gc->regs + GPIO_DIR, NULL, 366 BGPIOF_BIG_ENDIAN 367 | BGPIOF_BIG_ENDIAN_BYTE_ORDER); 368 if (ret) 369 goto err; 370 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n"); 371 } 372 373 mpc8xxx_gc->direction_output = gc->direction_output; 374 375 if (!devtype) 376 devtype = &mpc8xxx_gpio_devtype_default; 377 378 /* 379 * It's assumed that only a single type of gpio controller is available 380 * on the current machine, so overwriting global data is fine. 381 */ 382 if (devtype->irq_set_type) 383 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; 384 385 if (devtype->gpio_dir_out) 386 gc->direction_output = devtype->gpio_dir_out; 387 if (devtype->gpio_get) 388 gc->get = devtype->gpio_get; 389 390 gc->to_irq = mpc8xxx_gpio_to_irq; 391 392 if (of_device_is_compatible(np, "fsl,qoriq-gpio")) 393 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); 394 395 ret = gpiochip_add_data(gc, mpc8xxx_gc); 396 if (ret) { 397 pr_err("%pOF: GPIO chip registration failed with status %d\n", 398 np, ret); 399 goto err; 400 } 401 402 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0); 403 if (!mpc8xxx_gc->irqn) 404 return 0; 405 406 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, 407 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc); 408 if (!mpc8xxx_gc->irq) 409 return 0; 410 411 /* ack and mask all irqs */ 412 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); 413 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); 414 /* enable input buffer */ 415 if (devtype->gpio_dir_in_init) 416 devtype->gpio_dir_in_init(gc); 417 418 ret = devm_request_irq(&pdev->dev, mpc8xxx_gc->irqn, 419 mpc8xxx_gpio_irq_cascade, 420 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", 421 mpc8xxx_gc); 422 if (ret) { 423 dev_err(&pdev->dev, "%s: failed to devm_request_irq(%d), ret = %d\n", 424 np->full_name, mpc8xxx_gc->irqn, ret); 425 goto err; 426 } 427 428 return 0; 429 err: 430 iounmap(mpc8xxx_gc->regs); 431 return ret; 432 } 433 434 static int mpc8xxx_remove(struct platform_device *pdev) 435 { 436 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev); 437 438 if (mpc8xxx_gc->irq) { 439 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); 440 irq_domain_remove(mpc8xxx_gc->irq); 441 } 442 443 gpiochip_remove(&mpc8xxx_gc->gc); 444 iounmap(mpc8xxx_gc->regs); 445 446 return 0; 447 } 448 449 static struct platform_driver mpc8xxx_plat_driver = { 450 .probe = mpc8xxx_probe, 451 .remove = mpc8xxx_remove, 452 .driver = { 453 .name = "gpio-mpc8xxx", 454 .of_match_table = mpc8xxx_gpio_ids, 455 }, 456 }; 457 458 static int __init mpc8xxx_init(void) 459 { 460 return platform_driver_register(&mpc8xxx_plat_driver); 461 } 462 463 arch_initcall(mpc8xxx_init); 464