1 /* 2 * GPIOs on MPC512x/8349/8572/8610 and compatible 3 * 4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11 #include <linux/kernel.h> 12 #include <linux/init.h> 13 #include <linux/spinlock.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_gpio.h> 17 #include <linux/of_irq.h> 18 #include <linux/gpio.h> 19 #include <linux/slab.h> 20 #include <linux/irq.h> 21 22 #define MPC8XXX_GPIO_PINS 32 23 24 #define GPIO_DIR 0x00 25 #define GPIO_ODR 0x04 26 #define GPIO_DAT 0x08 27 #define GPIO_IER 0x0c 28 #define GPIO_IMR 0x10 29 #define GPIO_ICR 0x14 30 #define GPIO_ICR2 0x18 31 32 struct mpc8xxx_gpio_chip { 33 struct of_mm_gpio_chip mm_gc; 34 spinlock_t lock; 35 36 /* 37 * shadowed data register to be able to clear/set output pins in 38 * open drain mode safely 39 */ 40 u32 data; 41 struct irq_domain *irq; 42 const void *of_dev_id_data; 43 }; 44 45 static inline u32 mpc8xxx_gpio2mask(unsigned int gpio) 46 { 47 return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio); 48 } 49 50 static inline struct mpc8xxx_gpio_chip * 51 to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm) 52 { 53 return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc); 54 } 55 56 static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm) 57 { 58 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 59 60 mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT); 61 } 62 63 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs 64 * defined as output cannot be determined by reading GPDAT register, 65 * so we use shadow data register instead. The status of input pins 66 * is determined by reading GPDAT register. 67 */ 68 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) 69 { 70 u32 val; 71 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 72 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 73 74 val = in_be32(mm->regs + GPIO_DAT) & ~in_be32(mm->regs + GPIO_DIR); 75 76 return (val | mpc8xxx_gc->data) & mpc8xxx_gpio2mask(gpio); 77 } 78 79 static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio) 80 { 81 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 82 83 return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio); 84 } 85 86 static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 87 { 88 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 89 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 90 unsigned long flags; 91 92 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 93 94 if (val) 95 mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio); 96 else 97 mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio); 98 99 out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data); 100 101 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 102 } 103 104 static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 105 { 106 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 107 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 108 unsigned long flags; 109 110 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 111 112 clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); 113 114 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 115 116 return 0; 117 } 118 119 static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 120 { 121 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 122 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 123 unsigned long flags; 124 125 mpc8xxx_gpio_set(gc, gpio, val); 126 127 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 128 129 setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio)); 130 131 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 132 133 return 0; 134 } 135 136 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 137 { 138 /* GPIO 28..31 are input only on MPC5121 */ 139 if (gpio >= 28) 140 return -EINVAL; 141 142 return mpc8xxx_gpio_dir_out(gc, gpio, val); 143 } 144 145 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 146 { 147 struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc); 148 struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm); 149 150 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) 151 return irq_create_mapping(mpc8xxx_gc->irq, offset); 152 else 153 return -ENXIO; 154 } 155 156 static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc) 157 { 158 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); 159 struct irq_chip *chip = irq_desc_get_chip(desc); 160 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 161 unsigned int mask; 162 163 mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR); 164 if (mask) 165 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 166 32 - ffs(mask))); 167 if (chip->irq_eoi) 168 chip->irq_eoi(&desc->irq_data); 169 } 170 171 static void mpc8xxx_irq_unmask(struct irq_data *d) 172 { 173 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 174 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 175 unsigned long flags; 176 177 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 178 179 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); 180 181 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 182 } 183 184 static void mpc8xxx_irq_mask(struct irq_data *d) 185 { 186 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 187 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 188 unsigned long flags; 189 190 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 191 192 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); 193 194 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 195 } 196 197 static void mpc8xxx_irq_ack(struct irq_data *d) 198 { 199 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 200 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 201 202 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d))); 203 } 204 205 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) 206 { 207 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 208 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 209 unsigned long flags; 210 211 switch (flow_type) { 212 case IRQ_TYPE_EDGE_FALLING: 213 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 214 setbits32(mm->regs + GPIO_ICR, 215 mpc8xxx_gpio2mask(irqd_to_hwirq(d))); 216 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 217 break; 218 219 case IRQ_TYPE_EDGE_BOTH: 220 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 221 clrbits32(mm->regs + GPIO_ICR, 222 mpc8xxx_gpio2mask(irqd_to_hwirq(d))); 223 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 224 break; 225 226 default: 227 return -EINVAL; 228 } 229 230 return 0; 231 } 232 233 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) 234 { 235 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 236 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 237 unsigned long gpio = irqd_to_hwirq(d); 238 void __iomem *reg; 239 unsigned int shift; 240 unsigned long flags; 241 242 if (gpio < 16) { 243 reg = mm->regs + GPIO_ICR; 244 shift = (15 - gpio) * 2; 245 } else { 246 reg = mm->regs + GPIO_ICR2; 247 shift = (15 - (gpio % 16)) * 2; 248 } 249 250 switch (flow_type) { 251 case IRQ_TYPE_EDGE_FALLING: 252 case IRQ_TYPE_LEVEL_LOW: 253 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 254 clrsetbits_be32(reg, 3 << shift, 2 << shift); 255 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 256 break; 257 258 case IRQ_TYPE_EDGE_RISING: 259 case IRQ_TYPE_LEVEL_HIGH: 260 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 261 clrsetbits_be32(reg, 3 << shift, 1 << shift); 262 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 263 break; 264 265 case IRQ_TYPE_EDGE_BOTH: 266 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 267 clrbits32(reg, 3 << shift); 268 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 269 break; 270 271 default: 272 return -EINVAL; 273 } 274 275 return 0; 276 } 277 278 static struct irq_chip mpc8xxx_irq_chip = { 279 .name = "mpc8xxx-gpio", 280 .irq_unmask = mpc8xxx_irq_unmask, 281 .irq_mask = mpc8xxx_irq_mask, 282 .irq_ack = mpc8xxx_irq_ack, 283 .irq_set_type = mpc8xxx_irq_set_type, 284 }; 285 286 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int virq, 287 irq_hw_number_t hw) 288 { 289 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data; 290 291 if (mpc8xxx_gc->of_dev_id_data) 292 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data; 293 294 irq_set_chip_data(virq, h->host_data); 295 irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); 296 297 return 0; 298 } 299 300 static struct irq_domain_ops mpc8xxx_gpio_irq_ops = { 301 .map = mpc8xxx_gpio_irq_map, 302 .xlate = irq_domain_xlate_twocell, 303 }; 304 305 static struct of_device_id mpc8xxx_gpio_ids[] __initdata = { 306 { .compatible = "fsl,mpc8349-gpio", }, 307 { .compatible = "fsl,mpc8572-gpio", }, 308 { .compatible = "fsl,mpc8610-gpio", }, 309 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, }, 310 { .compatible = "fsl,pq3-gpio", }, 311 { .compatible = "fsl,qoriq-gpio", }, 312 {} 313 }; 314 315 static void __init mpc8xxx_add_controller(struct device_node *np) 316 { 317 struct mpc8xxx_gpio_chip *mpc8xxx_gc; 318 struct of_mm_gpio_chip *mm_gc; 319 struct gpio_chip *gc; 320 const struct of_device_id *id; 321 unsigned hwirq; 322 int ret; 323 324 mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL); 325 if (!mpc8xxx_gc) { 326 ret = -ENOMEM; 327 goto err; 328 } 329 330 spin_lock_init(&mpc8xxx_gc->lock); 331 332 mm_gc = &mpc8xxx_gc->mm_gc; 333 gc = &mm_gc->gc; 334 335 mm_gc->save_regs = mpc8xxx_gpio_save_regs; 336 gc->ngpio = MPC8XXX_GPIO_PINS; 337 gc->direction_input = mpc8xxx_gpio_dir_in; 338 gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ? 339 mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out; 340 gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ? 341 mpc8572_gpio_get : mpc8xxx_gpio_get; 342 gc->set = mpc8xxx_gpio_set; 343 gc->to_irq = mpc8xxx_gpio_to_irq; 344 345 ret = of_mm_gpiochip_add(np, mm_gc); 346 if (ret) 347 goto err; 348 349 hwirq = irq_of_parse_and_map(np, 0); 350 if (hwirq == NO_IRQ) 351 goto skip_irq; 352 353 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, 354 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc); 355 if (!mpc8xxx_gc->irq) 356 goto skip_irq; 357 358 id = of_match_node(mpc8xxx_gpio_ids, np); 359 if (id) 360 mpc8xxx_gc->of_dev_id_data = id->data; 361 362 /* ack and mask all irqs */ 363 out_be32(mm_gc->regs + GPIO_IER, 0xffffffff); 364 out_be32(mm_gc->regs + GPIO_IMR, 0); 365 366 irq_set_handler_data(hwirq, mpc8xxx_gc); 367 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); 368 369 skip_irq: 370 return; 371 372 err: 373 pr_err("%s: registration failed with status %d\n", 374 np->full_name, ret); 375 kfree(mpc8xxx_gc); 376 377 return; 378 } 379 380 static int __init mpc8xxx_add_gpiochips(void) 381 { 382 struct device_node *np; 383 384 for_each_matching_node(np, mpc8xxx_gpio_ids) 385 mpc8xxx_add_controller(np); 386 387 return 0; 388 } 389 arch_initcall(mpc8xxx_add_gpiochips); 390