1 /* 2 * Generic driver for memory-mapped GPIO controllers. 3 * 4 * Copyright 2008 MontaVista Software, Inc. 5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... 13 * ...`` ```````.. 14 * ..The simplest form of a GPIO controller that the driver supports is`` 15 * `.just a single "data" register, where GPIO state can be read and/or ` 16 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` 17 * ````````` 18 ___ 19 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... 20 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . 21 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` 22 `....trivial..'~`.```.``` 23 * ``````` 24 * .```````~~~~`..`.``.``. 25 * . The driver supports `... ,..```.`~~~```````````````....````.``,, 26 * . big-endian notation, just`. .. A bit more sophisticated controllers , 27 * . register the device with -be`. .with a pair of set/clear-bit registers , 28 * `.. suffix. ```~~`````....`.` . affecting the data register and the .` 29 * ``.`.``...``` ```.. output pins are also supported.` 30 * ^^ `````.`````````.,``~``~``~~`````` 31 * . ^^ 32 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. 33 * .. The expectation is that in at least some cases . ,-~~~-, 34 * .this will be used with roll-your-own ASIC/FPGA .` \ / 35 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / 36 * ..````````......``````````` \o_ 37 * | 38 * ^^ / \ 39 * 40 * ...`````~~`.....``.`..........``````.`.``.```........``. 41 * ` 8, 16, 32 and 64 bits registers are supported, and``. 42 * . the number of GPIOs is determined by the width of ~ 43 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ 44 * `.......````.``` 45 */ 46 47 #include <linux/init.h> 48 #include <linux/err.h> 49 #include <linux/bug.h> 50 #include <linux/kernel.h> 51 #include <linux/module.h> 52 #include <linux/spinlock.h> 53 #include <linux/compiler.h> 54 #include <linux/types.h> 55 #include <linux/errno.h> 56 #include <linux/log2.h> 57 #include <linux/ioport.h> 58 #include <linux/io.h> 59 #include <linux/gpio/driver.h> 60 #include <linux/slab.h> 61 #include <linux/bitops.h> 62 #include <linux/platform_device.h> 63 #include <linux/mod_devicetable.h> 64 #include <linux/of.h> 65 #include <linux/of_device.h> 66 67 static void bgpio_write8(void __iomem *reg, unsigned long data) 68 { 69 writeb(data, reg); 70 } 71 72 static unsigned long bgpio_read8(void __iomem *reg) 73 { 74 return readb(reg); 75 } 76 77 static void bgpio_write16(void __iomem *reg, unsigned long data) 78 { 79 writew(data, reg); 80 } 81 82 static unsigned long bgpio_read16(void __iomem *reg) 83 { 84 return readw(reg); 85 } 86 87 static void bgpio_write32(void __iomem *reg, unsigned long data) 88 { 89 writel(data, reg); 90 } 91 92 static unsigned long bgpio_read32(void __iomem *reg) 93 { 94 return readl(reg); 95 } 96 97 #if BITS_PER_LONG >= 64 98 static void bgpio_write64(void __iomem *reg, unsigned long data) 99 { 100 writeq(data, reg); 101 } 102 103 static unsigned long bgpio_read64(void __iomem *reg) 104 { 105 return readq(reg); 106 } 107 #endif /* BITS_PER_LONG >= 64 */ 108 109 static void bgpio_write16be(void __iomem *reg, unsigned long data) 110 { 111 iowrite16be(data, reg); 112 } 113 114 static unsigned long bgpio_read16be(void __iomem *reg) 115 { 116 return ioread16be(reg); 117 } 118 119 static void bgpio_write32be(void __iomem *reg, unsigned long data) 120 { 121 iowrite32be(data, reg); 122 } 123 124 static unsigned long bgpio_read32be(void __iomem *reg) 125 { 126 return ioread32be(reg); 127 } 128 129 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) 130 { 131 if (gc->be_bits) 132 return BIT(gc->bgpio_bits - 1 - line); 133 return BIT(line); 134 } 135 136 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) 137 { 138 unsigned long pinmask = bgpio_line2mask(gc, gpio); 139 140 if (gc->bgpio_dir & pinmask) 141 return !!(gc->read_reg(gc->reg_set) & pinmask); 142 else 143 return !!(gc->read_reg(gc->reg_dat) & pinmask); 144 } 145 146 /* 147 * This assumes that the bits in the GPIO register are in native endianness. 148 * We only assign the function pointer if we have that. 149 */ 150 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, 151 unsigned long *bits) 152 { 153 unsigned long get_mask = 0; 154 unsigned long set_mask = 0; 155 156 /* Make sure we first clear any bits that are zero when we read the register */ 157 *bits &= ~*mask; 158 159 /* Exploit the fact that we know which directions are set */ 160 set_mask = *mask & gc->bgpio_dir; 161 get_mask = *mask & ~gc->bgpio_dir; 162 163 if (set_mask) 164 *bits |= gc->read_reg(gc->reg_set) & set_mask; 165 if (get_mask) 166 *bits |= gc->read_reg(gc->reg_dat) & get_mask; 167 168 return 0; 169 } 170 171 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) 172 { 173 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); 174 } 175 176 /* 177 * This only works if the bits in the GPIO register are in native endianness. 178 */ 179 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, 180 unsigned long *bits) 181 { 182 /* Make sure we first clear any bits that are zero when we read the register */ 183 *bits &= ~*mask; 184 *bits |= gc->read_reg(gc->reg_dat) & *mask; 185 return 0; 186 } 187 188 /* 189 * With big endian mirrored bit order it becomes more tedious. 190 */ 191 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, 192 unsigned long *bits) 193 { 194 unsigned long readmask = 0; 195 unsigned long val; 196 int bit; 197 198 /* Make sure we first clear any bits that are zero when we read the register */ 199 *bits &= ~*mask; 200 201 /* Create a mirrored mask */ 202 bit = -1; 203 while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio) 204 readmask |= bgpio_line2mask(gc, bit); 205 206 /* Read the register */ 207 val = gc->read_reg(gc->reg_dat) & readmask; 208 209 /* 210 * Mirror the result into the "bits" result, this will give line 0 211 * in bit 0 ... line 31 in bit 31 for a 32bit register. 212 */ 213 bit = -1; 214 while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio) 215 *bits |= bgpio_line2mask(gc, bit); 216 217 return 0; 218 } 219 220 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) 221 { 222 } 223 224 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 225 { 226 unsigned long mask = bgpio_line2mask(gc, gpio); 227 unsigned long flags; 228 229 spin_lock_irqsave(&gc->bgpio_lock, flags); 230 231 if (val) 232 gc->bgpio_data |= mask; 233 else 234 gc->bgpio_data &= ~mask; 235 236 gc->write_reg(gc->reg_dat, gc->bgpio_data); 237 238 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 239 } 240 241 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, 242 int val) 243 { 244 unsigned long mask = bgpio_line2mask(gc, gpio); 245 246 if (val) 247 gc->write_reg(gc->reg_set, mask); 248 else 249 gc->write_reg(gc->reg_clr, mask); 250 } 251 252 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) 253 { 254 unsigned long mask = bgpio_line2mask(gc, gpio); 255 unsigned long flags; 256 257 spin_lock_irqsave(&gc->bgpio_lock, flags); 258 259 if (val) 260 gc->bgpio_data |= mask; 261 else 262 gc->bgpio_data &= ~mask; 263 264 gc->write_reg(gc->reg_set, gc->bgpio_data); 265 266 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 267 } 268 269 static void bgpio_multiple_get_masks(struct gpio_chip *gc, 270 unsigned long *mask, unsigned long *bits, 271 unsigned long *set_mask, 272 unsigned long *clear_mask) 273 { 274 int i; 275 276 *set_mask = 0; 277 *clear_mask = 0; 278 279 for (i = 0; i < gc->bgpio_bits; i++) { 280 if (*mask == 0) 281 break; 282 if (__test_and_clear_bit(i, mask)) { 283 if (test_bit(i, bits)) 284 *set_mask |= bgpio_line2mask(gc, i); 285 else 286 *clear_mask |= bgpio_line2mask(gc, i); 287 } 288 } 289 } 290 291 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, 292 unsigned long *mask, 293 unsigned long *bits, 294 void __iomem *reg) 295 { 296 unsigned long flags; 297 unsigned long set_mask, clear_mask; 298 299 spin_lock_irqsave(&gc->bgpio_lock, flags); 300 301 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 302 303 gc->bgpio_data |= set_mask; 304 gc->bgpio_data &= ~clear_mask; 305 306 gc->write_reg(reg, gc->bgpio_data); 307 308 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 309 } 310 311 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 312 unsigned long *bits) 313 { 314 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); 315 } 316 317 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, 318 unsigned long *bits) 319 { 320 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); 321 } 322 323 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, 324 unsigned long *mask, 325 unsigned long *bits) 326 { 327 unsigned long set_mask, clear_mask; 328 329 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 330 331 if (set_mask) 332 gc->write_reg(gc->reg_set, set_mask); 333 if (clear_mask) 334 gc->write_reg(gc->reg_clr, clear_mask); 335 } 336 337 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) 338 { 339 return 0; 340 } 341 342 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, 343 int val) 344 { 345 return -EINVAL; 346 } 347 348 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, 349 int val) 350 { 351 gc->set(gc, gpio, val); 352 353 return 0; 354 } 355 356 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 357 { 358 unsigned long flags; 359 360 spin_lock_irqsave(&gc->bgpio_lock, flags); 361 362 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); 363 gc->write_reg(gc->reg_dir, gc->bgpio_dir); 364 365 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 366 367 return 0; 368 } 369 370 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) 371 { 372 /* Return 0 if output, 1 of input */ 373 return !(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio)); 374 } 375 376 static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 377 { 378 unsigned long flags; 379 380 gc->set(gc, gpio, val); 381 382 spin_lock_irqsave(&gc->bgpio_lock, flags); 383 384 gc->bgpio_dir |= bgpio_line2mask(gc, gpio); 385 gc->write_reg(gc->reg_dir, gc->bgpio_dir); 386 387 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 388 389 return 0; 390 } 391 392 static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio) 393 { 394 unsigned long flags; 395 396 spin_lock_irqsave(&gc->bgpio_lock, flags); 397 398 gc->bgpio_dir |= bgpio_line2mask(gc, gpio); 399 gc->write_reg(gc->reg_dir, gc->bgpio_dir); 400 401 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 402 403 return 0; 404 } 405 406 static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val) 407 { 408 unsigned long flags; 409 410 gc->set(gc, gpio, val); 411 412 spin_lock_irqsave(&gc->bgpio_lock, flags); 413 414 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); 415 gc->write_reg(gc->reg_dir, gc->bgpio_dir); 416 417 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 418 419 return 0; 420 } 421 422 static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio) 423 { 424 /* Return 0 if output, 1 if input */ 425 return !!(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio)); 426 } 427 428 static int bgpio_setup_accessors(struct device *dev, 429 struct gpio_chip *gc, 430 bool byte_be) 431 { 432 433 switch (gc->bgpio_bits) { 434 case 8: 435 gc->read_reg = bgpio_read8; 436 gc->write_reg = bgpio_write8; 437 break; 438 case 16: 439 if (byte_be) { 440 gc->read_reg = bgpio_read16be; 441 gc->write_reg = bgpio_write16be; 442 } else { 443 gc->read_reg = bgpio_read16; 444 gc->write_reg = bgpio_write16; 445 } 446 break; 447 case 32: 448 if (byte_be) { 449 gc->read_reg = bgpio_read32be; 450 gc->write_reg = bgpio_write32be; 451 } else { 452 gc->read_reg = bgpio_read32; 453 gc->write_reg = bgpio_write32; 454 } 455 break; 456 #if BITS_PER_LONG >= 64 457 case 64: 458 if (byte_be) { 459 dev_err(dev, 460 "64 bit big endian byte order unsupported\n"); 461 return -EINVAL; 462 } else { 463 gc->read_reg = bgpio_read64; 464 gc->write_reg = bgpio_write64; 465 } 466 break; 467 #endif /* BITS_PER_LONG >= 64 */ 468 default: 469 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); 470 return -EINVAL; 471 } 472 473 return 0; 474 } 475 476 /* 477 * Create the device and allocate the resources. For setting GPIO's there are 478 * three supported configurations: 479 * 480 * - single input/output register resource (named "dat"). 481 * - set/clear pair (named "set" and "clr"). 482 * - single output register resource and single input resource ("set" and 483 * dat"). 484 * 485 * For the single output register, this drives a 1 by setting a bit and a zero 486 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit 487 * in the set register and clears it by setting a bit in the clear register. 488 * The configuration is detected by which resources are present. 489 * 490 * For setting the GPIO direction, there are three supported configurations: 491 * 492 * - simple bidirection GPIO that requires no configuration. 493 * - an output direction register (named "dirout") where a 1 bit 494 * indicates the GPIO is an output. 495 * - an input direction register (named "dirin") where a 1 bit indicates 496 * the GPIO is an input. 497 */ 498 static int bgpio_setup_io(struct gpio_chip *gc, 499 void __iomem *dat, 500 void __iomem *set, 501 void __iomem *clr, 502 unsigned long flags) 503 { 504 505 gc->reg_dat = dat; 506 if (!gc->reg_dat) 507 return -EINVAL; 508 509 if (set && clr) { 510 gc->reg_set = set; 511 gc->reg_clr = clr; 512 gc->set = bgpio_set_with_clear; 513 gc->set_multiple = bgpio_set_multiple_with_clear; 514 } else if (set && !clr) { 515 gc->reg_set = set; 516 gc->set = bgpio_set_set; 517 gc->set_multiple = bgpio_set_multiple_set; 518 } else if (flags & BGPIOF_NO_OUTPUT) { 519 gc->set = bgpio_set_none; 520 gc->set_multiple = NULL; 521 } else { 522 gc->set = bgpio_set; 523 gc->set_multiple = bgpio_set_multiple; 524 } 525 526 if (!(flags & BGPIOF_UNREADABLE_REG_SET) && 527 (flags & BGPIOF_READ_OUTPUT_REG_SET)) { 528 gc->get = bgpio_get_set; 529 if (!gc->be_bits) 530 gc->get_multiple = bgpio_get_set_multiple; 531 /* 532 * We deliberately avoid assigning the ->get_multiple() call 533 * for big endian mirrored registers which are ALSO reflecting 534 * their value in the set register when used as output. It is 535 * simply too much complexity, let the GPIO core fall back to 536 * reading each line individually in that fringe case. 537 */ 538 } else { 539 gc->get = bgpio_get; 540 if (gc->be_bits) 541 gc->get_multiple = bgpio_get_multiple_be; 542 else 543 gc->get_multiple = bgpio_get_multiple; 544 } 545 546 return 0; 547 } 548 549 static int bgpio_setup_direction(struct gpio_chip *gc, 550 void __iomem *dirout, 551 void __iomem *dirin, 552 unsigned long flags) 553 { 554 if (dirout && dirin) { 555 return -EINVAL; 556 } else if (dirout) { 557 gc->reg_dir = dirout; 558 gc->direction_output = bgpio_dir_out; 559 gc->direction_input = bgpio_dir_in; 560 gc->get_direction = bgpio_get_dir; 561 } else if (dirin) { 562 gc->reg_dir = dirin; 563 gc->direction_output = bgpio_dir_out_inv; 564 gc->direction_input = bgpio_dir_in_inv; 565 gc->get_direction = bgpio_get_dir_inv; 566 } else { 567 if (flags & BGPIOF_NO_OUTPUT) 568 gc->direction_output = bgpio_dir_out_err; 569 else 570 gc->direction_output = bgpio_simple_dir_out; 571 gc->direction_input = bgpio_simple_dir_in; 572 } 573 574 return 0; 575 } 576 577 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) 578 { 579 if (gpio_pin < chip->ngpio) 580 return 0; 581 582 return -EINVAL; 583 } 584 585 int bgpio_init(struct gpio_chip *gc, struct device *dev, 586 unsigned long sz, void __iomem *dat, void __iomem *set, 587 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 588 unsigned long flags) 589 { 590 int ret; 591 592 if (!is_power_of_2(sz)) 593 return -EINVAL; 594 595 gc->bgpio_bits = sz * 8; 596 if (gc->bgpio_bits > BITS_PER_LONG) 597 return -EINVAL; 598 599 spin_lock_init(&gc->bgpio_lock); 600 gc->parent = dev; 601 gc->label = dev_name(dev); 602 gc->base = -1; 603 gc->ngpio = gc->bgpio_bits; 604 gc->request = bgpio_request; 605 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN); 606 607 ret = bgpio_setup_io(gc, dat, set, clr, flags); 608 if (ret) 609 return ret; 610 611 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); 612 if (ret) 613 return ret; 614 615 ret = bgpio_setup_direction(gc, dirout, dirin, flags); 616 if (ret) 617 return ret; 618 619 gc->bgpio_data = gc->read_reg(gc->reg_dat); 620 if (gc->set == bgpio_set_set && 621 !(flags & BGPIOF_UNREADABLE_REG_SET)) 622 gc->bgpio_data = gc->read_reg(gc->reg_set); 623 if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR)) 624 gc->bgpio_dir = gc->read_reg(gc->reg_dir); 625 626 return ret; 627 } 628 EXPORT_SYMBOL_GPL(bgpio_init); 629 630 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) 631 632 static void __iomem *bgpio_map(struct platform_device *pdev, 633 const char *name, 634 resource_size_t sane_sz) 635 { 636 struct resource *r; 637 resource_size_t sz; 638 639 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 640 if (!r) 641 return NULL; 642 643 sz = resource_size(r); 644 if (sz != sane_sz) 645 return IOMEM_ERR_PTR(-EINVAL); 646 647 return devm_ioremap_resource(&pdev->dev, r); 648 } 649 650 #ifdef CONFIG_OF 651 static const struct of_device_id bgpio_of_match[] = { 652 { .compatible = "brcm,bcm6345-gpio" }, 653 { .compatible = "wd,mbl-gpio" }, 654 { .compatible = "ni,169445-nand-gpio" }, 655 { } 656 }; 657 MODULE_DEVICE_TABLE(of, bgpio_of_match); 658 659 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, 660 unsigned long *flags) 661 { 662 struct bgpio_pdata *pdata; 663 664 if (!of_match_device(bgpio_of_match, &pdev->dev)) 665 return NULL; 666 667 pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata), 668 GFP_KERNEL); 669 if (!pdata) 670 return ERR_PTR(-ENOMEM); 671 672 pdata->base = -1; 673 674 if (of_device_is_big_endian(pdev->dev.of_node)) 675 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER; 676 677 if (of_property_read_bool(pdev->dev.of_node, "no-output")) 678 *flags |= BGPIOF_NO_OUTPUT; 679 680 return pdata; 681 } 682 #else 683 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, 684 unsigned long *flags) 685 { 686 return NULL; 687 } 688 #endif /* CONFIG_OF */ 689 690 static int bgpio_pdev_probe(struct platform_device *pdev) 691 { 692 struct device *dev = &pdev->dev; 693 struct resource *r; 694 void __iomem *dat; 695 void __iomem *set; 696 void __iomem *clr; 697 void __iomem *dirout; 698 void __iomem *dirin; 699 unsigned long sz; 700 unsigned long flags = 0; 701 int err; 702 struct gpio_chip *gc; 703 struct bgpio_pdata *pdata; 704 705 pdata = bgpio_parse_dt(pdev, &flags); 706 if (IS_ERR(pdata)) 707 return PTR_ERR(pdata); 708 709 if (!pdata) { 710 pdata = dev_get_platdata(dev); 711 flags = pdev->id_entry->driver_data; 712 } 713 714 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 715 if (!r) 716 return -EINVAL; 717 718 sz = resource_size(r); 719 720 dat = bgpio_map(pdev, "dat", sz); 721 if (IS_ERR(dat)) 722 return PTR_ERR(dat); 723 724 set = bgpio_map(pdev, "set", sz); 725 if (IS_ERR(set)) 726 return PTR_ERR(set); 727 728 clr = bgpio_map(pdev, "clr", sz); 729 if (IS_ERR(clr)) 730 return PTR_ERR(clr); 731 732 dirout = bgpio_map(pdev, "dirout", sz); 733 if (IS_ERR(dirout)) 734 return PTR_ERR(dirout); 735 736 dirin = bgpio_map(pdev, "dirin", sz); 737 if (IS_ERR(dirin)) 738 return PTR_ERR(dirin); 739 740 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); 741 if (!gc) 742 return -ENOMEM; 743 744 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); 745 if (err) 746 return err; 747 748 if (pdata) { 749 if (pdata->label) 750 gc->label = pdata->label; 751 gc->base = pdata->base; 752 if (pdata->ngpio > 0) 753 gc->ngpio = pdata->ngpio; 754 } 755 756 platform_set_drvdata(pdev, gc); 757 758 return devm_gpiochip_add_data(&pdev->dev, gc, NULL); 759 } 760 761 static const struct platform_device_id bgpio_id_table[] = { 762 { 763 .name = "basic-mmio-gpio", 764 .driver_data = 0, 765 }, { 766 .name = "basic-mmio-gpio-be", 767 .driver_data = BGPIOF_BIG_ENDIAN, 768 }, 769 { } 770 }; 771 MODULE_DEVICE_TABLE(platform, bgpio_id_table); 772 773 static struct platform_driver bgpio_driver = { 774 .driver = { 775 .name = "basic-mmio-gpio", 776 .of_match_table = of_match_ptr(bgpio_of_match), 777 }, 778 .id_table = bgpio_id_table, 779 .probe = bgpio_pdev_probe, 780 }; 781 782 module_platform_driver(bgpio_driver); 783 784 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ 785 786 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); 787 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); 788 MODULE_LICENSE("GPL"); 789