xref: /openbmc/linux/drivers/gpio/gpio-mmio.c (revision 3e30a927)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Generic driver for memory-mapped GPIO controllers.
4  *
5  * Copyright 2008 MontaVista Software, Inc.
6  * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com>
7  *
8  * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`.......
9  * ...``                                                         ```````..
10  * ..The simplest form of a GPIO controller that the driver supports is``
11  *  `.just a single "data" register, where GPIO state can be read and/or `
12  *    `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.```````
13  *        `````````
14                                     ___
15 _/~~|___/~|   . ```~~~~~~       ___/___\___     ,~.`.`.`.`````.~~...,,,,...
16 __________|~$@~~~        %~    /o*o*o*o*o*o\   .. Implementing such a GPIO .
17 o        `                     ~~~~\___/~~~~    ` controller in FPGA is ,.`
18                                                  `....trivial..'~`.```.```
19  *                                                    ```````
20  *  .```````~~~~`..`.``.``.
21  * .  The driver supports  `...       ,..```.`~~~```````````````....````.``,,
22  * .   big-endian notation, just`.  .. A bit more sophisticated controllers ,
23  *  . register the device with -be`. .with a pair of set/clear-bit registers ,
24  *   `.. suffix.  ```~~`````....`.`   . affecting the data register and the .`
25  *     ``.`.``...```                  ```.. output pins are also supported.`
26  *                        ^^             `````.`````````.,``~``~``~~``````
27  *                                                   .                  ^^
28  *   ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`..
29  * .. The expectation is that in at least some cases .    ,-~~~-,
30  *  .this will be used with roll-your-own ASIC/FPGA .`     \   /
31  *  .logic in Verilog or VHDL. ~~~`````````..`````~~`       \ /
32  *  ..````````......```````````                             \o_
33  *                                                           |
34  *                              ^^                          / \
35  *
36  *           ...`````~~`.....``.`..........``````.`.``.```........``.
37  *            `  8, 16, 32 and 64 bits registers are supported, and``.
38  *            . the number of GPIOs is determined by the width of   ~
39  *             .. the registers. ,............```.`.`..`.`.~~~.`.`.`~
40  *               `.......````.```
41  */
42 
43 #include <linux/init.h>
44 #include <linux/err.h>
45 #include <linux/bug.h>
46 #include <linux/kernel.h>
47 #include <linux/module.h>
48 #include <linux/spinlock.h>
49 #include <linux/compiler.h>
50 #include <linux/types.h>
51 #include <linux/errno.h>
52 #include <linux/log2.h>
53 #include <linux/ioport.h>
54 #include <linux/io.h>
55 #include <linux/gpio/driver.h>
56 #include <linux/slab.h>
57 #include <linux/bitops.h>
58 #include <linux/platform_device.h>
59 #include <linux/mod_devicetable.h>
60 #include <linux/of.h>
61 #include <linux/of_device.h>
62 
63 static void bgpio_write8(void __iomem *reg, unsigned long data)
64 {
65 	writeb(data, reg);
66 }
67 
68 static unsigned long bgpio_read8(void __iomem *reg)
69 {
70 	return readb(reg);
71 }
72 
73 static void bgpio_write16(void __iomem *reg, unsigned long data)
74 {
75 	writew(data, reg);
76 }
77 
78 static unsigned long bgpio_read16(void __iomem *reg)
79 {
80 	return readw(reg);
81 }
82 
83 static void bgpio_write32(void __iomem *reg, unsigned long data)
84 {
85 	writel(data, reg);
86 }
87 
88 static unsigned long bgpio_read32(void __iomem *reg)
89 {
90 	return readl(reg);
91 }
92 
93 #if BITS_PER_LONG >= 64
94 static void bgpio_write64(void __iomem *reg, unsigned long data)
95 {
96 	writeq(data, reg);
97 }
98 
99 static unsigned long bgpio_read64(void __iomem *reg)
100 {
101 	return readq(reg);
102 }
103 #endif /* BITS_PER_LONG >= 64 */
104 
105 static void bgpio_write16be(void __iomem *reg, unsigned long data)
106 {
107 	iowrite16be(data, reg);
108 }
109 
110 static unsigned long bgpio_read16be(void __iomem *reg)
111 {
112 	return ioread16be(reg);
113 }
114 
115 static void bgpio_write32be(void __iomem *reg, unsigned long data)
116 {
117 	iowrite32be(data, reg);
118 }
119 
120 static unsigned long bgpio_read32be(void __iomem *reg)
121 {
122 	return ioread32be(reg);
123 }
124 
125 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line)
126 {
127 	if (gc->be_bits)
128 		return BIT(gc->bgpio_bits - 1 - line);
129 	return BIT(line);
130 }
131 
132 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio)
133 {
134 	unsigned long pinmask = bgpio_line2mask(gc, gpio);
135 	bool dir = !!(gc->bgpio_dir & pinmask);
136 
137 	if (dir)
138 		return !!(gc->read_reg(gc->reg_set) & pinmask);
139 	else
140 		return !!(gc->read_reg(gc->reg_dat) & pinmask);
141 }
142 
143 /*
144  * This assumes that the bits in the GPIO register are in native endianness.
145  * We only assign the function pointer if we have that.
146  */
147 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask,
148 				  unsigned long *bits)
149 {
150 	unsigned long get_mask = 0;
151 	unsigned long set_mask = 0;
152 
153 	/* Make sure we first clear any bits that are zero when we read the register */
154 	*bits &= ~*mask;
155 
156 	set_mask = *mask & gc->bgpio_dir;
157 	get_mask = *mask & ~gc->bgpio_dir;
158 
159 	if (set_mask)
160 		*bits |= gc->read_reg(gc->reg_set) & set_mask;
161 	if (get_mask)
162 		*bits |= gc->read_reg(gc->reg_dat) & get_mask;
163 
164 	return 0;
165 }
166 
167 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio)
168 {
169 	return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio));
170 }
171 
172 /*
173  * This only works if the bits in the GPIO register are in native endianness.
174  */
175 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask,
176 			      unsigned long *bits)
177 {
178 	/* Make sure we first clear any bits that are zero when we read the register */
179 	*bits &= ~*mask;
180 	*bits |= gc->read_reg(gc->reg_dat) & *mask;
181 	return 0;
182 }
183 
184 /*
185  * With big endian mirrored bit order it becomes more tedious.
186  */
187 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask,
188 				 unsigned long *bits)
189 {
190 	unsigned long readmask = 0;
191 	unsigned long val;
192 	int bit;
193 
194 	/* Make sure we first clear any bits that are zero when we read the register */
195 	*bits &= ~*mask;
196 
197 	/* Create a mirrored mask */
198 	bit = -1;
199 	while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio)
200 		readmask |= bgpio_line2mask(gc, bit);
201 
202 	/* Read the register */
203 	val = gc->read_reg(gc->reg_dat) & readmask;
204 
205 	/*
206 	 * Mirror the result into the "bits" result, this will give line 0
207 	 * in bit 0 ... line 31 in bit 31 for a 32bit register.
208 	 */
209 	bit = -1;
210 	while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio)
211 		*bits |= bgpio_line2mask(gc, bit);
212 
213 	return 0;
214 }
215 
216 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val)
217 {
218 }
219 
220 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
221 {
222 	unsigned long mask = bgpio_line2mask(gc, gpio);
223 	unsigned long flags;
224 
225 	spin_lock_irqsave(&gc->bgpio_lock, flags);
226 
227 	if (val)
228 		gc->bgpio_data |= mask;
229 	else
230 		gc->bgpio_data &= ~mask;
231 
232 	gc->write_reg(gc->reg_dat, gc->bgpio_data);
233 
234 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
235 }
236 
237 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio,
238 				 int val)
239 {
240 	unsigned long mask = bgpio_line2mask(gc, gpio);
241 
242 	if (val)
243 		gc->write_reg(gc->reg_set, mask);
244 	else
245 		gc->write_reg(gc->reg_clr, mask);
246 }
247 
248 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val)
249 {
250 	unsigned long mask = bgpio_line2mask(gc, gpio);
251 	unsigned long flags;
252 
253 	spin_lock_irqsave(&gc->bgpio_lock, flags);
254 
255 	if (val)
256 		gc->bgpio_data |= mask;
257 	else
258 		gc->bgpio_data &= ~mask;
259 
260 	gc->write_reg(gc->reg_set, gc->bgpio_data);
261 
262 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
263 }
264 
265 static void bgpio_multiple_get_masks(struct gpio_chip *gc,
266 				     unsigned long *mask, unsigned long *bits,
267 				     unsigned long *set_mask,
268 				     unsigned long *clear_mask)
269 {
270 	int i;
271 
272 	*set_mask = 0;
273 	*clear_mask = 0;
274 
275 	for (i = 0; i < gc->bgpio_bits; i++) {
276 		if (*mask == 0)
277 			break;
278 		if (__test_and_clear_bit(i, mask)) {
279 			if (test_bit(i, bits))
280 				*set_mask |= bgpio_line2mask(gc, i);
281 			else
282 				*clear_mask |= bgpio_line2mask(gc, i);
283 		}
284 	}
285 }
286 
287 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc,
288 					  unsigned long *mask,
289 					  unsigned long *bits,
290 					  void __iomem *reg)
291 {
292 	unsigned long flags;
293 	unsigned long set_mask, clear_mask;
294 
295 	spin_lock_irqsave(&gc->bgpio_lock, flags);
296 
297 	bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
298 
299 	gc->bgpio_data |= set_mask;
300 	gc->bgpio_data &= ~clear_mask;
301 
302 	gc->write_reg(reg, gc->bgpio_data);
303 
304 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
305 }
306 
307 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask,
308 			       unsigned long *bits)
309 {
310 	bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat);
311 }
312 
313 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask,
314 				   unsigned long *bits)
315 {
316 	bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set);
317 }
318 
319 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc,
320 					  unsigned long *mask,
321 					  unsigned long *bits)
322 {
323 	unsigned long set_mask, clear_mask;
324 
325 	bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask);
326 
327 	if (set_mask)
328 		gc->write_reg(gc->reg_set, set_mask);
329 	if (clear_mask)
330 		gc->write_reg(gc->reg_clr, clear_mask);
331 }
332 
333 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio)
334 {
335 	return 0;
336 }
337 
338 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio,
339 				int val)
340 {
341 	return -EINVAL;
342 }
343 
344 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio,
345 				int val)
346 {
347 	gc->set(gc, gpio, val);
348 
349 	return 0;
350 }
351 
352 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
353 {
354 	unsigned long flags;
355 
356 	spin_lock_irqsave(&gc->bgpio_lock, flags);
357 
358 	gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio);
359 
360 	if (gc->reg_dir_in)
361 		gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
362 	if (gc->reg_dir_out)
363 		gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
364 
365 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
366 
367 	return 0;
368 }
369 
370 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio)
371 {
372 	/* Return 0 if output, 1 if input */
373 	if (gc->bgpio_dir_unreadable) {
374 		if (gc->bgpio_dir & bgpio_line2mask(gc, gpio))
375 			return GPIO_LINE_DIRECTION_OUT;
376 		return GPIO_LINE_DIRECTION_IN;
377 	}
378 
379 	if (gc->reg_dir_out) {
380 		if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio))
381 			return GPIO_LINE_DIRECTION_OUT;
382 		return GPIO_LINE_DIRECTION_IN;
383 	}
384 
385 	if (gc->reg_dir_in)
386 		if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio)))
387 			return GPIO_LINE_DIRECTION_OUT;
388 
389 	return GPIO_LINE_DIRECTION_IN;
390 }
391 
392 static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
393 {
394 	unsigned long flags;
395 
396 	gc->set(gc, gpio, val);
397 
398 	spin_lock_irqsave(&gc->bgpio_lock, flags);
399 
400 	gc->bgpio_dir |= bgpio_line2mask(gc, gpio);
401 
402 	if (gc->reg_dir_in)
403 		gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
404 	if (gc->reg_dir_out)
405 		gc->write_reg(gc->reg_dir_out, gc->bgpio_dir);
406 
407 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
408 
409 	return 0;
410 }
411 
412 static int bgpio_setup_accessors(struct device *dev,
413 				 struct gpio_chip *gc,
414 				 bool byte_be)
415 {
416 
417 	switch (gc->bgpio_bits) {
418 	case 8:
419 		gc->read_reg	= bgpio_read8;
420 		gc->write_reg	= bgpio_write8;
421 		break;
422 	case 16:
423 		if (byte_be) {
424 			gc->read_reg	= bgpio_read16be;
425 			gc->write_reg	= bgpio_write16be;
426 		} else {
427 			gc->read_reg	= bgpio_read16;
428 			gc->write_reg	= bgpio_write16;
429 		}
430 		break;
431 	case 32:
432 		if (byte_be) {
433 			gc->read_reg	= bgpio_read32be;
434 			gc->write_reg	= bgpio_write32be;
435 		} else {
436 			gc->read_reg	= bgpio_read32;
437 			gc->write_reg	= bgpio_write32;
438 		}
439 		break;
440 #if BITS_PER_LONG >= 64
441 	case 64:
442 		if (byte_be) {
443 			dev_err(dev,
444 				"64 bit big endian byte order unsupported\n");
445 			return -EINVAL;
446 		} else {
447 			gc->read_reg	= bgpio_read64;
448 			gc->write_reg	= bgpio_write64;
449 		}
450 		break;
451 #endif /* BITS_PER_LONG >= 64 */
452 	default:
453 		dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits);
454 		return -EINVAL;
455 	}
456 
457 	return 0;
458 }
459 
460 /*
461  * Create the device and allocate the resources.  For setting GPIO's there are
462  * three supported configurations:
463  *
464  *	- single input/output register resource (named "dat").
465  *	- set/clear pair (named "set" and "clr").
466  *	- single output register resource and single input resource ("set" and
467  *	dat").
468  *
469  * For the single output register, this drives a 1 by setting a bit and a zero
470  * by clearing a bit.  For the set clr pair, this drives a 1 by setting a bit
471  * in the set register and clears it by setting a bit in the clear register.
472  * The configuration is detected by which resources are present.
473  *
474  * For setting the GPIO direction, there are three supported configurations:
475  *
476  *	- simple bidirection GPIO that requires no configuration.
477  *	- an output direction register (named "dirout") where a 1 bit
478  *	indicates the GPIO is an output.
479  *	- an input direction register (named "dirin") where a 1 bit indicates
480  *	the GPIO is an input.
481  */
482 static int bgpio_setup_io(struct gpio_chip *gc,
483 			  void __iomem *dat,
484 			  void __iomem *set,
485 			  void __iomem *clr,
486 			  unsigned long flags)
487 {
488 
489 	gc->reg_dat = dat;
490 	if (!gc->reg_dat)
491 		return -EINVAL;
492 
493 	if (set && clr) {
494 		gc->reg_set = set;
495 		gc->reg_clr = clr;
496 		gc->set = bgpio_set_with_clear;
497 		gc->set_multiple = bgpio_set_multiple_with_clear;
498 	} else if (set && !clr) {
499 		gc->reg_set = set;
500 		gc->set = bgpio_set_set;
501 		gc->set_multiple = bgpio_set_multiple_set;
502 	} else if (flags & BGPIOF_NO_OUTPUT) {
503 		gc->set = bgpio_set_none;
504 		gc->set_multiple = NULL;
505 	} else {
506 		gc->set = bgpio_set;
507 		gc->set_multiple = bgpio_set_multiple;
508 	}
509 
510 	if (!(flags & BGPIOF_UNREADABLE_REG_SET) &&
511 	    (flags & BGPIOF_READ_OUTPUT_REG_SET)) {
512 		gc->get = bgpio_get_set;
513 		if (!gc->be_bits)
514 			gc->get_multiple = bgpio_get_set_multiple;
515 		/*
516 		 * We deliberately avoid assigning the ->get_multiple() call
517 		 * for big endian mirrored registers which are ALSO reflecting
518 		 * their value in the set register when used as output. It is
519 		 * simply too much complexity, let the GPIO core fall back to
520 		 * reading each line individually in that fringe case.
521 		 */
522 	} else {
523 		gc->get = bgpio_get;
524 		if (gc->be_bits)
525 			gc->get_multiple = bgpio_get_multiple_be;
526 		else
527 			gc->get_multiple = bgpio_get_multiple;
528 	}
529 
530 	return 0;
531 }
532 
533 static int bgpio_setup_direction(struct gpio_chip *gc,
534 				 void __iomem *dirout,
535 				 void __iomem *dirin,
536 				 unsigned long flags)
537 {
538 	if (dirout || dirin) {
539 		gc->reg_dir_out = dirout;
540 		gc->reg_dir_in = dirin;
541 		gc->direction_output = bgpio_dir_out;
542 		gc->direction_input = bgpio_dir_in;
543 		gc->get_direction = bgpio_get_dir;
544 	} else {
545 		if (flags & BGPIOF_NO_OUTPUT)
546 			gc->direction_output = bgpio_dir_out_err;
547 		else
548 			gc->direction_output = bgpio_simple_dir_out;
549 		gc->direction_input = bgpio_simple_dir_in;
550 	}
551 
552 	return 0;
553 }
554 
555 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin)
556 {
557 	if (gpio_pin < chip->ngpio)
558 		return 0;
559 
560 	return -EINVAL;
561 }
562 
563 /**
564  * bgpio_init() - Initialize generic GPIO accessor functions
565  * @gc: the GPIO chip to set up
566  * @dev: the parent device of the new GPIO chip (compulsory)
567  * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4
568  * @dat: MMIO address for the register to READ the value of the GPIO lines, it
569  *	is expected that a 1 in the corresponding bit in this register means the
570  *	line is asserted
571  * @set: MMIO address for the register to SET the value of the GPIO lines, it is
572  *	expected that we write the line with 1 in this register to drive the GPIO line
573  *	high.
574  * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is
575  *	expected that we write the line with 1 in this register to drive the GPIO line
576  *	low. It is allowed to leave this address as NULL, in that case the SET register
577  *	will be assumed to also clear the GPIO lines, by actively writing the line
578  *	with 0.
579  * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed
580  *	that setting a line to 1 in this register will turn that line into an
581  *	output line. Conversely, setting the line to 0 will turn that line into
582  *	an input.
583  * @dirin: MMIO address for the register to set this line as INPUT. It is assumed
584  *	that setting a line to 1 in this register will turn that line into an
585  *	input line. Conversely, setting the line to 0 will turn that line into
586  *	an output.
587  * @flags: Different flags that will affect the behaviour of the device, such as
588  *	endianness etc.
589  */
590 int bgpio_init(struct gpio_chip *gc, struct device *dev,
591 	       unsigned long sz, void __iomem *dat, void __iomem *set,
592 	       void __iomem *clr, void __iomem *dirout, void __iomem *dirin,
593 	       unsigned long flags)
594 {
595 	int ret;
596 
597 	if (!is_power_of_2(sz))
598 		return -EINVAL;
599 
600 	gc->bgpio_bits = sz * 8;
601 	if (gc->bgpio_bits > BITS_PER_LONG)
602 		return -EINVAL;
603 
604 	spin_lock_init(&gc->bgpio_lock);
605 	gc->parent = dev;
606 	gc->label = dev_name(dev);
607 	gc->base = -1;
608 	gc->ngpio = gc->bgpio_bits;
609 	gc->request = bgpio_request;
610 	gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN);
611 
612 	ret = bgpio_setup_io(gc, dat, set, clr, flags);
613 	if (ret)
614 		return ret;
615 
616 	ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER);
617 	if (ret)
618 		return ret;
619 
620 	ret = bgpio_setup_direction(gc, dirout, dirin, flags);
621 	if (ret)
622 		return ret;
623 
624 	gc->bgpio_data = gc->read_reg(gc->reg_dat);
625 	if (gc->set == bgpio_set_set &&
626 			!(flags & BGPIOF_UNREADABLE_REG_SET))
627 		gc->bgpio_data = gc->read_reg(gc->reg_set);
628 
629 	if (flags & BGPIOF_UNREADABLE_REG_DIR)
630 		gc->bgpio_dir_unreadable = true;
631 
632 	/*
633 	 * Inspect hardware to find initial direction setting.
634 	 */
635 	if ((gc->reg_dir_out || gc->reg_dir_in) &&
636 	    !(flags & BGPIOF_UNREADABLE_REG_DIR)) {
637 		if (gc->reg_dir_out)
638 			gc->bgpio_dir = gc->read_reg(gc->reg_dir_out);
639 		else if (gc->reg_dir_in)
640 			gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in);
641 		/*
642 		 * If we have two direction registers, synchronise
643 		 * input setting to output setting, the library
644 		 * can not handle a line being input and output at
645 		 * the same time.
646 		 */
647 		if (gc->reg_dir_out && gc->reg_dir_in)
648 			gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir);
649 	}
650 
651 	return ret;
652 }
653 EXPORT_SYMBOL_GPL(bgpio_init);
654 
655 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM)
656 
657 static void __iomem *bgpio_map(struct platform_device *pdev,
658 			       const char *name,
659 			       resource_size_t sane_sz)
660 {
661 	struct resource *r;
662 	resource_size_t sz;
663 
664 	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
665 	if (!r)
666 		return NULL;
667 
668 	sz = resource_size(r);
669 	if (sz != sane_sz)
670 		return IOMEM_ERR_PTR(-EINVAL);
671 
672 	return devm_ioremap_resource(&pdev->dev, r);
673 }
674 
675 #ifdef CONFIG_OF
676 static const struct of_device_id bgpio_of_match[] = {
677 	{ .compatible = "brcm,bcm6345-gpio" },
678 	{ .compatible = "wd,mbl-gpio" },
679 	{ .compatible = "ni,169445-nand-gpio" },
680 	{ }
681 };
682 MODULE_DEVICE_TABLE(of, bgpio_of_match);
683 
684 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
685 					  unsigned long *flags)
686 {
687 	struct bgpio_pdata *pdata;
688 
689 	if (!of_match_device(bgpio_of_match, &pdev->dev))
690 		return NULL;
691 
692 	pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata),
693 			     GFP_KERNEL);
694 	if (!pdata)
695 		return ERR_PTR(-ENOMEM);
696 
697 	pdata->base = -1;
698 
699 	if (of_device_is_big_endian(pdev->dev.of_node))
700 		*flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER;
701 
702 	if (of_property_read_bool(pdev->dev.of_node, "no-output"))
703 		*flags |= BGPIOF_NO_OUTPUT;
704 
705 	return pdata;
706 }
707 #else
708 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev,
709 					  unsigned long *flags)
710 {
711 	return NULL;
712 }
713 #endif /* CONFIG_OF */
714 
715 static int bgpio_pdev_probe(struct platform_device *pdev)
716 {
717 	struct device *dev = &pdev->dev;
718 	struct resource *r;
719 	void __iomem *dat;
720 	void __iomem *set;
721 	void __iomem *clr;
722 	void __iomem *dirout;
723 	void __iomem *dirin;
724 	unsigned long sz;
725 	unsigned long flags = 0;
726 	int err;
727 	struct gpio_chip *gc;
728 	struct bgpio_pdata *pdata;
729 
730 	pdata = bgpio_parse_dt(pdev, &flags);
731 	if (IS_ERR(pdata))
732 		return PTR_ERR(pdata);
733 
734 	if (!pdata) {
735 		pdata = dev_get_platdata(dev);
736 		flags = pdev->id_entry->driver_data;
737 	}
738 
739 	r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
740 	if (!r)
741 		return -EINVAL;
742 
743 	sz = resource_size(r);
744 
745 	dat = bgpio_map(pdev, "dat", sz);
746 	if (IS_ERR(dat))
747 		return PTR_ERR(dat);
748 
749 	set = bgpio_map(pdev, "set", sz);
750 	if (IS_ERR(set))
751 		return PTR_ERR(set);
752 
753 	clr = bgpio_map(pdev, "clr", sz);
754 	if (IS_ERR(clr))
755 		return PTR_ERR(clr);
756 
757 	dirout = bgpio_map(pdev, "dirout", sz);
758 	if (IS_ERR(dirout))
759 		return PTR_ERR(dirout);
760 
761 	dirin = bgpio_map(pdev, "dirin", sz);
762 	if (IS_ERR(dirin))
763 		return PTR_ERR(dirin);
764 
765 	gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL);
766 	if (!gc)
767 		return -ENOMEM;
768 
769 	err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags);
770 	if (err)
771 		return err;
772 
773 	if (pdata) {
774 		if (pdata->label)
775 			gc->label = pdata->label;
776 		gc->base = pdata->base;
777 		if (pdata->ngpio > 0)
778 			gc->ngpio = pdata->ngpio;
779 	}
780 
781 	platform_set_drvdata(pdev, gc);
782 
783 	return devm_gpiochip_add_data(&pdev->dev, gc, NULL);
784 }
785 
786 static const struct platform_device_id bgpio_id_table[] = {
787 	{
788 		.name		= "basic-mmio-gpio",
789 		.driver_data	= 0,
790 	}, {
791 		.name		= "basic-mmio-gpio-be",
792 		.driver_data	= BGPIOF_BIG_ENDIAN,
793 	},
794 	{ }
795 };
796 MODULE_DEVICE_TABLE(platform, bgpio_id_table);
797 
798 static struct platform_driver bgpio_driver = {
799 	.driver = {
800 		.name = "basic-mmio-gpio",
801 		.of_match_table = of_match_ptr(bgpio_of_match),
802 	},
803 	.id_table = bgpio_id_table,
804 	.probe = bgpio_pdev_probe,
805 };
806 
807 module_platform_driver(bgpio_driver);
808 
809 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */
810 
811 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers");
812 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>");
813 MODULE_LICENSE("GPL");
814