1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Generic driver for memory-mapped GPIO controllers. 4 * 5 * Copyright 2008 MontaVista Software, Inc. 6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> 7 * 8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... 9 * ...`` ```````.. 10 * ..The simplest form of a GPIO controller that the driver supports is`` 11 * `.just a single "data" register, where GPIO state can be read and/or ` 12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` 13 * ````````` 14 ___ 15 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... 16 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . 17 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` 18 `....trivial..'~`.```.``` 19 * ``````` 20 * .```````~~~~`..`.``.``. 21 * . The driver supports `... ,..```.`~~~```````````````....````.``,, 22 * . big-endian notation, just`. .. A bit more sophisticated controllers , 23 * . register the device with -be`. .with a pair of set/clear-bit registers , 24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .` 25 * ``.`.``...``` ```.. output pins are also supported.` 26 * ^^ `````.`````````.,``~``~``~~`````` 27 * . ^^ 28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. 29 * .. The expectation is that in at least some cases . ,-~~~-, 30 * .this will be used with roll-your-own ASIC/FPGA .` \ / 31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / 32 * ..````````......``````````` \o_ 33 * | 34 * ^^ / \ 35 * 36 * ...`````~~`.....``.`..........``````.`.``.```........``. 37 * ` 8, 16, 32 and 64 bits registers are supported, and``. 38 * . the number of GPIOs is determined by the width of ~ 39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ 40 * `.......````.``` 41 */ 42 43 #include <linux/init.h> 44 #include <linux/err.h> 45 #include <linux/bug.h> 46 #include <linux/kernel.h> 47 #include <linux/module.h> 48 #include <linux/spinlock.h> 49 #include <linux/compiler.h> 50 #include <linux/types.h> 51 #include <linux/errno.h> 52 #include <linux/log2.h> 53 #include <linux/ioport.h> 54 #include <linux/io.h> 55 #include <linux/gpio/driver.h> 56 #include <linux/slab.h> 57 #include <linux/bitops.h> 58 #include <linux/platform_device.h> 59 #include <linux/mod_devicetable.h> 60 #include <linux/of.h> 61 #include <linux/of_device.h> 62 63 static void bgpio_write8(void __iomem *reg, unsigned long data) 64 { 65 writeb(data, reg); 66 } 67 68 static unsigned long bgpio_read8(void __iomem *reg) 69 { 70 return readb(reg); 71 } 72 73 static void bgpio_write16(void __iomem *reg, unsigned long data) 74 { 75 writew(data, reg); 76 } 77 78 static unsigned long bgpio_read16(void __iomem *reg) 79 { 80 return readw(reg); 81 } 82 83 static void bgpio_write32(void __iomem *reg, unsigned long data) 84 { 85 writel(data, reg); 86 } 87 88 static unsigned long bgpio_read32(void __iomem *reg) 89 { 90 return readl(reg); 91 } 92 93 #if BITS_PER_LONG >= 64 94 static void bgpio_write64(void __iomem *reg, unsigned long data) 95 { 96 writeq(data, reg); 97 } 98 99 static unsigned long bgpio_read64(void __iomem *reg) 100 { 101 return readq(reg); 102 } 103 #endif /* BITS_PER_LONG >= 64 */ 104 105 static void bgpio_write16be(void __iomem *reg, unsigned long data) 106 { 107 iowrite16be(data, reg); 108 } 109 110 static unsigned long bgpio_read16be(void __iomem *reg) 111 { 112 return ioread16be(reg); 113 } 114 115 static void bgpio_write32be(void __iomem *reg, unsigned long data) 116 { 117 iowrite32be(data, reg); 118 } 119 120 static unsigned long bgpio_read32be(void __iomem *reg) 121 { 122 return ioread32be(reg); 123 } 124 125 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) 126 { 127 if (gc->be_bits) 128 return BIT(gc->bgpio_bits - 1 - line); 129 return BIT(line); 130 } 131 132 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) 133 { 134 unsigned long pinmask = bgpio_line2mask(gc, gpio); 135 bool dir = !!(gc->bgpio_dir & pinmask); 136 137 if (dir) 138 return !!(gc->read_reg(gc->reg_set) & pinmask); 139 else 140 return !!(gc->read_reg(gc->reg_dat) & pinmask); 141 } 142 143 /* 144 * This assumes that the bits in the GPIO register are in native endianness. 145 * We only assign the function pointer if we have that. 146 */ 147 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, 148 unsigned long *bits) 149 { 150 unsigned long get_mask = 0; 151 unsigned long set_mask = 0; 152 153 /* Make sure we first clear any bits that are zero when we read the register */ 154 *bits &= ~*mask; 155 156 set_mask = *mask & gc->bgpio_dir; 157 get_mask = *mask & ~gc->bgpio_dir; 158 159 if (set_mask) 160 *bits |= gc->read_reg(gc->reg_set) & set_mask; 161 if (get_mask) 162 *bits |= gc->read_reg(gc->reg_dat) & get_mask; 163 164 return 0; 165 } 166 167 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) 168 { 169 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); 170 } 171 172 /* 173 * This only works if the bits in the GPIO register are in native endianness. 174 */ 175 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, 176 unsigned long *bits) 177 { 178 /* Make sure we first clear any bits that are zero when we read the register */ 179 *bits &= ~*mask; 180 *bits |= gc->read_reg(gc->reg_dat) & *mask; 181 return 0; 182 } 183 184 /* 185 * With big endian mirrored bit order it becomes more tedious. 186 */ 187 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, 188 unsigned long *bits) 189 { 190 unsigned long readmask = 0; 191 unsigned long val; 192 int bit; 193 194 /* Make sure we first clear any bits that are zero when we read the register */ 195 *bits &= ~*mask; 196 197 /* Create a mirrored mask */ 198 bit = -1; 199 while ((bit = find_next_bit(mask, gc->ngpio, bit + 1)) < gc->ngpio) 200 readmask |= bgpio_line2mask(gc, bit); 201 202 /* Read the register */ 203 val = gc->read_reg(gc->reg_dat) & readmask; 204 205 /* 206 * Mirror the result into the "bits" result, this will give line 0 207 * in bit 0 ... line 31 in bit 31 for a 32bit register. 208 */ 209 bit = -1; 210 while ((bit = find_next_bit(&val, gc->ngpio, bit + 1)) < gc->ngpio) 211 *bits |= bgpio_line2mask(gc, bit); 212 213 return 0; 214 } 215 216 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) 217 { 218 } 219 220 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 221 { 222 unsigned long mask = bgpio_line2mask(gc, gpio); 223 unsigned long flags; 224 225 spin_lock_irqsave(&gc->bgpio_lock, flags); 226 227 if (val) 228 gc->bgpio_data |= mask; 229 else 230 gc->bgpio_data &= ~mask; 231 232 gc->write_reg(gc->reg_dat, gc->bgpio_data); 233 234 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 235 } 236 237 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, 238 int val) 239 { 240 unsigned long mask = bgpio_line2mask(gc, gpio); 241 242 if (val) 243 gc->write_reg(gc->reg_set, mask); 244 else 245 gc->write_reg(gc->reg_clr, mask); 246 } 247 248 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) 249 { 250 unsigned long mask = bgpio_line2mask(gc, gpio); 251 unsigned long flags; 252 253 spin_lock_irqsave(&gc->bgpio_lock, flags); 254 255 if (val) 256 gc->bgpio_data |= mask; 257 else 258 gc->bgpio_data &= ~mask; 259 260 gc->write_reg(gc->reg_set, gc->bgpio_data); 261 262 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 263 } 264 265 static void bgpio_multiple_get_masks(struct gpio_chip *gc, 266 unsigned long *mask, unsigned long *bits, 267 unsigned long *set_mask, 268 unsigned long *clear_mask) 269 { 270 int i; 271 272 *set_mask = 0; 273 *clear_mask = 0; 274 275 for (i = 0; i < gc->bgpio_bits; i++) { 276 if (*mask == 0) 277 break; 278 if (__test_and_clear_bit(i, mask)) { 279 if (test_bit(i, bits)) 280 *set_mask |= bgpio_line2mask(gc, i); 281 else 282 *clear_mask |= bgpio_line2mask(gc, i); 283 } 284 } 285 } 286 287 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, 288 unsigned long *mask, 289 unsigned long *bits, 290 void __iomem *reg) 291 { 292 unsigned long flags; 293 unsigned long set_mask, clear_mask; 294 295 spin_lock_irqsave(&gc->bgpio_lock, flags); 296 297 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 298 299 gc->bgpio_data |= set_mask; 300 gc->bgpio_data &= ~clear_mask; 301 302 gc->write_reg(reg, gc->bgpio_data); 303 304 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 305 } 306 307 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 308 unsigned long *bits) 309 { 310 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); 311 } 312 313 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, 314 unsigned long *bits) 315 { 316 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); 317 } 318 319 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, 320 unsigned long *mask, 321 unsigned long *bits) 322 { 323 unsigned long set_mask, clear_mask; 324 325 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 326 327 if (set_mask) 328 gc->write_reg(gc->reg_set, set_mask); 329 if (clear_mask) 330 gc->write_reg(gc->reg_clr, clear_mask); 331 } 332 333 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) 334 { 335 return 0; 336 } 337 338 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, 339 int val) 340 { 341 return -EINVAL; 342 } 343 344 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, 345 int val) 346 { 347 gc->set(gc, gpio, val); 348 349 return 0; 350 } 351 352 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 353 { 354 unsigned long flags; 355 356 spin_lock_irqsave(&gc->bgpio_lock, flags); 357 358 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); 359 360 if (gc->reg_dir_in) 361 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 362 if (gc->reg_dir_out) 363 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); 364 365 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 366 367 return 0; 368 } 369 370 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) 371 { 372 /* Return 0 if output, 1 if input */ 373 if (gc->bgpio_dir_unreadable) { 374 if (gc->bgpio_dir & bgpio_line2mask(gc, gpio)) 375 return GPIO_LINE_DIRECTION_OUT; 376 return GPIO_LINE_DIRECTION_IN; 377 } 378 379 if (gc->reg_dir_out) { 380 if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio)) 381 return GPIO_LINE_DIRECTION_OUT; 382 return GPIO_LINE_DIRECTION_IN; 383 } 384 385 if (gc->reg_dir_in) 386 if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio))) 387 return GPIO_LINE_DIRECTION_OUT; 388 389 return GPIO_LINE_DIRECTION_IN; 390 } 391 392 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 393 { 394 unsigned long flags; 395 396 spin_lock_irqsave(&gc->bgpio_lock, flags); 397 398 gc->bgpio_dir |= bgpio_line2mask(gc, gpio); 399 400 if (gc->reg_dir_in) 401 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 402 if (gc->reg_dir_out) 403 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); 404 405 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 406 } 407 408 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, 409 int val) 410 { 411 bgpio_dir_out(gc, gpio, val); 412 gc->set(gc, gpio, val); 413 return 0; 414 } 415 416 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, 417 int val) 418 { 419 gc->set(gc, gpio, val); 420 bgpio_dir_out(gc, gpio, val); 421 return 0; 422 } 423 424 static int bgpio_setup_accessors(struct device *dev, 425 struct gpio_chip *gc, 426 bool byte_be) 427 { 428 429 switch (gc->bgpio_bits) { 430 case 8: 431 gc->read_reg = bgpio_read8; 432 gc->write_reg = bgpio_write8; 433 break; 434 case 16: 435 if (byte_be) { 436 gc->read_reg = bgpio_read16be; 437 gc->write_reg = bgpio_write16be; 438 } else { 439 gc->read_reg = bgpio_read16; 440 gc->write_reg = bgpio_write16; 441 } 442 break; 443 case 32: 444 if (byte_be) { 445 gc->read_reg = bgpio_read32be; 446 gc->write_reg = bgpio_write32be; 447 } else { 448 gc->read_reg = bgpio_read32; 449 gc->write_reg = bgpio_write32; 450 } 451 break; 452 #if BITS_PER_LONG >= 64 453 case 64: 454 if (byte_be) { 455 dev_err(dev, 456 "64 bit big endian byte order unsupported\n"); 457 return -EINVAL; 458 } else { 459 gc->read_reg = bgpio_read64; 460 gc->write_reg = bgpio_write64; 461 } 462 break; 463 #endif /* BITS_PER_LONG >= 64 */ 464 default: 465 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); 466 return -EINVAL; 467 } 468 469 return 0; 470 } 471 472 /* 473 * Create the device and allocate the resources. For setting GPIO's there are 474 * three supported configurations: 475 * 476 * - single input/output register resource (named "dat"). 477 * - set/clear pair (named "set" and "clr"). 478 * - single output register resource and single input resource ("set" and 479 * dat"). 480 * 481 * For the single output register, this drives a 1 by setting a bit and a zero 482 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit 483 * in the set register and clears it by setting a bit in the clear register. 484 * The configuration is detected by which resources are present. 485 * 486 * For setting the GPIO direction, there are three supported configurations: 487 * 488 * - simple bidirection GPIO that requires no configuration. 489 * - an output direction register (named "dirout") where a 1 bit 490 * indicates the GPIO is an output. 491 * - an input direction register (named "dirin") where a 1 bit indicates 492 * the GPIO is an input. 493 */ 494 static int bgpio_setup_io(struct gpio_chip *gc, 495 void __iomem *dat, 496 void __iomem *set, 497 void __iomem *clr, 498 unsigned long flags) 499 { 500 501 gc->reg_dat = dat; 502 if (!gc->reg_dat) 503 return -EINVAL; 504 505 if (set && clr) { 506 gc->reg_set = set; 507 gc->reg_clr = clr; 508 gc->set = bgpio_set_with_clear; 509 gc->set_multiple = bgpio_set_multiple_with_clear; 510 } else if (set && !clr) { 511 gc->reg_set = set; 512 gc->set = bgpio_set_set; 513 gc->set_multiple = bgpio_set_multiple_set; 514 } else if (flags & BGPIOF_NO_OUTPUT) { 515 gc->set = bgpio_set_none; 516 gc->set_multiple = NULL; 517 } else { 518 gc->set = bgpio_set; 519 gc->set_multiple = bgpio_set_multiple; 520 } 521 522 if (!(flags & BGPIOF_UNREADABLE_REG_SET) && 523 (flags & BGPIOF_READ_OUTPUT_REG_SET)) { 524 gc->get = bgpio_get_set; 525 if (!gc->be_bits) 526 gc->get_multiple = bgpio_get_set_multiple; 527 /* 528 * We deliberately avoid assigning the ->get_multiple() call 529 * for big endian mirrored registers which are ALSO reflecting 530 * their value in the set register when used as output. It is 531 * simply too much complexity, let the GPIO core fall back to 532 * reading each line individually in that fringe case. 533 */ 534 } else { 535 gc->get = bgpio_get; 536 if (gc->be_bits) 537 gc->get_multiple = bgpio_get_multiple_be; 538 else 539 gc->get_multiple = bgpio_get_multiple; 540 } 541 542 return 0; 543 } 544 545 static int bgpio_setup_direction(struct gpio_chip *gc, 546 void __iomem *dirout, 547 void __iomem *dirin, 548 unsigned long flags) 549 { 550 if (dirout || dirin) { 551 gc->reg_dir_out = dirout; 552 gc->reg_dir_in = dirin; 553 if (flags & BGPIOF_NO_SET_ON_INPUT) 554 gc->direction_output = bgpio_dir_out_dir_first; 555 else 556 gc->direction_output = bgpio_dir_out_val_first; 557 gc->direction_input = bgpio_dir_in; 558 gc->get_direction = bgpio_get_dir; 559 } else { 560 if (flags & BGPIOF_NO_OUTPUT) 561 gc->direction_output = bgpio_dir_out_err; 562 else 563 gc->direction_output = bgpio_simple_dir_out; 564 gc->direction_input = bgpio_simple_dir_in; 565 } 566 567 return 0; 568 } 569 570 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) 571 { 572 if (gpio_pin < chip->ngpio) 573 return 0; 574 575 return -EINVAL; 576 } 577 578 /** 579 * bgpio_init() - Initialize generic GPIO accessor functions 580 * @gc: the GPIO chip to set up 581 * @dev: the parent device of the new GPIO chip (compulsory) 582 * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4 583 * @dat: MMIO address for the register to READ the value of the GPIO lines, it 584 * is expected that a 1 in the corresponding bit in this register means the 585 * line is asserted 586 * @set: MMIO address for the register to SET the value of the GPIO lines, it is 587 * expected that we write the line with 1 in this register to drive the GPIO line 588 * high. 589 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is 590 * expected that we write the line with 1 in this register to drive the GPIO line 591 * low. It is allowed to leave this address as NULL, in that case the SET register 592 * will be assumed to also clear the GPIO lines, by actively writing the line 593 * with 0. 594 * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed 595 * that setting a line to 1 in this register will turn that line into an 596 * output line. Conversely, setting the line to 0 will turn that line into 597 * an input. 598 * @dirin: MMIO address for the register to set this line as INPUT. It is assumed 599 * that setting a line to 1 in this register will turn that line into an 600 * input line. Conversely, setting the line to 0 will turn that line into 601 * an output. 602 * @flags: Different flags that will affect the behaviour of the device, such as 603 * endianness etc. 604 */ 605 int bgpio_init(struct gpio_chip *gc, struct device *dev, 606 unsigned long sz, void __iomem *dat, void __iomem *set, 607 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 608 unsigned long flags) 609 { 610 int ret; 611 612 if (!is_power_of_2(sz)) 613 return -EINVAL; 614 615 gc->bgpio_bits = sz * 8; 616 if (gc->bgpio_bits > BITS_PER_LONG) 617 return -EINVAL; 618 619 spin_lock_init(&gc->bgpio_lock); 620 gc->parent = dev; 621 gc->label = dev_name(dev); 622 gc->base = -1; 623 gc->ngpio = gc->bgpio_bits; 624 gc->request = bgpio_request; 625 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN); 626 627 ret = bgpio_setup_io(gc, dat, set, clr, flags); 628 if (ret) 629 return ret; 630 631 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); 632 if (ret) 633 return ret; 634 635 ret = bgpio_setup_direction(gc, dirout, dirin, flags); 636 if (ret) 637 return ret; 638 639 gc->bgpio_data = gc->read_reg(gc->reg_dat); 640 if (gc->set == bgpio_set_set && 641 !(flags & BGPIOF_UNREADABLE_REG_SET)) 642 gc->bgpio_data = gc->read_reg(gc->reg_set); 643 644 if (flags & BGPIOF_UNREADABLE_REG_DIR) 645 gc->bgpio_dir_unreadable = true; 646 647 /* 648 * Inspect hardware to find initial direction setting. 649 */ 650 if ((gc->reg_dir_out || gc->reg_dir_in) && 651 !(flags & BGPIOF_UNREADABLE_REG_DIR)) { 652 if (gc->reg_dir_out) 653 gc->bgpio_dir = gc->read_reg(gc->reg_dir_out); 654 else if (gc->reg_dir_in) 655 gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in); 656 /* 657 * If we have two direction registers, synchronise 658 * input setting to output setting, the library 659 * can not handle a line being input and output at 660 * the same time. 661 */ 662 if (gc->reg_dir_out && gc->reg_dir_in) 663 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 664 } 665 666 return ret; 667 } 668 EXPORT_SYMBOL_GPL(bgpio_init); 669 670 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) 671 672 static void __iomem *bgpio_map(struct platform_device *pdev, 673 const char *name, 674 resource_size_t sane_sz) 675 { 676 struct resource *r; 677 resource_size_t sz; 678 679 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 680 if (!r) 681 return NULL; 682 683 sz = resource_size(r); 684 if (sz != sane_sz) 685 return IOMEM_ERR_PTR(-EINVAL); 686 687 return devm_ioremap_resource(&pdev->dev, r); 688 } 689 690 #ifdef CONFIG_OF 691 static const struct of_device_id bgpio_of_match[] = { 692 { .compatible = "brcm,bcm6345-gpio" }, 693 { .compatible = "wd,mbl-gpio" }, 694 { .compatible = "ni,169445-nand-gpio" }, 695 { } 696 }; 697 MODULE_DEVICE_TABLE(of, bgpio_of_match); 698 699 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, 700 unsigned long *flags) 701 { 702 struct bgpio_pdata *pdata; 703 704 if (!of_match_device(bgpio_of_match, &pdev->dev)) 705 return NULL; 706 707 pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata), 708 GFP_KERNEL); 709 if (!pdata) 710 return ERR_PTR(-ENOMEM); 711 712 pdata->base = -1; 713 714 if (of_device_is_big_endian(pdev->dev.of_node)) 715 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER; 716 717 if (of_property_read_bool(pdev->dev.of_node, "no-output")) 718 *flags |= BGPIOF_NO_OUTPUT; 719 720 return pdata; 721 } 722 #else 723 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, 724 unsigned long *flags) 725 { 726 return NULL; 727 } 728 #endif /* CONFIG_OF */ 729 730 static int bgpio_pdev_probe(struct platform_device *pdev) 731 { 732 struct device *dev = &pdev->dev; 733 struct resource *r; 734 void __iomem *dat; 735 void __iomem *set; 736 void __iomem *clr; 737 void __iomem *dirout; 738 void __iomem *dirin; 739 unsigned long sz; 740 unsigned long flags = 0; 741 int err; 742 struct gpio_chip *gc; 743 struct bgpio_pdata *pdata; 744 745 pdata = bgpio_parse_dt(pdev, &flags); 746 if (IS_ERR(pdata)) 747 return PTR_ERR(pdata); 748 749 if (!pdata) { 750 pdata = dev_get_platdata(dev); 751 flags = pdev->id_entry->driver_data; 752 } 753 754 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 755 if (!r) 756 return -EINVAL; 757 758 sz = resource_size(r); 759 760 dat = bgpio_map(pdev, "dat", sz); 761 if (IS_ERR(dat)) 762 return PTR_ERR(dat); 763 764 set = bgpio_map(pdev, "set", sz); 765 if (IS_ERR(set)) 766 return PTR_ERR(set); 767 768 clr = bgpio_map(pdev, "clr", sz); 769 if (IS_ERR(clr)) 770 return PTR_ERR(clr); 771 772 dirout = bgpio_map(pdev, "dirout", sz); 773 if (IS_ERR(dirout)) 774 return PTR_ERR(dirout); 775 776 dirin = bgpio_map(pdev, "dirin", sz); 777 if (IS_ERR(dirin)) 778 return PTR_ERR(dirin); 779 780 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); 781 if (!gc) 782 return -ENOMEM; 783 784 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); 785 if (err) 786 return err; 787 788 if (pdata) { 789 if (pdata->label) 790 gc->label = pdata->label; 791 gc->base = pdata->base; 792 if (pdata->ngpio > 0) 793 gc->ngpio = pdata->ngpio; 794 } 795 796 platform_set_drvdata(pdev, gc); 797 798 return devm_gpiochip_add_data(&pdev->dev, gc, NULL); 799 } 800 801 static const struct platform_device_id bgpio_id_table[] = { 802 { 803 .name = "basic-mmio-gpio", 804 .driver_data = 0, 805 }, { 806 .name = "basic-mmio-gpio-be", 807 .driver_data = BGPIOF_BIG_ENDIAN, 808 }, 809 { } 810 }; 811 MODULE_DEVICE_TABLE(platform, bgpio_id_table); 812 813 static struct platform_driver bgpio_driver = { 814 .driver = { 815 .name = "basic-mmio-gpio", 816 .of_match_table = of_match_ptr(bgpio_of_match), 817 }, 818 .id_table = bgpio_id_table, 819 .probe = bgpio_pdev_probe, 820 }; 821 822 module_platform_driver(bgpio_driver); 823 824 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ 825 826 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); 827 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); 828 MODULE_LICENSE("GPL"); 829