1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Merrifield SoC GPIO driver 4 * 5 * Copyright (c) 2016, 2023 Intel Corporation. 6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/types.h> 17 18 #include "gpio-tangier.h" 19 20 /* Intel Merrifield has 192 GPIO pins */ 21 #define MRFLD_NGPIO 192 22 23 static const struct tng_gpio_pinrange mrfld_gpio_ranges[] = { 24 GPIO_PINRANGE(0, 11, 146), 25 GPIO_PINRANGE(12, 13, 144), 26 GPIO_PINRANGE(14, 15, 35), 27 GPIO_PINRANGE(16, 16, 164), 28 GPIO_PINRANGE(17, 18, 105), 29 GPIO_PINRANGE(19, 22, 101), 30 GPIO_PINRANGE(23, 30, 107), 31 GPIO_PINRANGE(32, 43, 67), 32 GPIO_PINRANGE(44, 63, 195), 33 GPIO_PINRANGE(64, 67, 140), 34 GPIO_PINRANGE(68, 69, 165), 35 GPIO_PINRANGE(70, 71, 65), 36 GPIO_PINRANGE(72, 76, 228), 37 GPIO_PINRANGE(77, 86, 37), 38 GPIO_PINRANGE(87, 87, 48), 39 GPIO_PINRANGE(88, 88, 47), 40 GPIO_PINRANGE(89, 96, 49), 41 GPIO_PINRANGE(97, 97, 34), 42 GPIO_PINRANGE(102, 119, 83), 43 GPIO_PINRANGE(120, 123, 79), 44 GPIO_PINRANGE(124, 135, 115), 45 GPIO_PINRANGE(137, 142, 158), 46 GPIO_PINRANGE(154, 163, 24), 47 GPIO_PINRANGE(164, 176, 215), 48 GPIO_PINRANGE(177, 189, 127), 49 GPIO_PINRANGE(190, 191, 178), 50 }; 51 52 static const char *mrfld_gpio_get_pinctrl_dev_name(struct tng_gpio *priv) 53 { 54 struct acpi_device *adev; 55 const char *name; 56 57 adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1); 58 if (adev) { 59 name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL); 60 acpi_dev_put(adev); 61 } else { 62 name = "pinctrl-merrifield"; 63 } 64 65 return name; 66 } 67 68 static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id) 69 { 70 struct device *dev = &pdev->dev; 71 struct tng_gpio *priv; 72 u32 gpio_base, irq_base; 73 void __iomem *base; 74 int retval; 75 76 retval = pcim_enable_device(pdev); 77 if (retval) 78 return retval; 79 80 retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev)); 81 if (retval) 82 return dev_err_probe(dev, retval, "I/O memory mapping error\n"); 83 84 base = pcim_iomap_table(pdev)[1]; 85 86 irq_base = readl(base + 0 * sizeof(u32)); 87 gpio_base = readl(base + 1 * sizeof(u32)); 88 89 /* Release the IO mapping, since we already get the info from BAR1 */ 90 pcim_iounmap_regions(pdev, BIT(1)); 91 92 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 93 if (!priv) 94 return -ENOMEM; 95 96 priv->dev = &pdev->dev; 97 priv->reg_base = pcim_iomap_table(pdev)[0]; 98 99 priv->pin_info.pin_ranges = mrfld_gpio_ranges; 100 priv->pin_info.nranges = ARRAY_SIZE(mrfld_gpio_ranges); 101 priv->pin_info.name = mrfld_gpio_get_pinctrl_dev_name(priv); 102 if (!priv->pin_info.name) 103 return -ENOMEM; 104 105 priv->info.base = gpio_base; 106 priv->info.ngpio = MRFLD_NGPIO; 107 priv->info.first = irq_base; 108 109 retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 110 if (retval < 0) 111 return retval; 112 113 priv->irq = pci_irq_vector(pdev, 0); 114 115 priv->wake_regs.gwmr = GWMR_MRFLD; 116 priv->wake_regs.gwsr = GWSR_MRFLD; 117 priv->wake_regs.gsir = GSIR_MRFLD; 118 119 retval = devm_tng_gpio_probe(dev, priv); 120 if (retval) 121 return dev_err_probe(dev, retval, "tng_gpio_probe error\n"); 122 123 pci_set_drvdata(pdev, priv); 124 return 0; 125 } 126 127 static const struct pci_device_id mrfld_gpio_ids[] = { 128 { PCI_VDEVICE(INTEL, 0x1199) }, 129 { } 130 }; 131 MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids); 132 133 static struct pci_driver mrfld_gpio_driver = { 134 .name = "gpio-merrifield", 135 .id_table = mrfld_gpio_ids, 136 .probe = mrfld_gpio_probe, 137 }; 138 module_pci_driver(mrfld_gpio_driver); 139 140 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 141 MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver"); 142 MODULE_LICENSE("GPL v2"); 143 MODULE_IMPORT_NS(GPIO_TANGIER); 144