1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Merrifield SoC GPIO driver 4 * 5 * Copyright (c) 2016 Intel Corporation. 6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/pinctrl/consumer.h> 17 18 #define GCCR 0x000 /* controller configuration */ 19 #define GPLR 0x004 /* pin level r/o */ 20 #define GPDR 0x01c /* pin direction */ 21 #define GPSR 0x034 /* pin set w/o */ 22 #define GPCR 0x04c /* pin clear w/o */ 23 #define GRER 0x064 /* rising edge detect */ 24 #define GFER 0x07c /* falling edge detect */ 25 #define GFBR 0x094 /* glitch filter bypass */ 26 #define GIMR 0x0ac /* interrupt mask */ 27 #define GISR 0x0c4 /* interrupt source */ 28 #define GITR 0x300 /* input type */ 29 #define GLPR 0x318 /* level input polarity */ 30 #define GWMR 0x400 /* wake mask */ 31 #define GWSR 0x418 /* wake source */ 32 #define GSIR 0xc00 /* secure input */ 33 34 /* Intel Merrifield has 192 GPIO pins */ 35 #define MRFLD_NGPIO 192 36 37 struct mrfld_gpio_pinrange { 38 unsigned int gpio_base; 39 unsigned int pin_base; 40 unsigned int npins; 41 }; 42 43 #define GPIO_PINRANGE(gstart, gend, pstart) \ 44 { \ 45 .gpio_base = (gstart), \ 46 .pin_base = (pstart), \ 47 .npins = (gend) - (gstart) + 1, \ 48 } 49 50 struct mrfld_gpio { 51 struct gpio_chip chip; 52 void __iomem *reg_base; 53 raw_spinlock_t lock; 54 struct device *dev; 55 }; 56 57 static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = { 58 GPIO_PINRANGE(0, 11, 146), 59 GPIO_PINRANGE(12, 13, 144), 60 GPIO_PINRANGE(14, 15, 35), 61 GPIO_PINRANGE(16, 16, 164), 62 GPIO_PINRANGE(17, 18, 105), 63 GPIO_PINRANGE(19, 22, 101), 64 GPIO_PINRANGE(23, 30, 107), 65 GPIO_PINRANGE(32, 43, 67), 66 GPIO_PINRANGE(44, 63, 195), 67 GPIO_PINRANGE(64, 67, 140), 68 GPIO_PINRANGE(68, 69, 165), 69 GPIO_PINRANGE(70, 71, 65), 70 GPIO_PINRANGE(72, 76, 228), 71 GPIO_PINRANGE(77, 86, 37), 72 GPIO_PINRANGE(87, 87, 48), 73 GPIO_PINRANGE(88, 88, 47), 74 GPIO_PINRANGE(89, 96, 49), 75 GPIO_PINRANGE(97, 97, 34), 76 GPIO_PINRANGE(102, 119, 83), 77 GPIO_PINRANGE(120, 123, 79), 78 GPIO_PINRANGE(124, 135, 115), 79 GPIO_PINRANGE(137, 142, 158), 80 GPIO_PINRANGE(154, 163, 24), 81 GPIO_PINRANGE(164, 176, 215), 82 GPIO_PINRANGE(177, 189, 127), 83 GPIO_PINRANGE(190, 191, 178), 84 }; 85 86 static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset, 87 unsigned int reg_type_offset) 88 { 89 struct mrfld_gpio *priv = gpiochip_get_data(chip); 90 u8 reg = offset / 32; 91 92 return priv->reg_base + reg_type_offset + reg * 4; 93 } 94 95 static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset) 96 { 97 void __iomem *gplr = gpio_reg(chip, offset, GPLR); 98 99 return !!(readl(gplr) & BIT(offset % 32)); 100 } 101 102 static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset, 103 int value) 104 { 105 struct mrfld_gpio *priv = gpiochip_get_data(chip); 106 void __iomem *gpsr, *gpcr; 107 unsigned long flags; 108 109 raw_spin_lock_irqsave(&priv->lock, flags); 110 111 if (value) { 112 gpsr = gpio_reg(chip, offset, GPSR); 113 writel(BIT(offset % 32), gpsr); 114 } else { 115 gpcr = gpio_reg(chip, offset, GPCR); 116 writel(BIT(offset % 32), gpcr); 117 } 118 119 raw_spin_unlock_irqrestore(&priv->lock, flags); 120 } 121 122 static int mrfld_gpio_direction_input(struct gpio_chip *chip, 123 unsigned int offset) 124 { 125 struct mrfld_gpio *priv = gpiochip_get_data(chip); 126 void __iomem *gpdr = gpio_reg(chip, offset, GPDR); 127 unsigned long flags; 128 u32 value; 129 130 raw_spin_lock_irqsave(&priv->lock, flags); 131 132 value = readl(gpdr); 133 value &= ~BIT(offset % 32); 134 writel(value, gpdr); 135 136 raw_spin_unlock_irqrestore(&priv->lock, flags); 137 138 return 0; 139 } 140 141 static int mrfld_gpio_direction_output(struct gpio_chip *chip, 142 unsigned int offset, int value) 143 { 144 struct mrfld_gpio *priv = gpiochip_get_data(chip); 145 void __iomem *gpdr = gpio_reg(chip, offset, GPDR); 146 unsigned long flags; 147 148 mrfld_gpio_set(chip, offset, value); 149 150 raw_spin_lock_irqsave(&priv->lock, flags); 151 152 value = readl(gpdr); 153 value |= BIT(offset % 32); 154 writel(value, gpdr); 155 156 raw_spin_unlock_irqrestore(&priv->lock, flags); 157 158 return 0; 159 } 160 161 static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 162 { 163 void __iomem *gpdr = gpio_reg(chip, offset, GPDR); 164 165 if (readl(gpdr) & BIT(offset % 32)) 166 return GPIO_LINE_DIRECTION_OUT; 167 168 return GPIO_LINE_DIRECTION_IN; 169 } 170 171 static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, 172 unsigned int debounce) 173 { 174 struct mrfld_gpio *priv = gpiochip_get_data(chip); 175 void __iomem *gfbr = gpio_reg(chip, offset, GFBR); 176 unsigned long flags; 177 u32 value; 178 179 raw_spin_lock_irqsave(&priv->lock, flags); 180 181 if (debounce) 182 value = readl(gfbr) & ~BIT(offset % 32); 183 else 184 value = readl(gfbr) | BIT(offset % 32); 185 writel(value, gfbr); 186 187 raw_spin_unlock_irqrestore(&priv->lock, flags); 188 189 return 0; 190 } 191 192 static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 193 unsigned long config) 194 { 195 u32 debounce; 196 197 if ((pinconf_to_config_param(config) == PIN_CONFIG_BIAS_DISABLE) || 198 (pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_UP) || 199 (pinconf_to_config_param(config) == PIN_CONFIG_BIAS_PULL_DOWN)) 200 return gpiochip_generic_config(chip, offset, config); 201 202 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 203 return -ENOTSUPP; 204 205 debounce = pinconf_to_config_argument(config); 206 return mrfld_gpio_set_debounce(chip, offset, debounce); 207 } 208 209 static void mrfld_irq_ack(struct irq_data *d) 210 { 211 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); 212 u32 gpio = irqd_to_hwirq(d); 213 void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR); 214 unsigned long flags; 215 216 raw_spin_lock_irqsave(&priv->lock, flags); 217 218 writel(BIT(gpio % 32), gisr); 219 220 raw_spin_unlock_irqrestore(&priv->lock, flags); 221 } 222 223 static void mrfld_irq_unmask_mask(struct mrfld_gpio *priv, u32 gpio, bool unmask) 224 { 225 void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR); 226 unsigned long flags; 227 u32 value; 228 229 raw_spin_lock_irqsave(&priv->lock, flags); 230 231 if (unmask) 232 value = readl(gimr) | BIT(gpio % 32); 233 else 234 value = readl(gimr) & ~BIT(gpio % 32); 235 writel(value, gimr); 236 237 raw_spin_unlock_irqrestore(&priv->lock, flags); 238 } 239 240 static void mrfld_irq_mask(struct irq_data *d) 241 { 242 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); 243 u32 gpio = irqd_to_hwirq(d); 244 245 mrfld_irq_unmask_mask(priv, gpio, false); 246 gpiochip_disable_irq(&priv->chip, gpio); 247 } 248 249 static void mrfld_irq_unmask(struct irq_data *d) 250 { 251 struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); 252 u32 gpio = irqd_to_hwirq(d); 253 254 gpiochip_enable_irq(&priv->chip, gpio); 255 mrfld_irq_unmask_mask(priv, gpio, true); 256 } 257 258 static int mrfld_irq_set_type(struct irq_data *d, unsigned int type) 259 { 260 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 261 struct mrfld_gpio *priv = gpiochip_get_data(gc); 262 u32 gpio = irqd_to_hwirq(d); 263 void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); 264 void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); 265 void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); 266 void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); 267 unsigned long flags; 268 u32 value; 269 270 raw_spin_lock_irqsave(&priv->lock, flags); 271 272 if (type & IRQ_TYPE_EDGE_RISING) 273 value = readl(grer) | BIT(gpio % 32); 274 else 275 value = readl(grer) & ~BIT(gpio % 32); 276 writel(value, grer); 277 278 if (type & IRQ_TYPE_EDGE_FALLING) 279 value = readl(gfer) | BIT(gpio % 32); 280 else 281 value = readl(gfer) & ~BIT(gpio % 32); 282 writel(value, gfer); 283 284 /* 285 * To prevent glitches from triggering an unintended level interrupt, 286 * configure GLPR register first and then configure GITR. 287 */ 288 if (type & IRQ_TYPE_LEVEL_LOW) 289 value = readl(glpr) | BIT(gpio % 32); 290 else 291 value = readl(glpr) & ~BIT(gpio % 32); 292 writel(value, glpr); 293 294 if (type & IRQ_TYPE_LEVEL_MASK) { 295 value = readl(gitr) | BIT(gpio % 32); 296 writel(value, gitr); 297 298 irq_set_handler_locked(d, handle_level_irq); 299 } else if (type & IRQ_TYPE_EDGE_BOTH) { 300 value = readl(gitr) & ~BIT(gpio % 32); 301 writel(value, gitr); 302 303 irq_set_handler_locked(d, handle_edge_irq); 304 } 305 306 raw_spin_unlock_irqrestore(&priv->lock, flags); 307 308 return 0; 309 } 310 311 static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on) 312 { 313 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 314 struct mrfld_gpio *priv = gpiochip_get_data(gc); 315 u32 gpio = irqd_to_hwirq(d); 316 void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR); 317 void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR); 318 unsigned long flags; 319 u32 value; 320 321 raw_spin_lock_irqsave(&priv->lock, flags); 322 323 /* Clear the existing wake status */ 324 writel(BIT(gpio % 32), gwsr); 325 326 if (on) 327 value = readl(gwmr) | BIT(gpio % 32); 328 else 329 value = readl(gwmr) & ~BIT(gpio % 32); 330 writel(value, gwmr); 331 332 raw_spin_unlock_irqrestore(&priv->lock, flags); 333 334 dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio); 335 return 0; 336 } 337 338 static const struct irq_chip mrfld_irqchip = { 339 .name = "gpio-merrifield", 340 .irq_ack = mrfld_irq_ack, 341 .irq_mask = mrfld_irq_mask, 342 .irq_unmask = mrfld_irq_unmask, 343 .irq_set_type = mrfld_irq_set_type, 344 .irq_set_wake = mrfld_irq_set_wake, 345 .flags = IRQCHIP_IMMUTABLE, 346 GPIOCHIP_IRQ_RESOURCE_HELPERS, 347 }; 348 349 static void mrfld_irq_handler(struct irq_desc *desc) 350 { 351 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 352 struct mrfld_gpio *priv = gpiochip_get_data(gc); 353 struct irq_chip *irqchip = irq_desc_get_chip(desc); 354 unsigned long base, gpio; 355 356 chained_irq_enter(irqchip, desc); 357 358 /* Check GPIO controller to check which pin triggered the interrupt */ 359 for (base = 0; base < priv->chip.ngpio; base += 32) { 360 void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); 361 void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); 362 unsigned long pending, enabled; 363 364 pending = readl(gisr); 365 enabled = readl(gimr); 366 367 /* Only interrupts that are enabled */ 368 pending &= enabled; 369 370 for_each_set_bit(gpio, &pending, 32) 371 generic_handle_domain_irq(gc->irq.domain, base + gpio); 372 } 373 374 chained_irq_exit(irqchip, desc); 375 } 376 377 static int mrfld_irq_init_hw(struct gpio_chip *chip) 378 { 379 struct mrfld_gpio *priv = gpiochip_get_data(chip); 380 void __iomem *reg; 381 unsigned int base; 382 383 for (base = 0; base < priv->chip.ngpio; base += 32) { 384 /* Clear the rising-edge detect register */ 385 reg = gpio_reg(&priv->chip, base, GRER); 386 writel(0, reg); 387 /* Clear the falling-edge detect register */ 388 reg = gpio_reg(&priv->chip, base, GFER); 389 writel(0, reg); 390 } 391 392 return 0; 393 } 394 395 static const char *mrfld_gpio_get_pinctrl_dev_name(struct mrfld_gpio *priv) 396 { 397 struct acpi_device *adev; 398 const char *name; 399 400 adev = acpi_dev_get_first_match_dev("INTC1002", NULL, -1); 401 if (adev) { 402 name = devm_kstrdup(priv->dev, acpi_dev_name(adev), GFP_KERNEL); 403 acpi_dev_put(adev); 404 } else { 405 name = "pinctrl-merrifield"; 406 } 407 408 return name; 409 } 410 411 static int mrfld_gpio_add_pin_ranges(struct gpio_chip *chip) 412 { 413 struct mrfld_gpio *priv = gpiochip_get_data(chip); 414 const struct mrfld_gpio_pinrange *range; 415 const char *pinctrl_dev_name; 416 unsigned int i; 417 int retval; 418 419 pinctrl_dev_name = mrfld_gpio_get_pinctrl_dev_name(priv); 420 if (!pinctrl_dev_name) 421 return -ENOMEM; 422 423 for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) { 424 range = &mrfld_gpio_ranges[i]; 425 retval = gpiochip_add_pin_range(&priv->chip, pinctrl_dev_name, 426 range->gpio_base, 427 range->pin_base, 428 range->npins); 429 if (retval) { 430 dev_err(priv->dev, "failed to add GPIO pin range\n"); 431 return retval; 432 } 433 } 434 435 return 0; 436 } 437 438 static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id) 439 { 440 struct gpio_irq_chip *girq; 441 struct mrfld_gpio *priv; 442 u32 gpio_base, irq_base; 443 void __iomem *base; 444 int retval; 445 446 retval = pcim_enable_device(pdev); 447 if (retval) 448 return retval; 449 450 retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev)); 451 if (retval) { 452 dev_err(&pdev->dev, "I/O memory mapping error\n"); 453 return retval; 454 } 455 456 base = pcim_iomap_table(pdev)[1]; 457 458 irq_base = readl(base + 0 * sizeof(u32)); 459 gpio_base = readl(base + 1 * sizeof(u32)); 460 461 /* Release the IO mapping, since we already get the info from BAR1 */ 462 pcim_iounmap_regions(pdev, BIT(1)); 463 464 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 465 if (!priv) 466 return -ENOMEM; 467 468 priv->dev = &pdev->dev; 469 priv->reg_base = pcim_iomap_table(pdev)[0]; 470 471 priv->chip.label = dev_name(&pdev->dev); 472 priv->chip.parent = &pdev->dev; 473 priv->chip.request = gpiochip_generic_request; 474 priv->chip.free = gpiochip_generic_free; 475 priv->chip.direction_input = mrfld_gpio_direction_input; 476 priv->chip.direction_output = mrfld_gpio_direction_output; 477 priv->chip.get = mrfld_gpio_get; 478 priv->chip.set = mrfld_gpio_set; 479 priv->chip.get_direction = mrfld_gpio_get_direction; 480 priv->chip.set_config = mrfld_gpio_set_config; 481 priv->chip.base = gpio_base; 482 priv->chip.ngpio = MRFLD_NGPIO; 483 priv->chip.can_sleep = false; 484 priv->chip.add_pin_ranges = mrfld_gpio_add_pin_ranges; 485 486 raw_spin_lock_init(&priv->lock); 487 488 retval = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 489 if (retval < 0) 490 return retval; 491 492 girq = &priv->chip.irq; 493 gpio_irq_chip_set_chip(girq, &mrfld_irqchip); 494 girq->init_hw = mrfld_irq_init_hw; 495 girq->parent_handler = mrfld_irq_handler; 496 girq->num_parents = 1; 497 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, 498 sizeof(*girq->parents), GFP_KERNEL); 499 if (!girq->parents) 500 return -ENOMEM; 501 girq->parents[0] = pci_irq_vector(pdev, 0); 502 girq->first = irq_base; 503 girq->default_type = IRQ_TYPE_NONE; 504 girq->handler = handle_bad_irq; 505 506 retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); 507 if (retval) { 508 dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); 509 return retval; 510 } 511 512 pci_set_drvdata(pdev, priv); 513 return 0; 514 } 515 516 static const struct pci_device_id mrfld_gpio_ids[] = { 517 { PCI_VDEVICE(INTEL, 0x1199) }, 518 { } 519 }; 520 MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids); 521 522 static struct pci_driver mrfld_gpio_driver = { 523 .name = "gpio-merrifield", 524 .id_table = mrfld_gpio_ids, 525 .probe = mrfld_gpio_probe, 526 }; 527 528 module_pci_driver(mrfld_gpio_driver); 529 530 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 531 MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver"); 532 MODULE_LICENSE("GPL v2"); 533