10da094d8SJassi Brar /* 20da094d8SJassi Brar * linux/drivers/gpio/gpio-mb86s7x.c 30da094d8SJassi Brar * 40da094d8SJassi Brar * Copyright (C) 2015 Fujitsu Semiconductor Limited 50da094d8SJassi Brar * Copyright (C) 2015 Linaro Ltd. 60da094d8SJassi Brar * 70da094d8SJassi Brar * This program is free software: you can redistribute it and/or modify 80da094d8SJassi Brar * it under the terms of the GNU General Public License as published by 90da094d8SJassi Brar * the Free Software Foundation, version 2 of the License. 100da094d8SJassi Brar * 110da094d8SJassi Brar * This program is distributed in the hope that it will be useful, 120da094d8SJassi Brar * but WITHOUT ANY WARRANTY; without even the implied warranty of 130da094d8SJassi Brar * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 140da094d8SJassi Brar * GNU General Public License for more details. 150da094d8SJassi Brar */ 160da094d8SJassi Brar 17f3d705d5SArd Biesheuvel #include <linux/acpi.h> 180da094d8SJassi Brar #include <linux/io.h> 190da094d8SJassi Brar #include <linux/init.h> 200da094d8SJassi Brar #include <linux/clk.h> 21e1289dbaSArd Biesheuvel #include <linux/module.h> 220da094d8SJassi Brar #include <linux/err.h> 230da094d8SJassi Brar #include <linux/errno.h> 240da094d8SJassi Brar #include <linux/ioport.h> 250da094d8SJassi Brar #include <linux/of_device.h> 260da094d8SJassi Brar #include <linux/gpio/driver.h> 270da094d8SJassi Brar #include <linux/platform_device.h> 280da094d8SJassi Brar #include <linux/spinlock.h> 290da094d8SJassi Brar #include <linux/slab.h> 300da094d8SJassi Brar 31f3d705d5SArd Biesheuvel #include "gpiolib.h" 32f3d705d5SArd Biesheuvel 330da094d8SJassi Brar /* 340da094d8SJassi Brar * Only first 8bits of a register correspond to each pin, 350da094d8SJassi Brar * so there are 4 registers for 32 pins. 360da094d8SJassi Brar */ 370da094d8SJassi Brar #define PDR(x) (0x0 + x / 8 * 4) 380da094d8SJassi Brar #define DDR(x) (0x10 + x / 8 * 4) 390da094d8SJassi Brar #define PFR(x) (0x20 + x / 8 * 4) 400da094d8SJassi Brar 410da094d8SJassi Brar #define OFFSET(x) BIT((x) % 8) 420da094d8SJassi Brar 430da094d8SJassi Brar struct mb86s70_gpio_chip { 440da094d8SJassi Brar struct gpio_chip gc; 450da094d8SJassi Brar void __iomem *base; 460da094d8SJassi Brar struct clk *clk; 470da094d8SJassi Brar spinlock_t lock; 480da094d8SJassi Brar }; 490da094d8SJassi Brar 500da094d8SJassi Brar static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio) 510da094d8SJassi Brar { 5201f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 530da094d8SJassi Brar unsigned long flags; 540da094d8SJassi Brar u32 val; 550da094d8SJassi Brar 560da094d8SJassi Brar spin_lock_irqsave(&gchip->lock, flags); 570da094d8SJassi Brar 580da094d8SJassi Brar val = readl(gchip->base + PFR(gpio)); 590da094d8SJassi Brar val &= ~OFFSET(gpio); 600da094d8SJassi Brar writel(val, gchip->base + PFR(gpio)); 610da094d8SJassi Brar 620da094d8SJassi Brar spin_unlock_irqrestore(&gchip->lock, flags); 630da094d8SJassi Brar 640da094d8SJassi Brar return 0; 650da094d8SJassi Brar } 660da094d8SJassi Brar 670da094d8SJassi Brar static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio) 680da094d8SJassi Brar { 6901f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 700da094d8SJassi Brar unsigned long flags; 710da094d8SJassi Brar u32 val; 720da094d8SJassi Brar 730da094d8SJassi Brar spin_lock_irqsave(&gchip->lock, flags); 740da094d8SJassi Brar 750da094d8SJassi Brar val = readl(gchip->base + PFR(gpio)); 760da094d8SJassi Brar val |= OFFSET(gpio); 770da094d8SJassi Brar writel(val, gchip->base + PFR(gpio)); 780da094d8SJassi Brar 790da094d8SJassi Brar spin_unlock_irqrestore(&gchip->lock, flags); 800da094d8SJassi Brar } 810da094d8SJassi Brar 820da094d8SJassi Brar static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) 830da094d8SJassi Brar { 8401f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 850da094d8SJassi Brar unsigned long flags; 860da094d8SJassi Brar unsigned char val; 870da094d8SJassi Brar 880da094d8SJassi Brar spin_lock_irqsave(&gchip->lock, flags); 890da094d8SJassi Brar 900da094d8SJassi Brar val = readl(gchip->base + DDR(gpio)); 910da094d8SJassi Brar val &= ~OFFSET(gpio); 920da094d8SJassi Brar writel(val, gchip->base + DDR(gpio)); 930da094d8SJassi Brar 940da094d8SJassi Brar spin_unlock_irqrestore(&gchip->lock, flags); 950da094d8SJassi Brar 960da094d8SJassi Brar return 0; 970da094d8SJassi Brar } 980da094d8SJassi Brar 990da094d8SJassi Brar static int mb86s70_gpio_direction_output(struct gpio_chip *gc, 1000da094d8SJassi Brar unsigned gpio, int value) 1010da094d8SJassi Brar { 10201f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 1030da094d8SJassi Brar unsigned long flags; 1040da094d8SJassi Brar unsigned char val; 1050da094d8SJassi Brar 1060da094d8SJassi Brar spin_lock_irqsave(&gchip->lock, flags); 1070da094d8SJassi Brar 1080da094d8SJassi Brar val = readl(gchip->base + PDR(gpio)); 1090da094d8SJassi Brar if (value) 1100da094d8SJassi Brar val |= OFFSET(gpio); 1110da094d8SJassi Brar else 1120da094d8SJassi Brar val &= ~OFFSET(gpio); 1130da094d8SJassi Brar writel(val, gchip->base + PDR(gpio)); 1140da094d8SJassi Brar 1150da094d8SJassi Brar val = readl(gchip->base + DDR(gpio)); 1160da094d8SJassi Brar val |= OFFSET(gpio); 1170da094d8SJassi Brar writel(val, gchip->base + DDR(gpio)); 1180da094d8SJassi Brar 1190da094d8SJassi Brar spin_unlock_irqrestore(&gchip->lock, flags); 1200da094d8SJassi Brar 1210da094d8SJassi Brar return 0; 1220da094d8SJassi Brar } 1230da094d8SJassi Brar 1240da094d8SJassi Brar static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio) 1250da094d8SJassi Brar { 12601f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 1270da094d8SJassi Brar 1280da094d8SJassi Brar return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio)); 1290da094d8SJassi Brar } 1300da094d8SJassi Brar 1310da094d8SJassi Brar static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value) 1320da094d8SJassi Brar { 13301f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 1340da094d8SJassi Brar unsigned long flags; 1350da094d8SJassi Brar unsigned char val; 1360da094d8SJassi Brar 1370da094d8SJassi Brar spin_lock_irqsave(&gchip->lock, flags); 1380da094d8SJassi Brar 1390da094d8SJassi Brar val = readl(gchip->base + PDR(gpio)); 1400da094d8SJassi Brar if (value) 1410da094d8SJassi Brar val |= OFFSET(gpio); 1420da094d8SJassi Brar else 1430da094d8SJassi Brar val &= ~OFFSET(gpio); 1440da094d8SJassi Brar writel(val, gchip->base + PDR(gpio)); 1450da094d8SJassi Brar 1460da094d8SJassi Brar spin_unlock_irqrestore(&gchip->lock, flags); 1470da094d8SJassi Brar } 1480da094d8SJassi Brar 149f3d705d5SArd Biesheuvel static int mb86s70_gpio_to_irq(struct gpio_chip *gc, unsigned int offset) 150f3d705d5SArd Biesheuvel { 151f3d705d5SArd Biesheuvel int irq, index; 152f3d705d5SArd Biesheuvel 153f3d705d5SArd Biesheuvel for (index = 0;; index++) { 154f3d705d5SArd Biesheuvel irq = platform_get_irq(to_platform_device(gc->parent), index); 155f3d705d5SArd Biesheuvel if (irq <= 0) 156f3d705d5SArd Biesheuvel break; 157f3d705d5SArd Biesheuvel if (irq_get_irq_data(irq)->hwirq == offset) 158f3d705d5SArd Biesheuvel return irq; 159f3d705d5SArd Biesheuvel } 160f3d705d5SArd Biesheuvel return -EINVAL; 161f3d705d5SArd Biesheuvel } 162f3d705d5SArd Biesheuvel 1630da094d8SJassi Brar static int mb86s70_gpio_probe(struct platform_device *pdev) 1640da094d8SJassi Brar { 1650da094d8SJassi Brar struct mb86s70_gpio_chip *gchip; 1660da094d8SJassi Brar int ret; 1670da094d8SJassi Brar 1680da094d8SJassi Brar gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL); 1690da094d8SJassi Brar if (gchip == NULL) 1700da094d8SJassi Brar return -ENOMEM; 1710da094d8SJassi Brar 1720da094d8SJassi Brar platform_set_drvdata(pdev, gchip); 1730da094d8SJassi Brar 174329e23f9SEnrico Weigelt, metux IT consult gchip->base = devm_platform_ioremap_resource(pdev, 0); 1750da094d8SJassi Brar if (IS_ERR(gchip->base)) 1760da094d8SJassi Brar return PTR_ERR(gchip->base); 1770da094d8SJassi Brar 178f3d705d5SArd Biesheuvel if (!has_acpi_companion(&pdev->dev)) { 1790da094d8SJassi Brar gchip->clk = devm_clk_get(&pdev->dev, NULL); 1800da094d8SJassi Brar if (IS_ERR(gchip->clk)) 1810da094d8SJassi Brar return PTR_ERR(gchip->clk); 1820da094d8SJassi Brar 183d829b37aSArvind Yadav ret = clk_prepare_enable(gchip->clk); 184d829b37aSArvind Yadav if (ret) 185d829b37aSArvind Yadav return ret; 186f3d705d5SArd Biesheuvel } 1870da094d8SJassi Brar 1880da094d8SJassi Brar spin_lock_init(&gchip->lock); 1890da094d8SJassi Brar 1900da094d8SJassi Brar gchip->gc.direction_output = mb86s70_gpio_direction_output; 1910da094d8SJassi Brar gchip->gc.direction_input = mb86s70_gpio_direction_input; 1920da094d8SJassi Brar gchip->gc.request = mb86s70_gpio_request; 1930da094d8SJassi Brar gchip->gc.free = mb86s70_gpio_free; 1940da094d8SJassi Brar gchip->gc.get = mb86s70_gpio_get; 1950da094d8SJassi Brar gchip->gc.set = mb86s70_gpio_set; 1960da094d8SJassi Brar gchip->gc.label = dev_name(&pdev->dev); 1970da094d8SJassi Brar gchip->gc.ngpio = 32; 1980da094d8SJassi Brar gchip->gc.owner = THIS_MODULE; 19958383c78SLinus Walleij gchip->gc.parent = &pdev->dev; 2000da094d8SJassi Brar gchip->gc.base = -1; 2010da094d8SJassi Brar 202f3d705d5SArd Biesheuvel if (has_acpi_companion(&pdev->dev)) 203f3d705d5SArd Biesheuvel gchip->gc.to_irq = mb86s70_gpio_to_irq; 204f3d705d5SArd Biesheuvel 20501f76b26SLinus Walleij ret = gpiochip_add_data(&gchip->gc, gchip); 2060da094d8SJassi Brar if (ret) { 2070da094d8SJassi Brar dev_err(&pdev->dev, "couldn't register gpio driver\n"); 2080da094d8SJassi Brar clk_disable_unprepare(gchip->clk); 209f3d705d5SArd Biesheuvel return ret; 2100da094d8SJassi Brar } 2110da094d8SJassi Brar 212f3d705d5SArd Biesheuvel if (has_acpi_companion(&pdev->dev)) 213f3d705d5SArd Biesheuvel acpi_gpiochip_request_interrupts(&gchip->gc); 214f3d705d5SArd Biesheuvel 215f3d705d5SArd Biesheuvel return 0; 2160da094d8SJassi Brar } 2170da094d8SJassi Brar 2180da094d8SJassi Brar static int mb86s70_gpio_remove(struct platform_device *pdev) 2190da094d8SJassi Brar { 2200da094d8SJassi Brar struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev); 2210da094d8SJassi Brar 222f3d705d5SArd Biesheuvel if (has_acpi_companion(&pdev->dev)) 223f3d705d5SArd Biesheuvel acpi_gpiochip_free_interrupts(&gchip->gc); 2240da094d8SJassi Brar gpiochip_remove(&gchip->gc); 2250da094d8SJassi Brar clk_disable_unprepare(gchip->clk); 2260da094d8SJassi Brar 2270da094d8SJassi Brar return 0; 2280da094d8SJassi Brar } 2290da094d8SJassi Brar 2300da094d8SJassi Brar static const struct of_device_id mb86s70_gpio_dt_ids[] = { 2310da094d8SJassi Brar { .compatible = "fujitsu,mb86s70-gpio" }, 2320da094d8SJassi Brar { /* sentinel */ } 2330da094d8SJassi Brar }; 234e1289dbaSArd Biesheuvel MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids); 2350da094d8SJassi Brar 236f3d705d5SArd Biesheuvel #ifdef CONFIG_ACPI 237f3d705d5SArd Biesheuvel static const struct acpi_device_id mb86s70_gpio_acpi_ids[] = { 238f3d705d5SArd Biesheuvel { "SCX0007" }, 239f3d705d5SArd Biesheuvel { /* sentinel */ } 240f3d705d5SArd Biesheuvel }; 241f3d705d5SArd Biesheuvel MODULE_DEVICE_TABLE(acpi, mb86s70_gpio_acpi_ids); 242f3d705d5SArd Biesheuvel #endif 243f3d705d5SArd Biesheuvel 2440da094d8SJassi Brar static struct platform_driver mb86s70_gpio_driver = { 2450da094d8SJassi Brar .driver = { 2460da094d8SJassi Brar .name = "mb86s70-gpio", 2470da094d8SJassi Brar .of_match_table = mb86s70_gpio_dt_ids, 248f3d705d5SArd Biesheuvel .acpi_match_table = ACPI_PTR(mb86s70_gpio_acpi_ids), 2490da094d8SJassi Brar }, 2500da094d8SJassi Brar .probe = mb86s70_gpio_probe, 2510da094d8SJassi Brar .remove = mb86s70_gpio_remove, 2520da094d8SJassi Brar }; 253e1289dbaSArd Biesheuvel module_platform_driver(mb86s70_gpio_driver); 2540da094d8SJassi Brar 255e1289dbaSArd Biesheuvel MODULE_DESCRIPTION("MB86S7x GPIO Driver"); 256e1289dbaSArd Biesheuvel MODULE_ALIAS("platform:mb86s70-gpio"); 257e1289dbaSArd Biesheuvel MODULE_LICENSE("GPL"); 258