10da094d8SJassi Brar /* 20da094d8SJassi Brar * linux/drivers/gpio/gpio-mb86s7x.c 30da094d8SJassi Brar * 40da094d8SJassi Brar * Copyright (C) 2015 Fujitsu Semiconductor Limited 50da094d8SJassi Brar * Copyright (C) 2015 Linaro Ltd. 60da094d8SJassi Brar * 70da094d8SJassi Brar * This program is free software: you can redistribute it and/or modify 80da094d8SJassi Brar * it under the terms of the GNU General Public License as published by 90da094d8SJassi Brar * the Free Software Foundation, version 2 of the License. 100da094d8SJassi Brar * 110da094d8SJassi Brar * This program is distributed in the hope that it will be useful, 120da094d8SJassi Brar * but WITHOUT ANY WARRANTY; without even the implied warranty of 130da094d8SJassi Brar * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 140da094d8SJassi Brar * GNU General Public License for more details. 150da094d8SJassi Brar */ 160da094d8SJassi Brar 170da094d8SJassi Brar #include <linux/io.h> 180da094d8SJassi Brar #include <linux/init.h> 190da094d8SJassi Brar #include <linux/clk.h> 20e1289dbaSArd Biesheuvel #include <linux/module.h> 210da094d8SJassi Brar #include <linux/err.h> 220da094d8SJassi Brar #include <linux/errno.h> 230da094d8SJassi Brar #include <linux/ioport.h> 240da094d8SJassi Brar #include <linux/of_device.h> 250da094d8SJassi Brar #include <linux/gpio/driver.h> 260da094d8SJassi Brar #include <linux/platform_device.h> 270da094d8SJassi Brar #include <linux/spinlock.h> 280da094d8SJassi Brar #include <linux/slab.h> 290da094d8SJassi Brar 300da094d8SJassi Brar /* 310da094d8SJassi Brar * Only first 8bits of a register correspond to each pin, 320da094d8SJassi Brar * so there are 4 registers for 32 pins. 330da094d8SJassi Brar */ 340da094d8SJassi Brar #define PDR(x) (0x0 + x / 8 * 4) 350da094d8SJassi Brar #define DDR(x) (0x10 + x / 8 * 4) 360da094d8SJassi Brar #define PFR(x) (0x20 + x / 8 * 4) 370da094d8SJassi Brar 380da094d8SJassi Brar #define OFFSET(x) BIT((x) % 8) 390da094d8SJassi Brar 400da094d8SJassi Brar struct mb86s70_gpio_chip { 410da094d8SJassi Brar struct gpio_chip gc; 420da094d8SJassi Brar void __iomem *base; 430da094d8SJassi Brar struct clk *clk; 440da094d8SJassi Brar spinlock_t lock; 450da094d8SJassi Brar }; 460da094d8SJassi Brar 470da094d8SJassi Brar static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio) 480da094d8SJassi Brar { 4901f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 500da094d8SJassi Brar unsigned long flags; 510da094d8SJassi Brar u32 val; 520da094d8SJassi Brar 530da094d8SJassi Brar spin_lock_irqsave(&gchip->lock, flags); 540da094d8SJassi Brar 550da094d8SJassi Brar val = readl(gchip->base + PFR(gpio)); 560da094d8SJassi Brar val &= ~OFFSET(gpio); 570da094d8SJassi Brar writel(val, gchip->base + PFR(gpio)); 580da094d8SJassi Brar 590da094d8SJassi Brar spin_unlock_irqrestore(&gchip->lock, flags); 600da094d8SJassi Brar 610da094d8SJassi Brar return 0; 620da094d8SJassi Brar } 630da094d8SJassi Brar 640da094d8SJassi Brar static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio) 650da094d8SJassi Brar { 6601f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 670da094d8SJassi Brar unsigned long flags; 680da094d8SJassi Brar u32 val; 690da094d8SJassi Brar 700da094d8SJassi Brar spin_lock_irqsave(&gchip->lock, flags); 710da094d8SJassi Brar 720da094d8SJassi Brar val = readl(gchip->base + PFR(gpio)); 730da094d8SJassi Brar val |= OFFSET(gpio); 740da094d8SJassi Brar writel(val, gchip->base + PFR(gpio)); 750da094d8SJassi Brar 760da094d8SJassi Brar spin_unlock_irqrestore(&gchip->lock, flags); 770da094d8SJassi Brar } 780da094d8SJassi Brar 790da094d8SJassi Brar static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) 800da094d8SJassi Brar { 8101f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 820da094d8SJassi Brar unsigned long flags; 830da094d8SJassi Brar unsigned char val; 840da094d8SJassi Brar 850da094d8SJassi Brar spin_lock_irqsave(&gchip->lock, flags); 860da094d8SJassi Brar 870da094d8SJassi Brar val = readl(gchip->base + DDR(gpio)); 880da094d8SJassi Brar val &= ~OFFSET(gpio); 890da094d8SJassi Brar writel(val, gchip->base + DDR(gpio)); 900da094d8SJassi Brar 910da094d8SJassi Brar spin_unlock_irqrestore(&gchip->lock, flags); 920da094d8SJassi Brar 930da094d8SJassi Brar return 0; 940da094d8SJassi Brar } 950da094d8SJassi Brar 960da094d8SJassi Brar static int mb86s70_gpio_direction_output(struct gpio_chip *gc, 970da094d8SJassi Brar unsigned gpio, int value) 980da094d8SJassi Brar { 9901f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 1000da094d8SJassi Brar unsigned long flags; 1010da094d8SJassi Brar unsigned char val; 1020da094d8SJassi Brar 1030da094d8SJassi Brar spin_lock_irqsave(&gchip->lock, flags); 1040da094d8SJassi Brar 1050da094d8SJassi Brar val = readl(gchip->base + PDR(gpio)); 1060da094d8SJassi Brar if (value) 1070da094d8SJassi Brar val |= OFFSET(gpio); 1080da094d8SJassi Brar else 1090da094d8SJassi Brar val &= ~OFFSET(gpio); 1100da094d8SJassi Brar writel(val, gchip->base + PDR(gpio)); 1110da094d8SJassi Brar 1120da094d8SJassi Brar val = readl(gchip->base + DDR(gpio)); 1130da094d8SJassi Brar val |= OFFSET(gpio); 1140da094d8SJassi Brar writel(val, gchip->base + DDR(gpio)); 1150da094d8SJassi Brar 1160da094d8SJassi Brar spin_unlock_irqrestore(&gchip->lock, flags); 1170da094d8SJassi Brar 1180da094d8SJassi Brar return 0; 1190da094d8SJassi Brar } 1200da094d8SJassi Brar 1210da094d8SJassi Brar static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio) 1220da094d8SJassi Brar { 12301f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 1240da094d8SJassi Brar 1250da094d8SJassi Brar return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio)); 1260da094d8SJassi Brar } 1270da094d8SJassi Brar 1280da094d8SJassi Brar static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value) 1290da094d8SJassi Brar { 13001f76b26SLinus Walleij struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 1310da094d8SJassi Brar unsigned long flags; 1320da094d8SJassi Brar unsigned char val; 1330da094d8SJassi Brar 1340da094d8SJassi Brar spin_lock_irqsave(&gchip->lock, flags); 1350da094d8SJassi Brar 1360da094d8SJassi Brar val = readl(gchip->base + PDR(gpio)); 1370da094d8SJassi Brar if (value) 1380da094d8SJassi Brar val |= OFFSET(gpio); 1390da094d8SJassi Brar else 1400da094d8SJassi Brar val &= ~OFFSET(gpio); 1410da094d8SJassi Brar writel(val, gchip->base + PDR(gpio)); 1420da094d8SJassi Brar 1430da094d8SJassi Brar spin_unlock_irqrestore(&gchip->lock, flags); 1440da094d8SJassi Brar } 1450da094d8SJassi Brar 1460da094d8SJassi Brar static int mb86s70_gpio_probe(struct platform_device *pdev) 1470da094d8SJassi Brar { 1480da094d8SJassi Brar struct mb86s70_gpio_chip *gchip; 1490da094d8SJassi Brar int ret; 1500da094d8SJassi Brar 1510da094d8SJassi Brar gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL); 1520da094d8SJassi Brar if (gchip == NULL) 1530da094d8SJassi Brar return -ENOMEM; 1540da094d8SJassi Brar 1550da094d8SJassi Brar platform_set_drvdata(pdev, gchip); 1560da094d8SJassi Brar 157329e23f9SEnrico Weigelt, metux IT consult gchip->base = devm_platform_ioremap_resource(pdev, 0); 1580da094d8SJassi Brar if (IS_ERR(gchip->base)) 1590da094d8SJassi Brar return PTR_ERR(gchip->base); 1600da094d8SJassi Brar 1610da094d8SJassi Brar gchip->clk = devm_clk_get(&pdev->dev, NULL); 1620da094d8SJassi Brar if (IS_ERR(gchip->clk)) 1630da094d8SJassi Brar return PTR_ERR(gchip->clk); 1640da094d8SJassi Brar 165d829b37aSArvind Yadav ret = clk_prepare_enable(gchip->clk); 166d829b37aSArvind Yadav if (ret) 167d829b37aSArvind Yadav return ret; 1680da094d8SJassi Brar 1690da094d8SJassi Brar spin_lock_init(&gchip->lock); 1700da094d8SJassi Brar 1710da094d8SJassi Brar gchip->gc.direction_output = mb86s70_gpio_direction_output; 1720da094d8SJassi Brar gchip->gc.direction_input = mb86s70_gpio_direction_input; 1730da094d8SJassi Brar gchip->gc.request = mb86s70_gpio_request; 1740da094d8SJassi Brar gchip->gc.free = mb86s70_gpio_free; 1750da094d8SJassi Brar gchip->gc.get = mb86s70_gpio_get; 1760da094d8SJassi Brar gchip->gc.set = mb86s70_gpio_set; 1770da094d8SJassi Brar gchip->gc.label = dev_name(&pdev->dev); 1780da094d8SJassi Brar gchip->gc.ngpio = 32; 1790da094d8SJassi Brar gchip->gc.owner = THIS_MODULE; 18058383c78SLinus Walleij gchip->gc.parent = &pdev->dev; 1810da094d8SJassi Brar gchip->gc.base = -1; 1820da094d8SJassi Brar 18301f76b26SLinus Walleij ret = gpiochip_add_data(&gchip->gc, gchip); 1840da094d8SJassi Brar if (ret) { 1850da094d8SJassi Brar dev_err(&pdev->dev, "couldn't register gpio driver\n"); 1860da094d8SJassi Brar clk_disable_unprepare(gchip->clk); 1870da094d8SJassi Brar } 1880da094d8SJassi Brar 1890da094d8SJassi Brar return ret; 1900da094d8SJassi Brar } 1910da094d8SJassi Brar 1920da094d8SJassi Brar static int mb86s70_gpio_remove(struct platform_device *pdev) 1930da094d8SJassi Brar { 1940da094d8SJassi Brar struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev); 1950da094d8SJassi Brar 1960da094d8SJassi Brar gpiochip_remove(&gchip->gc); 1970da094d8SJassi Brar clk_disable_unprepare(gchip->clk); 1980da094d8SJassi Brar 1990da094d8SJassi Brar return 0; 2000da094d8SJassi Brar } 2010da094d8SJassi Brar 2020da094d8SJassi Brar static const struct of_device_id mb86s70_gpio_dt_ids[] = { 2030da094d8SJassi Brar { .compatible = "fujitsu,mb86s70-gpio" }, 2040da094d8SJassi Brar { /* sentinel */ } 2050da094d8SJassi Brar }; 206e1289dbaSArd Biesheuvel MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids); 2070da094d8SJassi Brar 2080da094d8SJassi Brar static struct platform_driver mb86s70_gpio_driver = { 2090da094d8SJassi Brar .driver = { 2100da094d8SJassi Brar .name = "mb86s70-gpio", 2110da094d8SJassi Brar .of_match_table = mb86s70_gpio_dt_ids, 2120da094d8SJassi Brar }, 2130da094d8SJassi Brar .probe = mb86s70_gpio_probe, 2140da094d8SJassi Brar .remove = mb86s70_gpio_remove, 2150da094d8SJassi Brar }; 216e1289dbaSArd Biesheuvel module_platform_driver(mb86s70_gpio_driver); 2170da094d8SJassi Brar 218e1289dbaSArd Biesheuvel MODULE_DESCRIPTION("MB86S7x GPIO Driver"); 219e1289dbaSArd Biesheuvel MODULE_ALIAS("platform:mb86s70-gpio"); 220e1289dbaSArd Biesheuvel MODULE_LICENSE("GPL"); 221