1 /* 2 * GPIO driver for LPC32xx SoC 3 * 4 * Author: Kevin Wells <kevin.wells@nxp.com> 5 * 6 * Copyright (C) 2010 NXP Semiconductors 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/io.h> 22 #include <linux/errno.h> 23 #include <linux/gpio.h> 24 #include <linux/of_gpio.h> 25 #include <linux/platform_device.h> 26 #include <linux/module.h> 27 28 #include <mach/hardware.h> 29 #include <mach/platform.h> 30 #include <mach/gpio-lpc32xx.h> 31 32 #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) 33 #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) 34 #define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) 35 #define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) 36 #define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) 37 #define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) 38 #define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) 39 #define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) 40 #define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) 41 #define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) 42 #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) 43 #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) 44 #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) 45 #define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) 46 #define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) 47 #define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) 48 #define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) 49 #define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) 50 #define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) 51 #define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) 52 #define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) 53 #define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) 54 #define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) 55 #define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) 56 #define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) 57 #define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) 58 #define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) 59 60 #define GPIO012_PIN_TO_BIT(x) (1 << (x)) 61 #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) 62 #define GPO3_PIN_TO_BIT(x) (1 << (x)) 63 #define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 64 #define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x)) 65 #define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1) 66 #define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1) 67 #define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 68 #define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 69 70 struct gpio_regs { 71 void __iomem *inp_state; 72 void __iomem *outp_state; 73 void __iomem *outp_set; 74 void __iomem *outp_clr; 75 void __iomem *dir_set; 76 void __iomem *dir_clr; 77 }; 78 79 /* 80 * GPIO names 81 */ 82 static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = { 83 "p0.0", "p0.1", "p0.2", "p0.3", 84 "p0.4", "p0.5", "p0.6", "p0.7" 85 }; 86 87 static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = { 88 "p1.0", "p1.1", "p1.2", "p1.3", 89 "p1.4", "p1.5", "p1.6", "p1.7", 90 "p1.8", "p1.9", "p1.10", "p1.11", 91 "p1.12", "p1.13", "p1.14", "p1.15", 92 "p1.16", "p1.17", "p1.18", "p1.19", 93 "p1.20", "p1.21", "p1.22", "p1.23", 94 }; 95 96 static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = { 97 "p2.0", "p2.1", "p2.2", "p2.3", 98 "p2.4", "p2.5", "p2.6", "p2.7", 99 "p2.8", "p2.9", "p2.10", "p2.11", 100 "p2.12" 101 }; 102 103 static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = { 104 "gpio00", "gpio01", "gpio02", "gpio03", 105 "gpio04", "gpio05" 106 }; 107 108 static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = { 109 "gpi00", "gpi01", "gpi02", "gpi03", 110 "gpi04", "gpi05", "gpi06", "gpi07", 111 "gpi08", "gpi09", NULL, NULL, 112 NULL, NULL, NULL, "gpi15", 113 "gpi16", "gpi17", "gpi18", "gpi19", 114 "gpi20", "gpi21", "gpi22", "gpi23", 115 "gpi24", "gpi25", "gpi26", "gpi27" 116 }; 117 118 static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = { 119 "gpo00", "gpo01", "gpo02", "gpo03", 120 "gpo04", "gpo05", "gpo06", "gpo07", 121 "gpo08", "gpo09", "gpo10", "gpo11", 122 "gpo12", "gpo13", "gpo14", "gpo15", 123 "gpo16", "gpo17", "gpo18", "gpo19", 124 "gpo20", "gpo21", "gpo22", "gpo23" 125 }; 126 127 static struct gpio_regs gpio_grp_regs_p0 = { 128 .inp_state = LPC32XX_GPIO_P0_INP_STATE, 129 .outp_set = LPC32XX_GPIO_P0_OUTP_SET, 130 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR, 131 .dir_set = LPC32XX_GPIO_P0_DIR_SET, 132 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR, 133 }; 134 135 static struct gpio_regs gpio_grp_regs_p1 = { 136 .inp_state = LPC32XX_GPIO_P1_INP_STATE, 137 .outp_set = LPC32XX_GPIO_P1_OUTP_SET, 138 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR, 139 .dir_set = LPC32XX_GPIO_P1_DIR_SET, 140 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR, 141 }; 142 143 static struct gpio_regs gpio_grp_regs_p2 = { 144 .inp_state = LPC32XX_GPIO_P2_INP_STATE, 145 .outp_set = LPC32XX_GPIO_P2_OUTP_SET, 146 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR, 147 .dir_set = LPC32XX_GPIO_P2_DIR_SET, 148 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, 149 }; 150 151 static struct gpio_regs gpio_grp_regs_p3 = { 152 .inp_state = LPC32XX_GPIO_P3_INP_STATE, 153 .outp_state = LPC32XX_GPIO_P3_OUTP_STATE, 154 .outp_set = LPC32XX_GPIO_P3_OUTP_SET, 155 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR, 156 .dir_set = LPC32XX_GPIO_P2_DIR_SET, 157 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, 158 }; 159 160 struct lpc32xx_gpio_chip { 161 struct gpio_chip chip; 162 struct gpio_regs *gpio_grp; 163 }; 164 165 static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio( 166 struct gpio_chip *gpc) 167 { 168 return container_of(gpc, struct lpc32xx_gpio_chip, chip); 169 } 170 171 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, 172 unsigned pin, int input) 173 { 174 if (input) 175 __raw_writel(GPIO012_PIN_TO_BIT(pin), 176 group->gpio_grp->dir_clr); 177 else 178 __raw_writel(GPIO012_PIN_TO_BIT(pin), 179 group->gpio_grp->dir_set); 180 } 181 182 static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, 183 unsigned pin, int input) 184 { 185 u32 u = GPIO3_PIN_TO_BIT(pin); 186 187 if (input) 188 __raw_writel(u, group->gpio_grp->dir_clr); 189 else 190 __raw_writel(u, group->gpio_grp->dir_set); 191 } 192 193 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, 194 unsigned pin, int high) 195 { 196 if (high) 197 __raw_writel(GPIO012_PIN_TO_BIT(pin), 198 group->gpio_grp->outp_set); 199 else 200 __raw_writel(GPIO012_PIN_TO_BIT(pin), 201 group->gpio_grp->outp_clr); 202 } 203 204 static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, 205 unsigned pin, int high) 206 { 207 u32 u = GPIO3_PIN_TO_BIT(pin); 208 209 if (high) 210 __raw_writel(u, group->gpio_grp->outp_set); 211 else 212 __raw_writel(u, group->gpio_grp->outp_clr); 213 } 214 215 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, 216 unsigned pin, int high) 217 { 218 if (high) 219 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); 220 else 221 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); 222 } 223 224 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, 225 unsigned pin) 226 { 227 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), 228 pin); 229 } 230 231 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, 232 unsigned pin) 233 { 234 int state = __raw_readl(group->gpio_grp->inp_state); 235 236 /* 237 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped 238 * to bits 10..14, while GPIOP3-5 is mapped to bit 24. 239 */ 240 return GPIO3_PIN_IN_SEL(state, pin); 241 } 242 243 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, 244 unsigned pin) 245 { 246 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); 247 } 248 249 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, 250 unsigned pin) 251 { 252 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); 253 } 254 255 /* 256 * GENERIC_GPIO primitives. 257 */ 258 static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip, 259 unsigned pin) 260 { 261 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 262 263 __set_gpio_dir_p012(group, pin, 1); 264 265 return 0; 266 } 267 268 static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip, 269 unsigned pin) 270 { 271 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 272 273 __set_gpio_dir_p3(group, pin, 1); 274 275 return 0; 276 } 277 278 static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip, 279 unsigned pin) 280 { 281 return 0; 282 } 283 284 static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin) 285 { 286 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 287 288 return __get_gpio_state_p012(group, pin); 289 } 290 291 static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin) 292 { 293 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 294 295 return __get_gpio_state_p3(group, pin); 296 } 297 298 static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin) 299 { 300 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 301 302 return __get_gpi_state_p3(group, pin); 303 } 304 305 static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin, 306 int value) 307 { 308 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 309 310 __set_gpio_dir_p012(group, pin, 0); 311 312 return 0; 313 } 314 315 static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin, 316 int value) 317 { 318 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 319 320 __set_gpio_dir_p3(group, pin, 0); 321 322 return 0; 323 } 324 325 static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin, 326 int value) 327 { 328 return 0; 329 } 330 331 static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin, 332 int value) 333 { 334 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 335 336 __set_gpio_level_p012(group, pin, value); 337 } 338 339 static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin, 340 int value) 341 { 342 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 343 344 __set_gpio_level_p3(group, pin, value); 345 } 346 347 static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin, 348 int value) 349 { 350 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 351 352 __set_gpo_level_p3(group, pin, value); 353 } 354 355 static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin) 356 { 357 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 358 359 return __get_gpo_state_p3(group, pin); 360 } 361 362 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) 363 { 364 if (pin < chip->ngpio) 365 return 0; 366 367 return -EINVAL; 368 } 369 370 static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = { 371 { 372 .chip = { 373 .label = "gpio_p0", 374 .direction_input = lpc32xx_gpio_dir_input_p012, 375 .get = lpc32xx_gpio_get_value_p012, 376 .direction_output = lpc32xx_gpio_dir_output_p012, 377 .set = lpc32xx_gpio_set_value_p012, 378 .request = lpc32xx_gpio_request, 379 .base = LPC32XX_GPIO_P0_GRP, 380 .ngpio = LPC32XX_GPIO_P0_MAX, 381 .names = gpio_p0_names, 382 .can_sleep = 0, 383 }, 384 .gpio_grp = &gpio_grp_regs_p0, 385 }, 386 { 387 .chip = { 388 .label = "gpio_p1", 389 .direction_input = lpc32xx_gpio_dir_input_p012, 390 .get = lpc32xx_gpio_get_value_p012, 391 .direction_output = lpc32xx_gpio_dir_output_p012, 392 .set = lpc32xx_gpio_set_value_p012, 393 .request = lpc32xx_gpio_request, 394 .base = LPC32XX_GPIO_P1_GRP, 395 .ngpio = LPC32XX_GPIO_P1_MAX, 396 .names = gpio_p1_names, 397 .can_sleep = 0, 398 }, 399 .gpio_grp = &gpio_grp_regs_p1, 400 }, 401 { 402 .chip = { 403 .label = "gpio_p2", 404 .direction_input = lpc32xx_gpio_dir_input_p012, 405 .get = lpc32xx_gpio_get_value_p012, 406 .direction_output = lpc32xx_gpio_dir_output_p012, 407 .set = lpc32xx_gpio_set_value_p012, 408 .request = lpc32xx_gpio_request, 409 .base = LPC32XX_GPIO_P2_GRP, 410 .ngpio = LPC32XX_GPIO_P2_MAX, 411 .names = gpio_p2_names, 412 .can_sleep = 0, 413 }, 414 .gpio_grp = &gpio_grp_regs_p2, 415 }, 416 { 417 .chip = { 418 .label = "gpio_p3", 419 .direction_input = lpc32xx_gpio_dir_input_p3, 420 .get = lpc32xx_gpio_get_value_p3, 421 .direction_output = lpc32xx_gpio_dir_output_p3, 422 .set = lpc32xx_gpio_set_value_p3, 423 .request = lpc32xx_gpio_request, 424 .base = LPC32XX_GPIO_P3_GRP, 425 .ngpio = LPC32XX_GPIO_P3_MAX, 426 .names = gpio_p3_names, 427 .can_sleep = 0, 428 }, 429 .gpio_grp = &gpio_grp_regs_p3, 430 }, 431 { 432 .chip = { 433 .label = "gpi_p3", 434 .direction_input = lpc32xx_gpio_dir_in_always, 435 .get = lpc32xx_gpi_get_value, 436 .request = lpc32xx_gpio_request, 437 .base = LPC32XX_GPI_P3_GRP, 438 .ngpio = LPC32XX_GPI_P3_MAX, 439 .names = gpi_p3_names, 440 .can_sleep = 0, 441 }, 442 .gpio_grp = &gpio_grp_regs_p3, 443 }, 444 { 445 .chip = { 446 .label = "gpo_p3", 447 .direction_output = lpc32xx_gpio_dir_out_always, 448 .set = lpc32xx_gpo_set_value, 449 .get = lpc32xx_gpo_get_value, 450 .request = lpc32xx_gpio_request, 451 .base = LPC32XX_GPO_P3_GRP, 452 .ngpio = LPC32XX_GPO_P3_MAX, 453 .names = gpo_p3_names, 454 .can_sleep = 0, 455 }, 456 .gpio_grp = &gpio_grp_regs_p3, 457 }, 458 }; 459 460 static int lpc32xx_of_xlate(struct gpio_chip *gc, 461 const struct of_phandle_args *gpiospec, u32 *flags) 462 { 463 /* Is this the correct bank? */ 464 u32 bank = gpiospec->args[0]; 465 if ((bank > ARRAY_SIZE(lpc32xx_gpiochip) || 466 (gc != &lpc32xx_gpiochip[bank].chip))) 467 return -EINVAL; 468 469 if (flags) 470 *flags = gpiospec->args[2]; 471 return gpiospec->args[1]; 472 } 473 474 static int __devinit lpc32xx_gpio_probe(struct platform_device *pdev) 475 { 476 int i; 477 478 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) { 479 if (pdev->dev.of_node) { 480 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate; 481 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; 482 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node; 483 } 484 gpiochip_add(&lpc32xx_gpiochip[i].chip); 485 } 486 487 return 0; 488 } 489 490 #ifdef CONFIG_OF 491 static struct of_device_id lpc32xx_gpio_of_match[] __devinitdata = { 492 { .compatible = "nxp,lpc3220-gpio", }, 493 { }, 494 }; 495 #endif 496 497 static struct platform_driver lpc32xx_gpio_driver = { 498 .driver = { 499 .name = "lpc32xx-gpio", 500 .owner = THIS_MODULE, 501 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match), 502 }, 503 .probe = lpc32xx_gpio_probe, 504 }; 505 506 module_platform_driver(lpc32xx_gpio_driver); 507