1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * GPIO driver for LPC32xx SoC 4 * 5 * Author: Kevin Wells <kevin.wells@nxp.com> 6 * 7 * Copyright (C) 2010 NXP Semiconductors 8 */ 9 10 #include <linux/kernel.h> 11 #include <linux/init.h> 12 #include <linux/io.h> 13 #include <linux/errno.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/of.h> 16 #include <linux/platform_device.h> 17 #include <linux/module.h> 18 19 #include <mach/hardware.h> 20 #include <mach/platform.h> 21 22 #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) 23 #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) 24 #define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) 25 #define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) 26 #define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) 27 #define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) 28 #define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) 29 #define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) 30 #define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) 31 #define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) 32 #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) 33 #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) 34 #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) 35 #define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) 36 #define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) 37 #define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) 38 #define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) 39 #define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) 40 #define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) 41 #define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) 42 #define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) 43 #define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) 44 #define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) 45 #define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) 46 #define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) 47 #define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) 48 #define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) 49 50 #define GPIO012_PIN_TO_BIT(x) (1 << (x)) 51 #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) 52 #define GPO3_PIN_TO_BIT(x) (1 << (x)) 53 #define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 54 #define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x)) 55 #define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1) 56 #define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1) 57 #define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 58 #define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 59 60 #define LPC32XX_GPIO_P0_MAX 8 61 #define LPC32XX_GPIO_P1_MAX 24 62 #define LPC32XX_GPIO_P2_MAX 13 63 #define LPC32XX_GPIO_P3_MAX 6 64 #define LPC32XX_GPI_P3_MAX 29 65 #define LPC32XX_GPO_P3_MAX 24 66 67 #define LPC32XX_GPIO_P0_GRP 0 68 #define LPC32XX_GPIO_P1_GRP (LPC32XX_GPIO_P0_GRP + LPC32XX_GPIO_P0_MAX) 69 #define LPC32XX_GPIO_P2_GRP (LPC32XX_GPIO_P1_GRP + LPC32XX_GPIO_P1_MAX) 70 #define LPC32XX_GPIO_P3_GRP (LPC32XX_GPIO_P2_GRP + LPC32XX_GPIO_P2_MAX) 71 #define LPC32XX_GPI_P3_GRP (LPC32XX_GPIO_P3_GRP + LPC32XX_GPIO_P3_MAX) 72 #define LPC32XX_GPO_P3_GRP (LPC32XX_GPI_P3_GRP + LPC32XX_GPI_P3_MAX) 73 74 struct gpio_regs { 75 void __iomem *inp_state; 76 void __iomem *outp_state; 77 void __iomem *outp_set; 78 void __iomem *outp_clr; 79 void __iomem *dir_set; 80 void __iomem *dir_clr; 81 }; 82 83 /* 84 * GPIO names 85 */ 86 static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = { 87 "p0.0", "p0.1", "p0.2", "p0.3", 88 "p0.4", "p0.5", "p0.6", "p0.7" 89 }; 90 91 static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = { 92 "p1.0", "p1.1", "p1.2", "p1.3", 93 "p1.4", "p1.5", "p1.6", "p1.7", 94 "p1.8", "p1.9", "p1.10", "p1.11", 95 "p1.12", "p1.13", "p1.14", "p1.15", 96 "p1.16", "p1.17", "p1.18", "p1.19", 97 "p1.20", "p1.21", "p1.22", "p1.23", 98 }; 99 100 static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = { 101 "p2.0", "p2.1", "p2.2", "p2.3", 102 "p2.4", "p2.5", "p2.6", "p2.7", 103 "p2.8", "p2.9", "p2.10", "p2.11", 104 "p2.12" 105 }; 106 107 static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = { 108 "gpio00", "gpio01", "gpio02", "gpio03", 109 "gpio04", "gpio05" 110 }; 111 112 static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = { 113 "gpi00", "gpi01", "gpi02", "gpi03", 114 "gpi04", "gpi05", "gpi06", "gpi07", 115 "gpi08", "gpi09", NULL, NULL, 116 NULL, NULL, NULL, "gpi15", 117 "gpi16", "gpi17", "gpi18", "gpi19", 118 "gpi20", "gpi21", "gpi22", "gpi23", 119 "gpi24", "gpi25", "gpi26", "gpi27", 120 "gpi28" 121 }; 122 123 static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = { 124 "gpo00", "gpo01", "gpo02", "gpo03", 125 "gpo04", "gpo05", "gpo06", "gpo07", 126 "gpo08", "gpo09", "gpo10", "gpo11", 127 "gpo12", "gpo13", "gpo14", "gpo15", 128 "gpo16", "gpo17", "gpo18", "gpo19", 129 "gpo20", "gpo21", "gpo22", "gpo23" 130 }; 131 132 static struct gpio_regs gpio_grp_regs_p0 = { 133 .inp_state = LPC32XX_GPIO_P0_INP_STATE, 134 .outp_set = LPC32XX_GPIO_P0_OUTP_SET, 135 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR, 136 .dir_set = LPC32XX_GPIO_P0_DIR_SET, 137 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR, 138 }; 139 140 static struct gpio_regs gpio_grp_regs_p1 = { 141 .inp_state = LPC32XX_GPIO_P1_INP_STATE, 142 .outp_set = LPC32XX_GPIO_P1_OUTP_SET, 143 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR, 144 .dir_set = LPC32XX_GPIO_P1_DIR_SET, 145 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR, 146 }; 147 148 static struct gpio_regs gpio_grp_regs_p2 = { 149 .inp_state = LPC32XX_GPIO_P2_INP_STATE, 150 .outp_set = LPC32XX_GPIO_P2_OUTP_SET, 151 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR, 152 .dir_set = LPC32XX_GPIO_P2_DIR_SET, 153 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, 154 }; 155 156 static struct gpio_regs gpio_grp_regs_p3 = { 157 .inp_state = LPC32XX_GPIO_P3_INP_STATE, 158 .outp_state = LPC32XX_GPIO_P3_OUTP_STATE, 159 .outp_set = LPC32XX_GPIO_P3_OUTP_SET, 160 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR, 161 .dir_set = LPC32XX_GPIO_P2_DIR_SET, 162 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, 163 }; 164 165 struct lpc32xx_gpio_chip { 166 struct gpio_chip chip; 167 struct gpio_regs *gpio_grp; 168 }; 169 170 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, 171 unsigned pin, int input) 172 { 173 if (input) 174 __raw_writel(GPIO012_PIN_TO_BIT(pin), 175 group->gpio_grp->dir_clr); 176 else 177 __raw_writel(GPIO012_PIN_TO_BIT(pin), 178 group->gpio_grp->dir_set); 179 } 180 181 static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, 182 unsigned pin, int input) 183 { 184 u32 u = GPIO3_PIN_TO_BIT(pin); 185 186 if (input) 187 __raw_writel(u, group->gpio_grp->dir_clr); 188 else 189 __raw_writel(u, group->gpio_grp->dir_set); 190 } 191 192 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, 193 unsigned pin, int high) 194 { 195 if (high) 196 __raw_writel(GPIO012_PIN_TO_BIT(pin), 197 group->gpio_grp->outp_set); 198 else 199 __raw_writel(GPIO012_PIN_TO_BIT(pin), 200 group->gpio_grp->outp_clr); 201 } 202 203 static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, 204 unsigned pin, int high) 205 { 206 u32 u = GPIO3_PIN_TO_BIT(pin); 207 208 if (high) 209 __raw_writel(u, group->gpio_grp->outp_set); 210 else 211 __raw_writel(u, group->gpio_grp->outp_clr); 212 } 213 214 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, 215 unsigned pin, int high) 216 { 217 if (high) 218 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); 219 else 220 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); 221 } 222 223 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, 224 unsigned pin) 225 { 226 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), 227 pin); 228 } 229 230 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, 231 unsigned pin) 232 { 233 int state = __raw_readl(group->gpio_grp->inp_state); 234 235 /* 236 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped 237 * to bits 10..14, while GPIOP3-5 is mapped to bit 24. 238 */ 239 return GPIO3_PIN_IN_SEL(state, pin); 240 } 241 242 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, 243 unsigned pin) 244 { 245 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); 246 } 247 248 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, 249 unsigned pin) 250 { 251 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); 252 } 253 254 /* 255 * GPIO primitives. 256 */ 257 static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip, 258 unsigned pin) 259 { 260 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 261 262 __set_gpio_dir_p012(group, pin, 1); 263 264 return 0; 265 } 266 267 static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip, 268 unsigned pin) 269 { 270 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 271 272 __set_gpio_dir_p3(group, pin, 1); 273 274 return 0; 275 } 276 277 static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip, 278 unsigned pin) 279 { 280 return 0; 281 } 282 283 static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin) 284 { 285 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 286 287 return !!__get_gpio_state_p012(group, pin); 288 } 289 290 static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin) 291 { 292 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 293 294 return !!__get_gpio_state_p3(group, pin); 295 } 296 297 static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin) 298 { 299 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 300 301 return !!__get_gpi_state_p3(group, pin); 302 } 303 304 static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin, 305 int value) 306 { 307 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 308 309 __set_gpio_level_p012(group, pin, value); 310 __set_gpio_dir_p012(group, pin, 0); 311 312 return 0; 313 } 314 315 static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin, 316 int value) 317 { 318 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 319 320 __set_gpio_level_p3(group, pin, value); 321 __set_gpio_dir_p3(group, pin, 0); 322 323 return 0; 324 } 325 326 static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin, 327 int value) 328 { 329 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 330 331 __set_gpo_level_p3(group, pin, value); 332 return 0; 333 } 334 335 static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin, 336 int value) 337 { 338 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 339 340 __set_gpio_level_p012(group, pin, value); 341 } 342 343 static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin, 344 int value) 345 { 346 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 347 348 __set_gpio_level_p3(group, pin, value); 349 } 350 351 static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin, 352 int value) 353 { 354 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 355 356 __set_gpo_level_p3(group, pin, value); 357 } 358 359 static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin) 360 { 361 struct lpc32xx_gpio_chip *group = gpiochip_get_data(chip); 362 363 return !!__get_gpo_state_p3(group, pin); 364 } 365 366 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) 367 { 368 if (pin < chip->ngpio) 369 return 0; 370 371 return -EINVAL; 372 } 373 374 static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset) 375 { 376 return -ENXIO; 377 } 378 379 static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset) 380 { 381 return -ENXIO; 382 } 383 384 static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset) 385 { 386 return -ENXIO; 387 } 388 389 static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = { 390 { 391 .chip = { 392 .label = "gpio_p0", 393 .direction_input = lpc32xx_gpio_dir_input_p012, 394 .get = lpc32xx_gpio_get_value_p012, 395 .direction_output = lpc32xx_gpio_dir_output_p012, 396 .set = lpc32xx_gpio_set_value_p012, 397 .request = lpc32xx_gpio_request, 398 .to_irq = lpc32xx_gpio_to_irq_p01, 399 .base = LPC32XX_GPIO_P0_GRP, 400 .ngpio = LPC32XX_GPIO_P0_MAX, 401 .names = gpio_p0_names, 402 .can_sleep = false, 403 }, 404 .gpio_grp = &gpio_grp_regs_p0, 405 }, 406 { 407 .chip = { 408 .label = "gpio_p1", 409 .direction_input = lpc32xx_gpio_dir_input_p012, 410 .get = lpc32xx_gpio_get_value_p012, 411 .direction_output = lpc32xx_gpio_dir_output_p012, 412 .set = lpc32xx_gpio_set_value_p012, 413 .request = lpc32xx_gpio_request, 414 .to_irq = lpc32xx_gpio_to_irq_p01, 415 .base = LPC32XX_GPIO_P1_GRP, 416 .ngpio = LPC32XX_GPIO_P1_MAX, 417 .names = gpio_p1_names, 418 .can_sleep = false, 419 }, 420 .gpio_grp = &gpio_grp_regs_p1, 421 }, 422 { 423 .chip = { 424 .label = "gpio_p2", 425 .direction_input = lpc32xx_gpio_dir_input_p012, 426 .get = lpc32xx_gpio_get_value_p012, 427 .direction_output = lpc32xx_gpio_dir_output_p012, 428 .set = lpc32xx_gpio_set_value_p012, 429 .request = lpc32xx_gpio_request, 430 .base = LPC32XX_GPIO_P2_GRP, 431 .ngpio = LPC32XX_GPIO_P2_MAX, 432 .names = gpio_p2_names, 433 .can_sleep = false, 434 }, 435 .gpio_grp = &gpio_grp_regs_p2, 436 }, 437 { 438 .chip = { 439 .label = "gpio_p3", 440 .direction_input = lpc32xx_gpio_dir_input_p3, 441 .get = lpc32xx_gpio_get_value_p3, 442 .direction_output = lpc32xx_gpio_dir_output_p3, 443 .set = lpc32xx_gpio_set_value_p3, 444 .request = lpc32xx_gpio_request, 445 .to_irq = lpc32xx_gpio_to_irq_gpio_p3, 446 .base = LPC32XX_GPIO_P3_GRP, 447 .ngpio = LPC32XX_GPIO_P3_MAX, 448 .names = gpio_p3_names, 449 .can_sleep = false, 450 }, 451 .gpio_grp = &gpio_grp_regs_p3, 452 }, 453 { 454 .chip = { 455 .label = "gpi_p3", 456 .direction_input = lpc32xx_gpio_dir_in_always, 457 .get = lpc32xx_gpi_get_value, 458 .request = lpc32xx_gpio_request, 459 .to_irq = lpc32xx_gpio_to_irq_gpi_p3, 460 .base = LPC32XX_GPI_P3_GRP, 461 .ngpio = LPC32XX_GPI_P3_MAX, 462 .names = gpi_p3_names, 463 .can_sleep = false, 464 }, 465 .gpio_grp = &gpio_grp_regs_p3, 466 }, 467 { 468 .chip = { 469 .label = "gpo_p3", 470 .direction_output = lpc32xx_gpio_dir_out_always, 471 .set = lpc32xx_gpo_set_value, 472 .get = lpc32xx_gpo_get_value, 473 .request = lpc32xx_gpio_request, 474 .base = LPC32XX_GPO_P3_GRP, 475 .ngpio = LPC32XX_GPO_P3_MAX, 476 .names = gpo_p3_names, 477 .can_sleep = false, 478 }, 479 .gpio_grp = &gpio_grp_regs_p3, 480 }, 481 }; 482 483 static int lpc32xx_of_xlate(struct gpio_chip *gc, 484 const struct of_phandle_args *gpiospec, u32 *flags) 485 { 486 /* Is this the correct bank? */ 487 u32 bank = gpiospec->args[0]; 488 if ((bank >= ARRAY_SIZE(lpc32xx_gpiochip) || 489 (gc != &lpc32xx_gpiochip[bank].chip))) 490 return -EINVAL; 491 492 if (flags) 493 *flags = gpiospec->args[2]; 494 return gpiospec->args[1]; 495 } 496 497 static int lpc32xx_gpio_probe(struct platform_device *pdev) 498 { 499 int i; 500 501 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) { 502 if (pdev->dev.of_node) { 503 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate; 504 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; 505 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node; 506 } 507 devm_gpiochip_add_data(&pdev->dev, &lpc32xx_gpiochip[i].chip, 508 &lpc32xx_gpiochip[i]); 509 } 510 511 return 0; 512 } 513 514 #ifdef CONFIG_OF 515 static const struct of_device_id lpc32xx_gpio_of_match[] = { 516 { .compatible = "nxp,lpc3220-gpio", }, 517 { }, 518 }; 519 #endif 520 521 static struct platform_driver lpc32xx_gpio_driver = { 522 .driver = { 523 .name = "lpc32xx-gpio", 524 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match), 525 }, 526 .probe = lpc32xx_gpio_probe, 527 }; 528 529 module_platform_driver(lpc32xx_gpio_driver); 530