1 /* 2 * GPIO driver for LPC32xx SoC 3 * 4 * Author: Kevin Wells <kevin.wells@nxp.com> 5 * 6 * Copyright (C) 2010 NXP Semiconductors 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/io.h> 22 #include <linux/errno.h> 23 #include <linux/gpio.h> 24 #include <linux/of_gpio.h> 25 #include <linux/platform_device.h> 26 #include <linux/module.h> 27 28 #include <mach/hardware.h> 29 #include <mach/platform.h> 30 #include <mach/gpio-lpc32xx.h> 31 #include <mach/irqs.h> 32 33 #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) 34 #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) 35 #define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) 36 #define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) 37 #define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) 38 #define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) 39 #define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) 40 #define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) 41 #define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) 42 #define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) 43 #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) 44 #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) 45 #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) 46 #define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) 47 #define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) 48 #define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) 49 #define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) 50 #define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) 51 #define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) 52 #define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) 53 #define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) 54 #define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) 55 #define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) 56 #define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) 57 #define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) 58 #define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) 59 #define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) 60 61 #define GPIO012_PIN_TO_BIT(x) (1 << (x)) 62 #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) 63 #define GPO3_PIN_TO_BIT(x) (1 << (x)) 64 #define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 65 #define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x)) 66 #define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1) 67 #define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1) 68 #define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 69 #define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 70 71 struct gpio_regs { 72 void __iomem *inp_state; 73 void __iomem *outp_state; 74 void __iomem *outp_set; 75 void __iomem *outp_clr; 76 void __iomem *dir_set; 77 void __iomem *dir_clr; 78 }; 79 80 /* 81 * GPIO names 82 */ 83 static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = { 84 "p0.0", "p0.1", "p0.2", "p0.3", 85 "p0.4", "p0.5", "p0.6", "p0.7" 86 }; 87 88 static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = { 89 "p1.0", "p1.1", "p1.2", "p1.3", 90 "p1.4", "p1.5", "p1.6", "p1.7", 91 "p1.8", "p1.9", "p1.10", "p1.11", 92 "p1.12", "p1.13", "p1.14", "p1.15", 93 "p1.16", "p1.17", "p1.18", "p1.19", 94 "p1.20", "p1.21", "p1.22", "p1.23", 95 }; 96 97 static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = { 98 "p2.0", "p2.1", "p2.2", "p2.3", 99 "p2.4", "p2.5", "p2.6", "p2.7", 100 "p2.8", "p2.9", "p2.10", "p2.11", 101 "p2.12" 102 }; 103 104 static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = { 105 "gpio00", "gpio01", "gpio02", "gpio03", 106 "gpio04", "gpio05" 107 }; 108 109 static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = { 110 "gpi00", "gpi01", "gpi02", "gpi03", 111 "gpi04", "gpi05", "gpi06", "gpi07", 112 "gpi08", "gpi09", NULL, NULL, 113 NULL, NULL, NULL, "gpi15", 114 "gpi16", "gpi17", "gpi18", "gpi19", 115 "gpi20", "gpi21", "gpi22", "gpi23", 116 "gpi24", "gpi25", "gpi26", "gpi27", 117 "gpi28" 118 }; 119 120 static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = { 121 "gpo00", "gpo01", "gpo02", "gpo03", 122 "gpo04", "gpo05", "gpo06", "gpo07", 123 "gpo08", "gpo09", "gpo10", "gpo11", 124 "gpo12", "gpo13", "gpo14", "gpo15", 125 "gpo16", "gpo17", "gpo18", "gpo19", 126 "gpo20", "gpo21", "gpo22", "gpo23" 127 }; 128 129 static struct gpio_regs gpio_grp_regs_p0 = { 130 .inp_state = LPC32XX_GPIO_P0_INP_STATE, 131 .outp_set = LPC32XX_GPIO_P0_OUTP_SET, 132 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR, 133 .dir_set = LPC32XX_GPIO_P0_DIR_SET, 134 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR, 135 }; 136 137 static struct gpio_regs gpio_grp_regs_p1 = { 138 .inp_state = LPC32XX_GPIO_P1_INP_STATE, 139 .outp_set = LPC32XX_GPIO_P1_OUTP_SET, 140 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR, 141 .dir_set = LPC32XX_GPIO_P1_DIR_SET, 142 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR, 143 }; 144 145 static struct gpio_regs gpio_grp_regs_p2 = { 146 .inp_state = LPC32XX_GPIO_P2_INP_STATE, 147 .outp_set = LPC32XX_GPIO_P2_OUTP_SET, 148 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR, 149 .dir_set = LPC32XX_GPIO_P2_DIR_SET, 150 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, 151 }; 152 153 static struct gpio_regs gpio_grp_regs_p3 = { 154 .inp_state = LPC32XX_GPIO_P3_INP_STATE, 155 .outp_state = LPC32XX_GPIO_P3_OUTP_STATE, 156 .outp_set = LPC32XX_GPIO_P3_OUTP_SET, 157 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR, 158 .dir_set = LPC32XX_GPIO_P2_DIR_SET, 159 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, 160 }; 161 162 struct lpc32xx_gpio_chip { 163 struct gpio_chip chip; 164 struct gpio_regs *gpio_grp; 165 }; 166 167 static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio( 168 struct gpio_chip *gpc) 169 { 170 return container_of(gpc, struct lpc32xx_gpio_chip, chip); 171 } 172 173 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, 174 unsigned pin, int input) 175 { 176 if (input) 177 __raw_writel(GPIO012_PIN_TO_BIT(pin), 178 group->gpio_grp->dir_clr); 179 else 180 __raw_writel(GPIO012_PIN_TO_BIT(pin), 181 group->gpio_grp->dir_set); 182 } 183 184 static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, 185 unsigned pin, int input) 186 { 187 u32 u = GPIO3_PIN_TO_BIT(pin); 188 189 if (input) 190 __raw_writel(u, group->gpio_grp->dir_clr); 191 else 192 __raw_writel(u, group->gpio_grp->dir_set); 193 } 194 195 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, 196 unsigned pin, int high) 197 { 198 if (high) 199 __raw_writel(GPIO012_PIN_TO_BIT(pin), 200 group->gpio_grp->outp_set); 201 else 202 __raw_writel(GPIO012_PIN_TO_BIT(pin), 203 group->gpio_grp->outp_clr); 204 } 205 206 static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, 207 unsigned pin, int high) 208 { 209 u32 u = GPIO3_PIN_TO_BIT(pin); 210 211 if (high) 212 __raw_writel(u, group->gpio_grp->outp_set); 213 else 214 __raw_writel(u, group->gpio_grp->outp_clr); 215 } 216 217 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, 218 unsigned pin, int high) 219 { 220 if (high) 221 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); 222 else 223 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); 224 } 225 226 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, 227 unsigned pin) 228 { 229 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), 230 pin); 231 } 232 233 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, 234 unsigned pin) 235 { 236 int state = __raw_readl(group->gpio_grp->inp_state); 237 238 /* 239 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped 240 * to bits 10..14, while GPIOP3-5 is mapped to bit 24. 241 */ 242 return GPIO3_PIN_IN_SEL(state, pin); 243 } 244 245 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, 246 unsigned pin) 247 { 248 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); 249 } 250 251 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, 252 unsigned pin) 253 { 254 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); 255 } 256 257 /* 258 * GENERIC_GPIO primitives. 259 */ 260 static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip, 261 unsigned pin) 262 { 263 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 264 265 __set_gpio_dir_p012(group, pin, 1); 266 267 return 0; 268 } 269 270 static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip, 271 unsigned pin) 272 { 273 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 274 275 __set_gpio_dir_p3(group, pin, 1); 276 277 return 0; 278 } 279 280 static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip, 281 unsigned pin) 282 { 283 return 0; 284 } 285 286 static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin) 287 { 288 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 289 290 return __get_gpio_state_p012(group, pin); 291 } 292 293 static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin) 294 { 295 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 296 297 return __get_gpio_state_p3(group, pin); 298 } 299 300 static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin) 301 { 302 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 303 304 return __get_gpi_state_p3(group, pin); 305 } 306 307 static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin, 308 int value) 309 { 310 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 311 312 __set_gpio_dir_p012(group, pin, 0); 313 314 return 0; 315 } 316 317 static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin, 318 int value) 319 { 320 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 321 322 __set_gpio_dir_p3(group, pin, 0); 323 324 return 0; 325 } 326 327 static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin, 328 int value) 329 { 330 return 0; 331 } 332 333 static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin, 334 int value) 335 { 336 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 337 338 __set_gpio_level_p012(group, pin, value); 339 } 340 341 static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin, 342 int value) 343 { 344 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 345 346 __set_gpio_level_p3(group, pin, value); 347 } 348 349 static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin, 350 int value) 351 { 352 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 353 354 __set_gpo_level_p3(group, pin, value); 355 } 356 357 static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin) 358 { 359 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 360 361 return __get_gpo_state_p3(group, pin); 362 } 363 364 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) 365 { 366 if (pin < chip->ngpio) 367 return 0; 368 369 return -EINVAL; 370 } 371 372 static int lpc32xx_gpio_to_irq_p01(struct gpio_chip *chip, unsigned offset) 373 { 374 return IRQ_LPC32XX_P0_P1_IRQ; 375 } 376 377 static const char lpc32xx_gpio_to_irq_gpio_p3_table[] = { 378 IRQ_LPC32XX_GPIO_00, 379 IRQ_LPC32XX_GPIO_01, 380 IRQ_LPC32XX_GPIO_02, 381 IRQ_LPC32XX_GPIO_03, 382 IRQ_LPC32XX_GPIO_04, 383 IRQ_LPC32XX_GPIO_05, 384 }; 385 386 static int lpc32xx_gpio_to_irq_gpio_p3(struct gpio_chip *chip, unsigned offset) 387 { 388 if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpio_p3_table)) 389 return lpc32xx_gpio_to_irq_gpio_p3_table[offset]; 390 return -ENXIO; 391 } 392 393 static const char lpc32xx_gpio_to_irq_gpi_p3_table[] = { 394 IRQ_LPC32XX_GPI_00, 395 IRQ_LPC32XX_GPI_01, 396 IRQ_LPC32XX_GPI_02, 397 IRQ_LPC32XX_GPI_03, 398 IRQ_LPC32XX_GPI_04, 399 IRQ_LPC32XX_GPI_05, 400 IRQ_LPC32XX_GPI_06, 401 IRQ_LPC32XX_GPI_07, 402 IRQ_LPC32XX_GPI_08, 403 IRQ_LPC32XX_GPI_09, 404 -ENXIO, /* 10 */ 405 -ENXIO, /* 11 */ 406 -ENXIO, /* 12 */ 407 -ENXIO, /* 13 */ 408 -ENXIO, /* 14 */ 409 -ENXIO, /* 15 */ 410 -ENXIO, /* 16 */ 411 -ENXIO, /* 17 */ 412 -ENXIO, /* 18 */ 413 IRQ_LPC32XX_GPI_19, 414 -ENXIO, /* 20 */ 415 -ENXIO, /* 21 */ 416 -ENXIO, /* 22 */ 417 -ENXIO, /* 23 */ 418 -ENXIO, /* 24 */ 419 -ENXIO, /* 25 */ 420 -ENXIO, /* 26 */ 421 -ENXIO, /* 27 */ 422 IRQ_LPC32XX_GPI_28, 423 }; 424 425 static int lpc32xx_gpio_to_irq_gpi_p3(struct gpio_chip *chip, unsigned offset) 426 { 427 if (offset < ARRAY_SIZE(lpc32xx_gpio_to_irq_gpi_p3_table)) 428 return lpc32xx_gpio_to_irq_gpi_p3_table[offset]; 429 return -ENXIO; 430 } 431 432 static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = { 433 { 434 .chip = { 435 .label = "gpio_p0", 436 .direction_input = lpc32xx_gpio_dir_input_p012, 437 .get = lpc32xx_gpio_get_value_p012, 438 .direction_output = lpc32xx_gpio_dir_output_p012, 439 .set = lpc32xx_gpio_set_value_p012, 440 .request = lpc32xx_gpio_request, 441 .to_irq = lpc32xx_gpio_to_irq_p01, 442 .base = LPC32XX_GPIO_P0_GRP, 443 .ngpio = LPC32XX_GPIO_P0_MAX, 444 .names = gpio_p0_names, 445 .can_sleep = 0, 446 }, 447 .gpio_grp = &gpio_grp_regs_p0, 448 }, 449 { 450 .chip = { 451 .label = "gpio_p1", 452 .direction_input = lpc32xx_gpio_dir_input_p012, 453 .get = lpc32xx_gpio_get_value_p012, 454 .direction_output = lpc32xx_gpio_dir_output_p012, 455 .set = lpc32xx_gpio_set_value_p012, 456 .request = lpc32xx_gpio_request, 457 .to_irq = lpc32xx_gpio_to_irq_p01, 458 .base = LPC32XX_GPIO_P1_GRP, 459 .ngpio = LPC32XX_GPIO_P1_MAX, 460 .names = gpio_p1_names, 461 .can_sleep = 0, 462 }, 463 .gpio_grp = &gpio_grp_regs_p1, 464 }, 465 { 466 .chip = { 467 .label = "gpio_p2", 468 .direction_input = lpc32xx_gpio_dir_input_p012, 469 .get = lpc32xx_gpio_get_value_p012, 470 .direction_output = lpc32xx_gpio_dir_output_p012, 471 .set = lpc32xx_gpio_set_value_p012, 472 .request = lpc32xx_gpio_request, 473 .base = LPC32XX_GPIO_P2_GRP, 474 .ngpio = LPC32XX_GPIO_P2_MAX, 475 .names = gpio_p2_names, 476 .can_sleep = 0, 477 }, 478 .gpio_grp = &gpio_grp_regs_p2, 479 }, 480 { 481 .chip = { 482 .label = "gpio_p3", 483 .direction_input = lpc32xx_gpio_dir_input_p3, 484 .get = lpc32xx_gpio_get_value_p3, 485 .direction_output = lpc32xx_gpio_dir_output_p3, 486 .set = lpc32xx_gpio_set_value_p3, 487 .request = lpc32xx_gpio_request, 488 .to_irq = lpc32xx_gpio_to_irq_gpio_p3, 489 .base = LPC32XX_GPIO_P3_GRP, 490 .ngpio = LPC32XX_GPIO_P3_MAX, 491 .names = gpio_p3_names, 492 .can_sleep = 0, 493 }, 494 .gpio_grp = &gpio_grp_regs_p3, 495 }, 496 { 497 .chip = { 498 .label = "gpi_p3", 499 .direction_input = lpc32xx_gpio_dir_in_always, 500 .get = lpc32xx_gpi_get_value, 501 .request = lpc32xx_gpio_request, 502 .to_irq = lpc32xx_gpio_to_irq_gpi_p3, 503 .base = LPC32XX_GPI_P3_GRP, 504 .ngpio = LPC32XX_GPI_P3_MAX, 505 .names = gpi_p3_names, 506 .can_sleep = 0, 507 }, 508 .gpio_grp = &gpio_grp_regs_p3, 509 }, 510 { 511 .chip = { 512 .label = "gpo_p3", 513 .direction_output = lpc32xx_gpio_dir_out_always, 514 .set = lpc32xx_gpo_set_value, 515 .get = lpc32xx_gpo_get_value, 516 .request = lpc32xx_gpio_request, 517 .base = LPC32XX_GPO_P3_GRP, 518 .ngpio = LPC32XX_GPO_P3_MAX, 519 .names = gpo_p3_names, 520 .can_sleep = 0, 521 }, 522 .gpio_grp = &gpio_grp_regs_p3, 523 }, 524 }; 525 526 static int lpc32xx_of_xlate(struct gpio_chip *gc, 527 const struct of_phandle_args *gpiospec, u32 *flags) 528 { 529 /* Is this the correct bank? */ 530 u32 bank = gpiospec->args[0]; 531 if ((bank > ARRAY_SIZE(lpc32xx_gpiochip) || 532 (gc != &lpc32xx_gpiochip[bank].chip))) 533 return -EINVAL; 534 535 if (flags) 536 *flags = gpiospec->args[2]; 537 return gpiospec->args[1]; 538 } 539 540 static int __devinit lpc32xx_gpio_probe(struct platform_device *pdev) 541 { 542 int i; 543 544 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) { 545 if (pdev->dev.of_node) { 546 lpc32xx_gpiochip[i].chip.of_xlate = lpc32xx_of_xlate; 547 lpc32xx_gpiochip[i].chip.of_gpio_n_cells = 3; 548 lpc32xx_gpiochip[i].chip.of_node = pdev->dev.of_node; 549 } 550 gpiochip_add(&lpc32xx_gpiochip[i].chip); 551 } 552 553 return 0; 554 } 555 556 #ifdef CONFIG_OF 557 static struct of_device_id lpc32xx_gpio_of_match[] __devinitdata = { 558 { .compatible = "nxp,lpc3220-gpio", }, 559 { }, 560 }; 561 #endif 562 563 static struct platform_driver lpc32xx_gpio_driver = { 564 .driver = { 565 .name = "lpc32xx-gpio", 566 .owner = THIS_MODULE, 567 .of_match_table = of_match_ptr(lpc32xx_gpio_of_match), 568 }, 569 .probe = lpc32xx_gpio_probe, 570 }; 571 572 module_platform_driver(lpc32xx_gpio_driver); 573