1 /* 2 * arch/arm/mach-lpc32xx/gpiolib.c 3 * 4 * Author: Kevin Wells <kevin.wells@nxp.com> 5 * 6 * Copyright (C) 2010 NXP Semiconductors 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/io.h> 22 #include <linux/errno.h> 23 #include <linux/gpio.h> 24 25 #include <mach/hardware.h> 26 #include <mach/platform.h> 27 #include <mach/gpio-lpc32xx.h> 28 29 #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) 30 #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) 31 #define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) 32 #define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) 33 #define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) 34 #define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) 35 #define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) 36 #define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) 37 #define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) 38 #define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) 39 #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) 40 #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) 41 #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) 42 #define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) 43 #define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) 44 #define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) 45 #define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) 46 #define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) 47 #define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) 48 #define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) 49 #define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) 50 #define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) 51 #define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) 52 #define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) 53 #define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) 54 #define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) 55 #define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) 56 57 #define GPIO012_PIN_TO_BIT(x) (1 << (x)) 58 #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) 59 #define GPO3_PIN_TO_BIT(x) (1 << (x)) 60 #define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 61 #define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x)) 62 #define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1) 63 #define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1) 64 #define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 65 #define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 66 67 struct gpio_regs { 68 void __iomem *inp_state; 69 void __iomem *outp_state; 70 void __iomem *outp_set; 71 void __iomem *outp_clr; 72 void __iomem *dir_set; 73 void __iomem *dir_clr; 74 }; 75 76 /* 77 * GPIO names 78 */ 79 static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = { 80 "p0.0", "p0.1", "p0.2", "p0.3", 81 "p0.4", "p0.5", "p0.6", "p0.7" 82 }; 83 84 static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = { 85 "p1.0", "p1.1", "p1.2", "p1.3", 86 "p1.4", "p1.5", "p1.6", "p1.7", 87 "p1.8", "p1.9", "p1.10", "p1.11", 88 "p1.12", "p1.13", "p1.14", "p1.15", 89 "p1.16", "p1.17", "p1.18", "p1.19", 90 "p1.20", "p1.21", "p1.22", "p1.23", 91 }; 92 93 static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = { 94 "p2.0", "p2.1", "p2.2", "p2.3", 95 "p2.4", "p2.5", "p2.6", "p2.7", 96 "p2.8", "p2.9", "p2.10", "p2.11", 97 "p2.12" 98 }; 99 100 static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = { 101 "gpio00", "gpio01", "gpio02", "gpio03", 102 "gpio04", "gpio05" 103 }; 104 105 static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = { 106 "gpi00", "gpi01", "gpi02", "gpi03", 107 "gpi04", "gpi05", "gpi06", "gpi07", 108 "gpi08", "gpi09", NULL, NULL, 109 NULL, NULL, NULL, "gpi15", 110 "gpi16", "gpi17", "gpi18", "gpi19", 111 "gpi20", "gpi21", "gpi22", "gpi23", 112 "gpi24", "gpi25", "gpi26", "gpi27" 113 }; 114 115 static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = { 116 "gpo00", "gpo01", "gpo02", "gpo03", 117 "gpo04", "gpo05", "gpo06", "gpo07", 118 "gpo08", "gpo09", "gpo10", "gpo11", 119 "gpo12", "gpo13", "gpo14", "gpo15", 120 "gpo16", "gpo17", "gpo18", "gpo19", 121 "gpo20", "gpo21", "gpo22", "gpo23" 122 }; 123 124 static struct gpio_regs gpio_grp_regs_p0 = { 125 .inp_state = LPC32XX_GPIO_P0_INP_STATE, 126 .outp_set = LPC32XX_GPIO_P0_OUTP_SET, 127 .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR, 128 .dir_set = LPC32XX_GPIO_P0_DIR_SET, 129 .dir_clr = LPC32XX_GPIO_P0_DIR_CLR, 130 }; 131 132 static struct gpio_regs gpio_grp_regs_p1 = { 133 .inp_state = LPC32XX_GPIO_P1_INP_STATE, 134 .outp_set = LPC32XX_GPIO_P1_OUTP_SET, 135 .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR, 136 .dir_set = LPC32XX_GPIO_P1_DIR_SET, 137 .dir_clr = LPC32XX_GPIO_P1_DIR_CLR, 138 }; 139 140 static struct gpio_regs gpio_grp_regs_p2 = { 141 .inp_state = LPC32XX_GPIO_P2_INP_STATE, 142 .outp_set = LPC32XX_GPIO_P2_OUTP_SET, 143 .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR, 144 .dir_set = LPC32XX_GPIO_P2_DIR_SET, 145 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, 146 }; 147 148 static struct gpio_regs gpio_grp_regs_p3 = { 149 .inp_state = LPC32XX_GPIO_P3_INP_STATE, 150 .outp_state = LPC32XX_GPIO_P3_OUTP_STATE, 151 .outp_set = LPC32XX_GPIO_P3_OUTP_SET, 152 .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR, 153 .dir_set = LPC32XX_GPIO_P2_DIR_SET, 154 .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, 155 }; 156 157 struct lpc32xx_gpio_chip { 158 struct gpio_chip chip; 159 struct gpio_regs *gpio_grp; 160 }; 161 162 static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio( 163 struct gpio_chip *gpc) 164 { 165 return container_of(gpc, struct lpc32xx_gpio_chip, chip); 166 } 167 168 static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, 169 unsigned pin, int input) 170 { 171 if (input) 172 __raw_writel(GPIO012_PIN_TO_BIT(pin), 173 group->gpio_grp->dir_clr); 174 else 175 __raw_writel(GPIO012_PIN_TO_BIT(pin), 176 group->gpio_grp->dir_set); 177 } 178 179 static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, 180 unsigned pin, int input) 181 { 182 u32 u = GPIO3_PIN_TO_BIT(pin); 183 184 if (input) 185 __raw_writel(u, group->gpio_grp->dir_clr); 186 else 187 __raw_writel(u, group->gpio_grp->dir_set); 188 } 189 190 static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, 191 unsigned pin, int high) 192 { 193 if (high) 194 __raw_writel(GPIO012_PIN_TO_BIT(pin), 195 group->gpio_grp->outp_set); 196 else 197 __raw_writel(GPIO012_PIN_TO_BIT(pin), 198 group->gpio_grp->outp_clr); 199 } 200 201 static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, 202 unsigned pin, int high) 203 { 204 u32 u = GPIO3_PIN_TO_BIT(pin); 205 206 if (high) 207 __raw_writel(u, group->gpio_grp->outp_set); 208 else 209 __raw_writel(u, group->gpio_grp->outp_clr); 210 } 211 212 static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, 213 unsigned pin, int high) 214 { 215 if (high) 216 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); 217 else 218 __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); 219 } 220 221 static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, 222 unsigned pin) 223 { 224 return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), 225 pin); 226 } 227 228 static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, 229 unsigned pin) 230 { 231 int state = __raw_readl(group->gpio_grp->inp_state); 232 233 /* 234 * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped 235 * to bits 10..14, while GPIOP3-5 is mapped to bit 24. 236 */ 237 return GPIO3_PIN_IN_SEL(state, pin); 238 } 239 240 static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, 241 unsigned pin) 242 { 243 return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); 244 } 245 246 static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, 247 unsigned pin) 248 { 249 return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); 250 } 251 252 /* 253 * GENERIC_GPIO primitives. 254 */ 255 static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip, 256 unsigned pin) 257 { 258 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 259 260 __set_gpio_dir_p012(group, pin, 1); 261 262 return 0; 263 } 264 265 static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip, 266 unsigned pin) 267 { 268 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 269 270 __set_gpio_dir_p3(group, pin, 1); 271 272 return 0; 273 } 274 275 static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip, 276 unsigned pin) 277 { 278 return 0; 279 } 280 281 static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin) 282 { 283 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 284 285 return __get_gpio_state_p012(group, pin); 286 } 287 288 static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin) 289 { 290 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 291 292 return __get_gpio_state_p3(group, pin); 293 } 294 295 static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin) 296 { 297 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 298 299 return __get_gpi_state_p3(group, pin); 300 } 301 302 static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin, 303 int value) 304 { 305 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 306 307 __set_gpio_dir_p012(group, pin, 0); 308 309 return 0; 310 } 311 312 static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin, 313 int value) 314 { 315 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 316 317 __set_gpio_dir_p3(group, pin, 0); 318 319 return 0; 320 } 321 322 static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin, 323 int value) 324 { 325 return 0; 326 } 327 328 static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin, 329 int value) 330 { 331 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 332 333 __set_gpio_level_p012(group, pin, value); 334 } 335 336 static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin, 337 int value) 338 { 339 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 340 341 __set_gpio_level_p3(group, pin, value); 342 } 343 344 static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin, 345 int value) 346 { 347 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 348 349 __set_gpo_level_p3(group, pin, value); 350 } 351 352 static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin) 353 { 354 struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 355 356 return __get_gpo_state_p3(group, pin); 357 } 358 359 static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) 360 { 361 if (pin < chip->ngpio) 362 return 0; 363 364 return -EINVAL; 365 } 366 367 static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = { 368 { 369 .chip = { 370 .label = "gpio_p0", 371 .direction_input = lpc32xx_gpio_dir_input_p012, 372 .get = lpc32xx_gpio_get_value_p012, 373 .direction_output = lpc32xx_gpio_dir_output_p012, 374 .set = lpc32xx_gpio_set_value_p012, 375 .request = lpc32xx_gpio_request, 376 .base = LPC32XX_GPIO_P0_GRP, 377 .ngpio = LPC32XX_GPIO_P0_MAX, 378 .names = gpio_p0_names, 379 .can_sleep = 0, 380 }, 381 .gpio_grp = &gpio_grp_regs_p0, 382 }, 383 { 384 .chip = { 385 .label = "gpio_p1", 386 .direction_input = lpc32xx_gpio_dir_input_p012, 387 .get = lpc32xx_gpio_get_value_p012, 388 .direction_output = lpc32xx_gpio_dir_output_p012, 389 .set = lpc32xx_gpio_set_value_p012, 390 .request = lpc32xx_gpio_request, 391 .base = LPC32XX_GPIO_P1_GRP, 392 .ngpio = LPC32XX_GPIO_P1_MAX, 393 .names = gpio_p1_names, 394 .can_sleep = 0, 395 }, 396 .gpio_grp = &gpio_grp_regs_p1, 397 }, 398 { 399 .chip = { 400 .label = "gpio_p2", 401 .direction_input = lpc32xx_gpio_dir_input_p012, 402 .get = lpc32xx_gpio_get_value_p012, 403 .direction_output = lpc32xx_gpio_dir_output_p012, 404 .set = lpc32xx_gpio_set_value_p012, 405 .request = lpc32xx_gpio_request, 406 .base = LPC32XX_GPIO_P2_GRP, 407 .ngpio = LPC32XX_GPIO_P2_MAX, 408 .names = gpio_p2_names, 409 .can_sleep = 0, 410 }, 411 .gpio_grp = &gpio_grp_regs_p2, 412 }, 413 { 414 .chip = { 415 .label = "gpio_p3", 416 .direction_input = lpc32xx_gpio_dir_input_p3, 417 .get = lpc32xx_gpio_get_value_p3, 418 .direction_output = lpc32xx_gpio_dir_output_p3, 419 .set = lpc32xx_gpio_set_value_p3, 420 .request = lpc32xx_gpio_request, 421 .base = LPC32XX_GPIO_P3_GRP, 422 .ngpio = LPC32XX_GPIO_P3_MAX, 423 .names = gpio_p3_names, 424 .can_sleep = 0, 425 }, 426 .gpio_grp = &gpio_grp_regs_p3, 427 }, 428 { 429 .chip = { 430 .label = "gpi_p3", 431 .direction_input = lpc32xx_gpio_dir_in_always, 432 .get = lpc32xx_gpi_get_value, 433 .request = lpc32xx_gpio_request, 434 .base = LPC32XX_GPI_P3_GRP, 435 .ngpio = LPC32XX_GPI_P3_MAX, 436 .names = gpi_p3_names, 437 .can_sleep = 0, 438 }, 439 .gpio_grp = &gpio_grp_regs_p3, 440 }, 441 { 442 .chip = { 443 .label = "gpo_p3", 444 .direction_output = lpc32xx_gpio_dir_out_always, 445 .set = lpc32xx_gpo_set_value, 446 .get = lpc32xx_gpo_get_value, 447 .request = lpc32xx_gpio_request, 448 .base = LPC32XX_GPO_P3_GRP, 449 .ngpio = LPC32XX_GPO_P3_MAX, 450 .names = gpo_p3_names, 451 .can_sleep = 0, 452 }, 453 .gpio_grp = &gpio_grp_regs_p3, 454 }, 455 }; 456 457 void __init lpc32xx_gpio_init(void) 458 { 459 int i; 460 461 for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) 462 gpiochip_add(&lpc32xx_gpiochip[i].chip); 463 } 464