1f80cb526SLinus Walleij /* 2f80cb526SLinus Walleij * arch/arm/mach-lpc32xx/gpiolib.c 3f80cb526SLinus Walleij * 4f80cb526SLinus Walleij * Author: Kevin Wells <kevin.wells@nxp.com> 5f80cb526SLinus Walleij * 6f80cb526SLinus Walleij * Copyright (C) 2010 NXP Semiconductors 7f80cb526SLinus Walleij * 8f80cb526SLinus Walleij * This program is free software; you can redistribute it and/or modify 9f80cb526SLinus Walleij * it under the terms of the GNU General Public License as published by 10f80cb526SLinus Walleij * the Free Software Foundation; either version 2 of the License, or 11f80cb526SLinus Walleij * (at your option) any later version. 12f80cb526SLinus Walleij * 13f80cb526SLinus Walleij * This program is distributed in the hope that it will be useful, 14f80cb526SLinus Walleij * but WITHOUT ANY WARRANTY; without even the implied warranty of 15f80cb526SLinus Walleij * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16f80cb526SLinus Walleij * GNU General Public License for more details. 17f80cb526SLinus Walleij */ 18f80cb526SLinus Walleij 19f80cb526SLinus Walleij #include <linux/kernel.h> 20f80cb526SLinus Walleij #include <linux/init.h> 21f80cb526SLinus Walleij #include <linux/io.h> 22f80cb526SLinus Walleij #include <linux/errno.h> 23f80cb526SLinus Walleij #include <linux/gpio.h> 24f80cb526SLinus Walleij 25f80cb526SLinus Walleij #include <mach/hardware.h> 26f80cb526SLinus Walleij #include <mach/platform.h> 279c587c05SLinus Walleij #include <mach/gpio-lpc32xx.h> 28f80cb526SLinus Walleij 29f80cb526SLinus Walleij #define LPC32XX_GPIO_P3_INP_STATE _GPREG(0x000) 30f80cb526SLinus Walleij #define LPC32XX_GPIO_P3_OUTP_SET _GPREG(0x004) 31f80cb526SLinus Walleij #define LPC32XX_GPIO_P3_OUTP_CLR _GPREG(0x008) 32f80cb526SLinus Walleij #define LPC32XX_GPIO_P3_OUTP_STATE _GPREG(0x00C) 33f80cb526SLinus Walleij #define LPC32XX_GPIO_P2_DIR_SET _GPREG(0x010) 34f80cb526SLinus Walleij #define LPC32XX_GPIO_P2_DIR_CLR _GPREG(0x014) 35f80cb526SLinus Walleij #define LPC32XX_GPIO_P2_DIR_STATE _GPREG(0x018) 36f80cb526SLinus Walleij #define LPC32XX_GPIO_P2_INP_STATE _GPREG(0x01C) 37f80cb526SLinus Walleij #define LPC32XX_GPIO_P2_OUTP_SET _GPREG(0x020) 38f80cb526SLinus Walleij #define LPC32XX_GPIO_P2_OUTP_CLR _GPREG(0x024) 39f80cb526SLinus Walleij #define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028) 40f80cb526SLinus Walleij #define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C) 41f80cb526SLinus Walleij #define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030) 42f80cb526SLinus Walleij #define LPC32XX_GPIO_P0_INP_STATE _GPREG(0x040) 43f80cb526SLinus Walleij #define LPC32XX_GPIO_P0_OUTP_SET _GPREG(0x044) 44f80cb526SLinus Walleij #define LPC32XX_GPIO_P0_OUTP_CLR _GPREG(0x048) 45f80cb526SLinus Walleij #define LPC32XX_GPIO_P0_OUTP_STATE _GPREG(0x04C) 46f80cb526SLinus Walleij #define LPC32XX_GPIO_P0_DIR_SET _GPREG(0x050) 47f80cb526SLinus Walleij #define LPC32XX_GPIO_P0_DIR_CLR _GPREG(0x054) 48f80cb526SLinus Walleij #define LPC32XX_GPIO_P0_DIR_STATE _GPREG(0x058) 49f80cb526SLinus Walleij #define LPC32XX_GPIO_P1_INP_STATE _GPREG(0x060) 50f80cb526SLinus Walleij #define LPC32XX_GPIO_P1_OUTP_SET _GPREG(0x064) 51f80cb526SLinus Walleij #define LPC32XX_GPIO_P1_OUTP_CLR _GPREG(0x068) 52f80cb526SLinus Walleij #define LPC32XX_GPIO_P1_OUTP_STATE _GPREG(0x06C) 53f80cb526SLinus Walleij #define LPC32XX_GPIO_P1_DIR_SET _GPREG(0x070) 54f80cb526SLinus Walleij #define LPC32XX_GPIO_P1_DIR_CLR _GPREG(0x074) 55f80cb526SLinus Walleij #define LPC32XX_GPIO_P1_DIR_STATE _GPREG(0x078) 56f80cb526SLinus Walleij 57f80cb526SLinus Walleij #define GPIO012_PIN_TO_BIT(x) (1 << (x)) 58f80cb526SLinus Walleij #define GPIO3_PIN_TO_BIT(x) (1 << ((x) + 25)) 59f80cb526SLinus Walleij #define GPO3_PIN_TO_BIT(x) (1 << (x)) 60f80cb526SLinus Walleij #define GPIO012_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 61f80cb526SLinus Walleij #define GPIO3_PIN_IN_SHIFT(x) ((x) == 5 ? 24 : 10 + (x)) 628e5fb37bSRoland Stigge #define GPIO3_PIN_IN_SEL(x, y) (((x) >> GPIO3_PIN_IN_SHIFT(y)) & 1) 63f80cb526SLinus Walleij #define GPIO3_PIN5_IN_SEL(x) (((x) >> 24) & 1) 64f80cb526SLinus Walleij #define GPI3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 6546158aadSRoland Stigge #define GPO3_PIN_IN_SEL(x, y) (((x) >> (y)) & 1) 66f80cb526SLinus Walleij 67f80cb526SLinus Walleij struct gpio_regs { 68f80cb526SLinus Walleij void __iomem *inp_state; 6946158aadSRoland Stigge void __iomem *outp_state; 70f80cb526SLinus Walleij void __iomem *outp_set; 71f80cb526SLinus Walleij void __iomem *outp_clr; 72f80cb526SLinus Walleij void __iomem *dir_set; 73f80cb526SLinus Walleij void __iomem *dir_clr; 74f80cb526SLinus Walleij }; 75f80cb526SLinus Walleij 76f80cb526SLinus Walleij /* 77f80cb526SLinus Walleij * GPIO names 78f80cb526SLinus Walleij */ 79f80cb526SLinus Walleij static const char *gpio_p0_names[LPC32XX_GPIO_P0_MAX] = { 80f80cb526SLinus Walleij "p0.0", "p0.1", "p0.2", "p0.3", 81f80cb526SLinus Walleij "p0.4", "p0.5", "p0.6", "p0.7" 82f80cb526SLinus Walleij }; 83f80cb526SLinus Walleij 84f80cb526SLinus Walleij static const char *gpio_p1_names[LPC32XX_GPIO_P1_MAX] = { 85f80cb526SLinus Walleij "p1.0", "p1.1", "p1.2", "p1.3", 86f80cb526SLinus Walleij "p1.4", "p1.5", "p1.6", "p1.7", 87f80cb526SLinus Walleij "p1.8", "p1.9", "p1.10", "p1.11", 88f80cb526SLinus Walleij "p1.12", "p1.13", "p1.14", "p1.15", 89f80cb526SLinus Walleij "p1.16", "p1.17", "p1.18", "p1.19", 90f80cb526SLinus Walleij "p1.20", "p1.21", "p1.22", "p1.23", 91f80cb526SLinus Walleij }; 92f80cb526SLinus Walleij 93f80cb526SLinus Walleij static const char *gpio_p2_names[LPC32XX_GPIO_P2_MAX] = { 94f80cb526SLinus Walleij "p2.0", "p2.1", "p2.2", "p2.3", 95f80cb526SLinus Walleij "p2.4", "p2.5", "p2.6", "p2.7", 96f80cb526SLinus Walleij "p2.8", "p2.9", "p2.10", "p2.11", 97f80cb526SLinus Walleij "p2.12" 98f80cb526SLinus Walleij }; 99f80cb526SLinus Walleij 100f80cb526SLinus Walleij static const char *gpio_p3_names[LPC32XX_GPIO_P3_MAX] = { 10195120d5dSRoland Stigge "gpio00", "gpio01", "gpio02", "gpio03", 102f80cb526SLinus Walleij "gpio04", "gpio05" 103f80cb526SLinus Walleij }; 104f80cb526SLinus Walleij 105f80cb526SLinus Walleij static const char *gpi_p3_names[LPC32XX_GPI_P3_MAX] = { 106f80cb526SLinus Walleij "gpi00", "gpi01", "gpi02", "gpi03", 107f80cb526SLinus Walleij "gpi04", "gpi05", "gpi06", "gpi07", 108f80cb526SLinus Walleij "gpi08", "gpi09", NULL, NULL, 109f80cb526SLinus Walleij NULL, NULL, NULL, "gpi15", 110f80cb526SLinus Walleij "gpi16", "gpi17", "gpi18", "gpi19", 111f80cb526SLinus Walleij "gpi20", "gpi21", "gpi22", "gpi23", 112f80cb526SLinus Walleij "gpi24", "gpi25", "gpi26", "gpi27" 113f80cb526SLinus Walleij }; 114f80cb526SLinus Walleij 115f80cb526SLinus Walleij static const char *gpo_p3_names[LPC32XX_GPO_P3_MAX] = { 116f80cb526SLinus Walleij "gpo00", "gpo01", "gpo02", "gpo03", 117f80cb526SLinus Walleij "gpo04", "gpo05", "gpo06", "gpo07", 118f80cb526SLinus Walleij "gpo08", "gpo09", "gpo10", "gpo11", 119f80cb526SLinus Walleij "gpo12", "gpo13", "gpo14", "gpo15", 120f80cb526SLinus Walleij "gpo16", "gpo17", "gpo18", "gpo19", 121f80cb526SLinus Walleij "gpo20", "gpo21", "gpo22", "gpo23" 122f80cb526SLinus Walleij }; 123f80cb526SLinus Walleij 124f80cb526SLinus Walleij static struct gpio_regs gpio_grp_regs_p0 = { 125f80cb526SLinus Walleij .inp_state = LPC32XX_GPIO_P0_INP_STATE, 126f80cb526SLinus Walleij .outp_set = LPC32XX_GPIO_P0_OUTP_SET, 127f80cb526SLinus Walleij .outp_clr = LPC32XX_GPIO_P0_OUTP_CLR, 128f80cb526SLinus Walleij .dir_set = LPC32XX_GPIO_P0_DIR_SET, 129f80cb526SLinus Walleij .dir_clr = LPC32XX_GPIO_P0_DIR_CLR, 130f80cb526SLinus Walleij }; 131f80cb526SLinus Walleij 132f80cb526SLinus Walleij static struct gpio_regs gpio_grp_regs_p1 = { 133f80cb526SLinus Walleij .inp_state = LPC32XX_GPIO_P1_INP_STATE, 134f80cb526SLinus Walleij .outp_set = LPC32XX_GPIO_P1_OUTP_SET, 135f80cb526SLinus Walleij .outp_clr = LPC32XX_GPIO_P1_OUTP_CLR, 136f80cb526SLinus Walleij .dir_set = LPC32XX_GPIO_P1_DIR_SET, 137f80cb526SLinus Walleij .dir_clr = LPC32XX_GPIO_P1_DIR_CLR, 138f80cb526SLinus Walleij }; 139f80cb526SLinus Walleij 140f80cb526SLinus Walleij static struct gpio_regs gpio_grp_regs_p2 = { 141f80cb526SLinus Walleij .inp_state = LPC32XX_GPIO_P2_INP_STATE, 142f80cb526SLinus Walleij .outp_set = LPC32XX_GPIO_P2_OUTP_SET, 143f80cb526SLinus Walleij .outp_clr = LPC32XX_GPIO_P2_OUTP_CLR, 144f80cb526SLinus Walleij .dir_set = LPC32XX_GPIO_P2_DIR_SET, 145f80cb526SLinus Walleij .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, 146f80cb526SLinus Walleij }; 147f80cb526SLinus Walleij 148f80cb526SLinus Walleij static struct gpio_regs gpio_grp_regs_p3 = { 149f80cb526SLinus Walleij .inp_state = LPC32XX_GPIO_P3_INP_STATE, 15046158aadSRoland Stigge .outp_state = LPC32XX_GPIO_P3_OUTP_STATE, 151f80cb526SLinus Walleij .outp_set = LPC32XX_GPIO_P3_OUTP_SET, 152f80cb526SLinus Walleij .outp_clr = LPC32XX_GPIO_P3_OUTP_CLR, 153f80cb526SLinus Walleij .dir_set = LPC32XX_GPIO_P2_DIR_SET, 154f80cb526SLinus Walleij .dir_clr = LPC32XX_GPIO_P2_DIR_CLR, 155f80cb526SLinus Walleij }; 156f80cb526SLinus Walleij 157f80cb526SLinus Walleij struct lpc32xx_gpio_chip { 158f80cb526SLinus Walleij struct gpio_chip chip; 159f80cb526SLinus Walleij struct gpio_regs *gpio_grp; 160f80cb526SLinus Walleij }; 161f80cb526SLinus Walleij 162f80cb526SLinus Walleij static inline struct lpc32xx_gpio_chip *to_lpc32xx_gpio( 163f80cb526SLinus Walleij struct gpio_chip *gpc) 164f80cb526SLinus Walleij { 165f80cb526SLinus Walleij return container_of(gpc, struct lpc32xx_gpio_chip, chip); 166f80cb526SLinus Walleij } 167f80cb526SLinus Walleij 168f80cb526SLinus Walleij static void __set_gpio_dir_p012(struct lpc32xx_gpio_chip *group, 169f80cb526SLinus Walleij unsigned pin, int input) 170f80cb526SLinus Walleij { 171f80cb526SLinus Walleij if (input) 172f80cb526SLinus Walleij __raw_writel(GPIO012_PIN_TO_BIT(pin), 173f80cb526SLinus Walleij group->gpio_grp->dir_clr); 174f80cb526SLinus Walleij else 175f80cb526SLinus Walleij __raw_writel(GPIO012_PIN_TO_BIT(pin), 176f80cb526SLinus Walleij group->gpio_grp->dir_set); 177f80cb526SLinus Walleij } 178f80cb526SLinus Walleij 179f80cb526SLinus Walleij static void __set_gpio_dir_p3(struct lpc32xx_gpio_chip *group, 180f80cb526SLinus Walleij unsigned pin, int input) 181f80cb526SLinus Walleij { 182f80cb526SLinus Walleij u32 u = GPIO3_PIN_TO_BIT(pin); 183f80cb526SLinus Walleij 184f80cb526SLinus Walleij if (input) 185f80cb526SLinus Walleij __raw_writel(u, group->gpio_grp->dir_clr); 186f80cb526SLinus Walleij else 187f80cb526SLinus Walleij __raw_writel(u, group->gpio_grp->dir_set); 188f80cb526SLinus Walleij } 189f80cb526SLinus Walleij 190f80cb526SLinus Walleij static void __set_gpio_level_p012(struct lpc32xx_gpio_chip *group, 191f80cb526SLinus Walleij unsigned pin, int high) 192f80cb526SLinus Walleij { 193f80cb526SLinus Walleij if (high) 194f80cb526SLinus Walleij __raw_writel(GPIO012_PIN_TO_BIT(pin), 195f80cb526SLinus Walleij group->gpio_grp->outp_set); 196f80cb526SLinus Walleij else 197f80cb526SLinus Walleij __raw_writel(GPIO012_PIN_TO_BIT(pin), 198f80cb526SLinus Walleij group->gpio_grp->outp_clr); 199f80cb526SLinus Walleij } 200f80cb526SLinus Walleij 201f80cb526SLinus Walleij static void __set_gpio_level_p3(struct lpc32xx_gpio_chip *group, 202f80cb526SLinus Walleij unsigned pin, int high) 203f80cb526SLinus Walleij { 204f80cb526SLinus Walleij u32 u = GPIO3_PIN_TO_BIT(pin); 205f80cb526SLinus Walleij 206f80cb526SLinus Walleij if (high) 207f80cb526SLinus Walleij __raw_writel(u, group->gpio_grp->outp_set); 208f80cb526SLinus Walleij else 209f80cb526SLinus Walleij __raw_writel(u, group->gpio_grp->outp_clr); 210f80cb526SLinus Walleij } 211f80cb526SLinus Walleij 212f80cb526SLinus Walleij static void __set_gpo_level_p3(struct lpc32xx_gpio_chip *group, 213f80cb526SLinus Walleij unsigned pin, int high) 214f80cb526SLinus Walleij { 215f80cb526SLinus Walleij if (high) 216f80cb526SLinus Walleij __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_set); 217f80cb526SLinus Walleij else 218f80cb526SLinus Walleij __raw_writel(GPO3_PIN_TO_BIT(pin), group->gpio_grp->outp_clr); 219f80cb526SLinus Walleij } 220f80cb526SLinus Walleij 221f80cb526SLinus Walleij static int __get_gpio_state_p012(struct lpc32xx_gpio_chip *group, 222f80cb526SLinus Walleij unsigned pin) 223f80cb526SLinus Walleij { 224f80cb526SLinus Walleij return GPIO012_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), 225f80cb526SLinus Walleij pin); 226f80cb526SLinus Walleij } 227f80cb526SLinus Walleij 228f80cb526SLinus Walleij static int __get_gpio_state_p3(struct lpc32xx_gpio_chip *group, 229f80cb526SLinus Walleij unsigned pin) 230f80cb526SLinus Walleij { 231f80cb526SLinus Walleij int state = __raw_readl(group->gpio_grp->inp_state); 232f80cb526SLinus Walleij 233f80cb526SLinus Walleij /* 234f80cb526SLinus Walleij * P3 GPIO pin input mapping is not contiguous, GPIOP3-0..4 is mapped 235f80cb526SLinus Walleij * to bits 10..14, while GPIOP3-5 is mapped to bit 24. 236f80cb526SLinus Walleij */ 237f80cb526SLinus Walleij return GPIO3_PIN_IN_SEL(state, pin); 238f80cb526SLinus Walleij } 239f80cb526SLinus Walleij 240f80cb526SLinus Walleij static int __get_gpi_state_p3(struct lpc32xx_gpio_chip *group, 241f80cb526SLinus Walleij unsigned pin) 242f80cb526SLinus Walleij { 243f80cb526SLinus Walleij return GPI3_PIN_IN_SEL(__raw_readl(group->gpio_grp->inp_state), pin); 244f80cb526SLinus Walleij } 245f80cb526SLinus Walleij 24646158aadSRoland Stigge static int __get_gpo_state_p3(struct lpc32xx_gpio_chip *group, 24746158aadSRoland Stigge unsigned pin) 24846158aadSRoland Stigge { 24946158aadSRoland Stigge return GPO3_PIN_IN_SEL(__raw_readl(group->gpio_grp->outp_state), pin); 25046158aadSRoland Stigge } 25146158aadSRoland Stigge 252f80cb526SLinus Walleij /* 253f80cb526SLinus Walleij * GENERIC_GPIO primitives. 254f80cb526SLinus Walleij */ 255f80cb526SLinus Walleij static int lpc32xx_gpio_dir_input_p012(struct gpio_chip *chip, 256f80cb526SLinus Walleij unsigned pin) 257f80cb526SLinus Walleij { 258f80cb526SLinus Walleij struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 259f80cb526SLinus Walleij 260f80cb526SLinus Walleij __set_gpio_dir_p012(group, pin, 1); 261f80cb526SLinus Walleij 262f80cb526SLinus Walleij return 0; 263f80cb526SLinus Walleij } 264f80cb526SLinus Walleij 265f80cb526SLinus Walleij static int lpc32xx_gpio_dir_input_p3(struct gpio_chip *chip, 266f80cb526SLinus Walleij unsigned pin) 267f80cb526SLinus Walleij { 268f80cb526SLinus Walleij struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 269f80cb526SLinus Walleij 270f80cb526SLinus Walleij __set_gpio_dir_p3(group, pin, 1); 271f80cb526SLinus Walleij 272f80cb526SLinus Walleij return 0; 273f80cb526SLinus Walleij } 274f80cb526SLinus Walleij 275f80cb526SLinus Walleij static int lpc32xx_gpio_dir_in_always(struct gpio_chip *chip, 276f80cb526SLinus Walleij unsigned pin) 277f80cb526SLinus Walleij { 278f80cb526SLinus Walleij return 0; 279f80cb526SLinus Walleij } 280f80cb526SLinus Walleij 281f80cb526SLinus Walleij static int lpc32xx_gpio_get_value_p012(struct gpio_chip *chip, unsigned pin) 282f80cb526SLinus Walleij { 283f80cb526SLinus Walleij struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 284f80cb526SLinus Walleij 285f80cb526SLinus Walleij return __get_gpio_state_p012(group, pin); 286f80cb526SLinus Walleij } 287f80cb526SLinus Walleij 288f80cb526SLinus Walleij static int lpc32xx_gpio_get_value_p3(struct gpio_chip *chip, unsigned pin) 289f80cb526SLinus Walleij { 290f80cb526SLinus Walleij struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 291f80cb526SLinus Walleij 292f80cb526SLinus Walleij return __get_gpio_state_p3(group, pin); 293f80cb526SLinus Walleij } 294f80cb526SLinus Walleij 295f80cb526SLinus Walleij static int lpc32xx_gpi_get_value(struct gpio_chip *chip, unsigned pin) 296f80cb526SLinus Walleij { 297f80cb526SLinus Walleij struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 298f80cb526SLinus Walleij 299f80cb526SLinus Walleij return __get_gpi_state_p3(group, pin); 300f80cb526SLinus Walleij } 301f80cb526SLinus Walleij 302f80cb526SLinus Walleij static int lpc32xx_gpio_dir_output_p012(struct gpio_chip *chip, unsigned pin, 303f80cb526SLinus Walleij int value) 304f80cb526SLinus Walleij { 305f80cb526SLinus Walleij struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 306f80cb526SLinus Walleij 307f80cb526SLinus Walleij __set_gpio_dir_p012(group, pin, 0); 308f80cb526SLinus Walleij 309f80cb526SLinus Walleij return 0; 310f80cb526SLinus Walleij } 311f80cb526SLinus Walleij 312f80cb526SLinus Walleij static int lpc32xx_gpio_dir_output_p3(struct gpio_chip *chip, unsigned pin, 313f80cb526SLinus Walleij int value) 314f80cb526SLinus Walleij { 315f80cb526SLinus Walleij struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 316f80cb526SLinus Walleij 317f80cb526SLinus Walleij __set_gpio_dir_p3(group, pin, 0); 318f80cb526SLinus Walleij 319f80cb526SLinus Walleij return 0; 320f80cb526SLinus Walleij } 321f80cb526SLinus Walleij 322f80cb526SLinus Walleij static int lpc32xx_gpio_dir_out_always(struct gpio_chip *chip, unsigned pin, 323f80cb526SLinus Walleij int value) 324f80cb526SLinus Walleij { 325f80cb526SLinus Walleij return 0; 326f80cb526SLinus Walleij } 327f80cb526SLinus Walleij 328f80cb526SLinus Walleij static void lpc32xx_gpio_set_value_p012(struct gpio_chip *chip, unsigned pin, 329f80cb526SLinus Walleij int value) 330f80cb526SLinus Walleij { 331f80cb526SLinus Walleij struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 332f80cb526SLinus Walleij 333f80cb526SLinus Walleij __set_gpio_level_p012(group, pin, value); 334f80cb526SLinus Walleij } 335f80cb526SLinus Walleij 336f80cb526SLinus Walleij static void lpc32xx_gpio_set_value_p3(struct gpio_chip *chip, unsigned pin, 337f80cb526SLinus Walleij int value) 338f80cb526SLinus Walleij { 339f80cb526SLinus Walleij struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 340f80cb526SLinus Walleij 341f80cb526SLinus Walleij __set_gpio_level_p3(group, pin, value); 342f80cb526SLinus Walleij } 343f80cb526SLinus Walleij 344f80cb526SLinus Walleij static void lpc32xx_gpo_set_value(struct gpio_chip *chip, unsigned pin, 345f80cb526SLinus Walleij int value) 346f80cb526SLinus Walleij { 347f80cb526SLinus Walleij struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 348f80cb526SLinus Walleij 349f80cb526SLinus Walleij __set_gpo_level_p3(group, pin, value); 350f80cb526SLinus Walleij } 351f80cb526SLinus Walleij 35246158aadSRoland Stigge static int lpc32xx_gpo_get_value(struct gpio_chip *chip, unsigned pin) 35346158aadSRoland Stigge { 35446158aadSRoland Stigge struct lpc32xx_gpio_chip *group = to_lpc32xx_gpio(chip); 35546158aadSRoland Stigge 35646158aadSRoland Stigge return __get_gpo_state_p3(group, pin); 35746158aadSRoland Stigge } 35846158aadSRoland Stigge 359f80cb526SLinus Walleij static int lpc32xx_gpio_request(struct gpio_chip *chip, unsigned pin) 360f80cb526SLinus Walleij { 361f80cb526SLinus Walleij if (pin < chip->ngpio) 362f80cb526SLinus Walleij return 0; 363f80cb526SLinus Walleij 364f80cb526SLinus Walleij return -EINVAL; 365f80cb526SLinus Walleij } 366f80cb526SLinus Walleij 367f80cb526SLinus Walleij static struct lpc32xx_gpio_chip lpc32xx_gpiochip[] = { 368f80cb526SLinus Walleij { 369f80cb526SLinus Walleij .chip = { 370f80cb526SLinus Walleij .label = "gpio_p0", 371f80cb526SLinus Walleij .direction_input = lpc32xx_gpio_dir_input_p012, 372f80cb526SLinus Walleij .get = lpc32xx_gpio_get_value_p012, 373f80cb526SLinus Walleij .direction_output = lpc32xx_gpio_dir_output_p012, 374f80cb526SLinus Walleij .set = lpc32xx_gpio_set_value_p012, 375f80cb526SLinus Walleij .request = lpc32xx_gpio_request, 376f80cb526SLinus Walleij .base = LPC32XX_GPIO_P0_GRP, 377f80cb526SLinus Walleij .ngpio = LPC32XX_GPIO_P0_MAX, 378f80cb526SLinus Walleij .names = gpio_p0_names, 379f80cb526SLinus Walleij .can_sleep = 0, 380f80cb526SLinus Walleij }, 381f80cb526SLinus Walleij .gpio_grp = &gpio_grp_regs_p0, 382f80cb526SLinus Walleij }, 383f80cb526SLinus Walleij { 384f80cb526SLinus Walleij .chip = { 385f80cb526SLinus Walleij .label = "gpio_p1", 386f80cb526SLinus Walleij .direction_input = lpc32xx_gpio_dir_input_p012, 387f80cb526SLinus Walleij .get = lpc32xx_gpio_get_value_p012, 388f80cb526SLinus Walleij .direction_output = lpc32xx_gpio_dir_output_p012, 389f80cb526SLinus Walleij .set = lpc32xx_gpio_set_value_p012, 390f80cb526SLinus Walleij .request = lpc32xx_gpio_request, 391f80cb526SLinus Walleij .base = LPC32XX_GPIO_P1_GRP, 392f80cb526SLinus Walleij .ngpio = LPC32XX_GPIO_P1_MAX, 393f80cb526SLinus Walleij .names = gpio_p1_names, 394f80cb526SLinus Walleij .can_sleep = 0, 395f80cb526SLinus Walleij }, 396f80cb526SLinus Walleij .gpio_grp = &gpio_grp_regs_p1, 397f80cb526SLinus Walleij }, 398f80cb526SLinus Walleij { 399f80cb526SLinus Walleij .chip = { 400f80cb526SLinus Walleij .label = "gpio_p2", 401f80cb526SLinus Walleij .direction_input = lpc32xx_gpio_dir_input_p012, 402f80cb526SLinus Walleij .get = lpc32xx_gpio_get_value_p012, 403f80cb526SLinus Walleij .direction_output = lpc32xx_gpio_dir_output_p012, 404f80cb526SLinus Walleij .set = lpc32xx_gpio_set_value_p012, 405f80cb526SLinus Walleij .request = lpc32xx_gpio_request, 406f80cb526SLinus Walleij .base = LPC32XX_GPIO_P2_GRP, 407f80cb526SLinus Walleij .ngpio = LPC32XX_GPIO_P2_MAX, 408f80cb526SLinus Walleij .names = gpio_p2_names, 409f80cb526SLinus Walleij .can_sleep = 0, 410f80cb526SLinus Walleij }, 411f80cb526SLinus Walleij .gpio_grp = &gpio_grp_regs_p2, 412f80cb526SLinus Walleij }, 413f80cb526SLinus Walleij { 414f80cb526SLinus Walleij .chip = { 415f80cb526SLinus Walleij .label = "gpio_p3", 416f80cb526SLinus Walleij .direction_input = lpc32xx_gpio_dir_input_p3, 417f80cb526SLinus Walleij .get = lpc32xx_gpio_get_value_p3, 418f80cb526SLinus Walleij .direction_output = lpc32xx_gpio_dir_output_p3, 419f80cb526SLinus Walleij .set = lpc32xx_gpio_set_value_p3, 420f80cb526SLinus Walleij .request = lpc32xx_gpio_request, 421f80cb526SLinus Walleij .base = LPC32XX_GPIO_P3_GRP, 422f80cb526SLinus Walleij .ngpio = LPC32XX_GPIO_P3_MAX, 423f80cb526SLinus Walleij .names = gpio_p3_names, 424f80cb526SLinus Walleij .can_sleep = 0, 425f80cb526SLinus Walleij }, 426f80cb526SLinus Walleij .gpio_grp = &gpio_grp_regs_p3, 427f80cb526SLinus Walleij }, 428f80cb526SLinus Walleij { 429f80cb526SLinus Walleij .chip = { 430f80cb526SLinus Walleij .label = "gpi_p3", 431f80cb526SLinus Walleij .direction_input = lpc32xx_gpio_dir_in_always, 432f80cb526SLinus Walleij .get = lpc32xx_gpi_get_value, 433f80cb526SLinus Walleij .request = lpc32xx_gpio_request, 434f80cb526SLinus Walleij .base = LPC32XX_GPI_P3_GRP, 435f80cb526SLinus Walleij .ngpio = LPC32XX_GPI_P3_MAX, 436f80cb526SLinus Walleij .names = gpi_p3_names, 437f80cb526SLinus Walleij .can_sleep = 0, 438f80cb526SLinus Walleij }, 439f80cb526SLinus Walleij .gpio_grp = &gpio_grp_regs_p3, 440f80cb526SLinus Walleij }, 441f80cb526SLinus Walleij { 442f80cb526SLinus Walleij .chip = { 443f80cb526SLinus Walleij .label = "gpo_p3", 444f80cb526SLinus Walleij .direction_output = lpc32xx_gpio_dir_out_always, 445f80cb526SLinus Walleij .set = lpc32xx_gpo_set_value, 44646158aadSRoland Stigge .get = lpc32xx_gpo_get_value, 447f80cb526SLinus Walleij .request = lpc32xx_gpio_request, 448f80cb526SLinus Walleij .base = LPC32XX_GPO_P3_GRP, 449f80cb526SLinus Walleij .ngpio = LPC32XX_GPO_P3_MAX, 450f80cb526SLinus Walleij .names = gpo_p3_names, 451f80cb526SLinus Walleij .can_sleep = 0, 452f80cb526SLinus Walleij }, 453f80cb526SLinus Walleij .gpio_grp = &gpio_grp_regs_p3, 454f80cb526SLinus Walleij }, 455f80cb526SLinus Walleij }; 456f80cb526SLinus Walleij 457f80cb526SLinus Walleij void __init lpc32xx_gpio_init(void) 458f80cb526SLinus Walleij { 459f80cb526SLinus Walleij int i; 460f80cb526SLinus Walleij 461f80cb526SLinus Walleij for (i = 0; i < ARRAY_SIZE(lpc32xx_gpiochip); i++) 462f80cb526SLinus Walleij gpiochip_add(&lpc32xx_gpiochip[i].chip); 463f80cb526SLinus Walleij } 464