1a10e763bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 20cc59b9dSMilo Kim /* 30cc59b9dSMilo Kim * TI/National Semiconductor LP3943 GPIO driver 40cc59b9dSMilo Kim * 50cc59b9dSMilo Kim * Copyright 2013 Texas Instruments 60cc59b9dSMilo Kim * 70cc59b9dSMilo Kim * Author: Milo Kim <milo.kim@ti.com> 80cc59b9dSMilo Kim */ 90cc59b9dSMilo Kim 100cc59b9dSMilo Kim #include <linux/bitops.h> 110cc59b9dSMilo Kim #include <linux/err.h> 12e92a5c61SLinus Walleij #include <linux/gpio/driver.h> 130cc59b9dSMilo Kim #include <linux/i2c.h> 140cc59b9dSMilo Kim #include <linux/mfd/lp3943.h> 150cc59b9dSMilo Kim #include <linux/module.h> 160cc59b9dSMilo Kim #include <linux/platform_device.h> 170cc59b9dSMilo Kim #include <linux/slab.h> 180cc59b9dSMilo Kim 190cc59b9dSMilo Kim enum lp3943_gpios { 200cc59b9dSMilo Kim LP3943_GPIO1, 210cc59b9dSMilo Kim LP3943_GPIO2, 220cc59b9dSMilo Kim LP3943_GPIO3, 230cc59b9dSMilo Kim LP3943_GPIO4, 240cc59b9dSMilo Kim LP3943_GPIO5, 250cc59b9dSMilo Kim LP3943_GPIO6, 260cc59b9dSMilo Kim LP3943_GPIO7, 270cc59b9dSMilo Kim LP3943_GPIO8, 280cc59b9dSMilo Kim LP3943_GPIO9, 290cc59b9dSMilo Kim LP3943_GPIO10, 300cc59b9dSMilo Kim LP3943_GPIO11, 310cc59b9dSMilo Kim LP3943_GPIO12, 320cc59b9dSMilo Kim LP3943_GPIO13, 330cc59b9dSMilo Kim LP3943_GPIO14, 340cc59b9dSMilo Kim LP3943_GPIO15, 350cc59b9dSMilo Kim LP3943_GPIO16, 360cc59b9dSMilo Kim LP3943_MAX_GPIO, 370cc59b9dSMilo Kim }; 380cc59b9dSMilo Kim 390cc59b9dSMilo Kim struct lp3943_gpio { 400cc59b9dSMilo Kim struct gpio_chip chip; 410cc59b9dSMilo Kim struct lp3943 *lp3943; 420cc59b9dSMilo Kim u16 input_mask; /* 1 = GPIO is input direction, 0 = output */ 430cc59b9dSMilo Kim }; 440cc59b9dSMilo Kim 4570aba44bSLinus Walleij static int lp3943_gpio_request(struct gpio_chip *chip, unsigned offset) 4670aba44bSLinus Walleij { 4770aba44bSLinus Walleij struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip); 4870aba44bSLinus Walleij struct lp3943 *lp3943 = lp3943_gpio->lp3943; 4970aba44bSLinus Walleij 5070aba44bSLinus Walleij /* Return an error if the pin is already assigned */ 5170aba44bSLinus Walleij if (test_and_set_bit(offset, &lp3943->pin_used)) 5270aba44bSLinus Walleij return -EBUSY; 5370aba44bSLinus Walleij 5470aba44bSLinus Walleij return 0; 5570aba44bSLinus Walleij } 5670aba44bSLinus Walleij 5770aba44bSLinus Walleij static void lp3943_gpio_free(struct gpio_chip *chip, unsigned offset) 5870aba44bSLinus Walleij { 5970aba44bSLinus Walleij struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip); 6070aba44bSLinus Walleij struct lp3943 *lp3943 = lp3943_gpio->lp3943; 6170aba44bSLinus Walleij 6270aba44bSLinus Walleij clear_bit(offset, &lp3943->pin_used); 6370aba44bSLinus Walleij } 6470aba44bSLinus Walleij 650cc59b9dSMilo Kim static int lp3943_gpio_set_mode(struct lp3943_gpio *lp3943_gpio, u8 offset, 660cc59b9dSMilo Kim u8 val) 670cc59b9dSMilo Kim { 680cc59b9dSMilo Kim struct lp3943 *lp3943 = lp3943_gpio->lp3943; 690cc59b9dSMilo Kim const struct lp3943_reg_cfg *mux = lp3943->mux_cfg; 700cc59b9dSMilo Kim 710cc59b9dSMilo Kim return lp3943_update_bits(lp3943, mux[offset].reg, mux[offset].mask, 720cc59b9dSMilo Kim val << mux[offset].shift); 730cc59b9dSMilo Kim } 740cc59b9dSMilo Kim 750cc59b9dSMilo Kim static int lp3943_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 760cc59b9dSMilo Kim { 77a2f33804SLinus Walleij struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip); 780cc59b9dSMilo Kim 790cc59b9dSMilo Kim lp3943_gpio->input_mask |= BIT(offset); 800cc59b9dSMilo Kim 810cc59b9dSMilo Kim return lp3943_gpio_set_mode(lp3943_gpio, offset, LP3943_GPIO_IN); 820cc59b9dSMilo Kim } 830cc59b9dSMilo Kim 840cc59b9dSMilo Kim static int lp3943_get_gpio_in_status(struct lp3943_gpio *lp3943_gpio, 850cc59b9dSMilo Kim struct gpio_chip *chip, unsigned offset) 860cc59b9dSMilo Kim { 870cc59b9dSMilo Kim u8 addr, read; 880cc59b9dSMilo Kim int err; 890cc59b9dSMilo Kim 900cc59b9dSMilo Kim switch (offset) { 910cc59b9dSMilo Kim case LP3943_GPIO1 ... LP3943_GPIO8: 920cc59b9dSMilo Kim addr = LP3943_REG_GPIO_A; 930cc59b9dSMilo Kim break; 940cc59b9dSMilo Kim case LP3943_GPIO9 ... LP3943_GPIO16: 950cc59b9dSMilo Kim addr = LP3943_REG_GPIO_B; 960cc59b9dSMilo Kim offset = offset - 8; 970cc59b9dSMilo Kim break; 980cc59b9dSMilo Kim default: 990cc59b9dSMilo Kim return -EINVAL; 1000cc59b9dSMilo Kim } 1010cc59b9dSMilo Kim 1020cc59b9dSMilo Kim err = lp3943_read_byte(lp3943_gpio->lp3943, addr, &read); 1030cc59b9dSMilo Kim if (err) 1040cc59b9dSMilo Kim return err; 1050cc59b9dSMilo Kim 1060cc59b9dSMilo Kim return !!(read & BIT(offset)); 1070cc59b9dSMilo Kim } 1080cc59b9dSMilo Kim 1090cc59b9dSMilo Kim static int lp3943_get_gpio_out_status(struct lp3943_gpio *lp3943_gpio, 1100cc59b9dSMilo Kim struct gpio_chip *chip, unsigned offset) 1110cc59b9dSMilo Kim { 1120cc59b9dSMilo Kim struct lp3943 *lp3943 = lp3943_gpio->lp3943; 1130cc59b9dSMilo Kim const struct lp3943_reg_cfg *mux = lp3943->mux_cfg; 1140cc59b9dSMilo Kim u8 read; 1150cc59b9dSMilo Kim int err; 1160cc59b9dSMilo Kim 1170cc59b9dSMilo Kim err = lp3943_read_byte(lp3943, mux[offset].reg, &read); 1180cc59b9dSMilo Kim if (err) 1190cc59b9dSMilo Kim return err; 1200cc59b9dSMilo Kim 1210cc59b9dSMilo Kim read = (read & mux[offset].mask) >> mux[offset].shift; 1220cc59b9dSMilo Kim 1230cc59b9dSMilo Kim if (read == LP3943_GPIO_OUT_HIGH) 1240cc59b9dSMilo Kim return 1; 1250cc59b9dSMilo Kim else if (read == LP3943_GPIO_OUT_LOW) 1260cc59b9dSMilo Kim return 0; 1270cc59b9dSMilo Kim else 1280cc59b9dSMilo Kim return -EINVAL; 1290cc59b9dSMilo Kim } 1300cc59b9dSMilo Kim 1310cc59b9dSMilo Kim static int lp3943_gpio_get(struct gpio_chip *chip, unsigned offset) 1320cc59b9dSMilo Kim { 133a2f33804SLinus Walleij struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip); 1340cc59b9dSMilo Kim 1350cc59b9dSMilo Kim /* 1360cc59b9dSMilo Kim * Limitation: 1370cc59b9dSMilo Kim * LP3943 doesn't have the GPIO direction register. It provides 1380cc59b9dSMilo Kim * only input and output status registers. 1390cc59b9dSMilo Kim * So, direction info is required to handle the 'get' operation. 1400cc59b9dSMilo Kim * This variable is updated whenever the direction is changed and 1410cc59b9dSMilo Kim * it is used here. 1420cc59b9dSMilo Kim */ 1430cc59b9dSMilo Kim 1440cc59b9dSMilo Kim if (lp3943_gpio->input_mask & BIT(offset)) 1450cc59b9dSMilo Kim return lp3943_get_gpio_in_status(lp3943_gpio, chip, offset); 1460cc59b9dSMilo Kim else 1470cc59b9dSMilo Kim return lp3943_get_gpio_out_status(lp3943_gpio, chip, offset); 1480cc59b9dSMilo Kim } 1490cc59b9dSMilo Kim 1500cc59b9dSMilo Kim static void lp3943_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1510cc59b9dSMilo Kim { 152a2f33804SLinus Walleij struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip); 1530cc59b9dSMilo Kim u8 data; 1540cc59b9dSMilo Kim 1550cc59b9dSMilo Kim if (value) 1560cc59b9dSMilo Kim data = LP3943_GPIO_OUT_HIGH; 1570cc59b9dSMilo Kim else 1580cc59b9dSMilo Kim data = LP3943_GPIO_OUT_LOW; 1590cc59b9dSMilo Kim 1600cc59b9dSMilo Kim lp3943_gpio_set_mode(lp3943_gpio, offset, data); 1610cc59b9dSMilo Kim } 1620cc59b9dSMilo Kim 1630cc59b9dSMilo Kim static int lp3943_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 1640cc59b9dSMilo Kim int value) 1650cc59b9dSMilo Kim { 166a2f33804SLinus Walleij struct lp3943_gpio *lp3943_gpio = gpiochip_get_data(chip); 1670cc59b9dSMilo Kim 1680cc59b9dSMilo Kim lp3943_gpio_set(chip, offset, value); 1690cc59b9dSMilo Kim lp3943_gpio->input_mask &= ~BIT(offset); 1700cc59b9dSMilo Kim 1710cc59b9dSMilo Kim return 0; 1720cc59b9dSMilo Kim } 1730cc59b9dSMilo Kim 1740cc59b9dSMilo Kim static const struct gpio_chip lp3943_gpio_chip = { 1750cc59b9dSMilo Kim .label = "lp3943", 1760cc59b9dSMilo Kim .owner = THIS_MODULE, 17770aba44bSLinus Walleij .request = lp3943_gpio_request, 17870aba44bSLinus Walleij .free = lp3943_gpio_free, 1790cc59b9dSMilo Kim .direction_input = lp3943_gpio_direction_input, 1800cc59b9dSMilo Kim .get = lp3943_gpio_get, 1810cc59b9dSMilo Kim .direction_output = lp3943_gpio_direction_output, 1820cc59b9dSMilo Kim .set = lp3943_gpio_set, 1830cc59b9dSMilo Kim .base = -1, 1840cc59b9dSMilo Kim .ngpio = LP3943_MAX_GPIO, 1850cc59b9dSMilo Kim .can_sleep = 1, 1860cc59b9dSMilo Kim }; 1870cc59b9dSMilo Kim 1880cc59b9dSMilo Kim static int lp3943_gpio_probe(struct platform_device *pdev) 1890cc59b9dSMilo Kim { 1900cc59b9dSMilo Kim struct lp3943 *lp3943 = dev_get_drvdata(pdev->dev.parent); 1910cc59b9dSMilo Kim struct lp3943_gpio *lp3943_gpio; 1920cc59b9dSMilo Kim 1930cc59b9dSMilo Kim lp3943_gpio = devm_kzalloc(&pdev->dev, sizeof(*lp3943_gpio), 1940cc59b9dSMilo Kim GFP_KERNEL); 1950cc59b9dSMilo Kim if (!lp3943_gpio) 1960cc59b9dSMilo Kim return -ENOMEM; 1970cc59b9dSMilo Kim 1980cc59b9dSMilo Kim lp3943_gpio->lp3943 = lp3943; 1990cc59b9dSMilo Kim lp3943_gpio->chip = lp3943_gpio_chip; 20058383c78SLinus Walleij lp3943_gpio->chip.parent = &pdev->dev; 2010cc59b9dSMilo Kim 2020cc59b9dSMilo Kim platform_set_drvdata(pdev, lp3943_gpio); 2030cc59b9dSMilo Kim 2044ca75bfeSLaxman Dewangan return devm_gpiochip_add_data(&pdev->dev, &lp3943_gpio->chip, 2054ca75bfeSLaxman Dewangan lp3943_gpio); 2060cc59b9dSMilo Kim } 2070cc59b9dSMilo Kim 2080cc59b9dSMilo Kim static const struct of_device_id lp3943_gpio_of_match[] = { 2090cc59b9dSMilo Kim { .compatible = "ti,lp3943-gpio", }, 2100cc59b9dSMilo Kim { } 2110cc59b9dSMilo Kim }; 2120cc59b9dSMilo Kim MODULE_DEVICE_TABLE(of, lp3943_gpio_of_match); 2130cc59b9dSMilo Kim 2140cc59b9dSMilo Kim static struct platform_driver lp3943_gpio_driver = { 2150cc59b9dSMilo Kim .probe = lp3943_gpio_probe, 2160cc59b9dSMilo Kim .driver = { 2170cc59b9dSMilo Kim .name = "lp3943-gpio", 2183b1ba0cbSSachin Kamat .of_match_table = lp3943_gpio_of_match, 2190cc59b9dSMilo Kim }, 2200cc59b9dSMilo Kim }; 2210cc59b9dSMilo Kim module_platform_driver(lp3943_gpio_driver); 2220cc59b9dSMilo Kim 2230cc59b9dSMilo Kim MODULE_DESCRIPTION("LP3943 GPIO driver"); 2240cc59b9dSMilo Kim MODULE_ALIAS("platform:lp3943-gpio"); 2250cc59b9dSMilo Kim MODULE_AUTHOR("Milo Kim"); 2260cc59b9dSMilo Kim MODULE_LICENSE("GPL"); 227