1 /* 2 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver 3 * 4 * Copyright (C) 2010 Extreme Engineering Solutions. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 19 */ 20 21 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 22 23 #include <linux/module.h> 24 #include <linux/pci.h> 25 #include <linux/gpio.h> 26 #include <linux/platform_device.h> 27 #include <linux/mfd/lpc_ich.h> 28 29 #define DRV_NAME "gpio_ich" 30 31 /* 32 * GPIO register offsets in GPIO I/O space. 33 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and 34 * LVLx registers. Logic in the read/write functions takes a register and 35 * an absolute bit number and determines the proper register offset and bit 36 * number in that register. For example, to read the value of GPIO bit 50 37 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)], 38 * bit 18 (50%32). 39 */ 40 enum GPIO_REG { 41 GPIO_USE_SEL = 0, 42 GPIO_IO_SEL, 43 GPIO_LVL, 44 GPO_BLINK 45 }; 46 47 static const u8 ichx_regs[4][3] = { 48 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */ 49 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */ 50 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */ 51 {0x18, 0x18, 0x18}, /* BLINK offset */ 52 }; 53 54 static const u8 ichx_reglen[3] = { 55 0x30, 0x10, 0x10, 56 }; 57 58 static const u8 avoton_regs[4][3] = { 59 {0x00, 0x80, 0x00}, 60 {0x04, 0x84, 0x00}, 61 {0x08, 0x88, 0x00}, 62 }; 63 64 static const u8 avoton_reglen[3] = { 65 0x10, 0x10, 0x00, 66 }; 67 68 #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) 69 #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) 70 71 struct ichx_desc { 72 /* Max GPIO pins the chipset can have */ 73 uint ngpio; 74 75 /* chipset registers */ 76 const u8 (*regs)[3]; 77 const u8 *reglen; 78 79 /* GPO_BLINK is available on this chipset */ 80 bool have_blink; 81 82 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */ 83 bool uses_gpe0; 84 85 /* USE_SEL is bogus on some chipsets, eg 3100 */ 86 u32 use_sel_ignore[3]; 87 88 /* Some chipsets have quirks, let these use their own request/get */ 89 int (*request)(struct gpio_chip *chip, unsigned offset); 90 int (*get)(struct gpio_chip *chip, unsigned offset); 91 92 /* 93 * Some chipsets don't let reading output values on GPIO_LVL register 94 * this option allows driver caching written output values 95 */ 96 bool use_outlvl_cache; 97 }; 98 99 static struct { 100 spinlock_t lock; 101 struct platform_device *dev; 102 struct gpio_chip chip; 103 struct resource *gpio_base; /* GPIO IO base */ 104 struct resource *pm_base; /* Power Mangagment IO base */ 105 struct ichx_desc *desc; /* Pointer to chipset-specific description */ 106 u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */ 107 u8 use_gpio; /* Which GPIO groups are usable */ 108 int outlvl_cache[3]; /* cached output values */ 109 } ichx_priv; 110 111 static int modparam_gpiobase = -1; /* dynamic */ 112 module_param_named(gpiobase, modparam_gpiobase, int, 0444); 113 MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, " 114 "which is the default."); 115 116 static int ichx_write_bit(int reg, unsigned nr, int val, int verify) 117 { 118 unsigned long flags; 119 u32 data, tmp; 120 int reg_nr = nr / 32; 121 int bit = nr & 0x1f; 122 int ret = 0; 123 124 spin_lock_irqsave(&ichx_priv.lock, flags); 125 126 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 127 data = ichx_priv.outlvl_cache[reg_nr]; 128 else 129 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 130 ichx_priv.gpio_base); 131 132 if (val) 133 data |= 1 << bit; 134 else 135 data &= ~(1 << bit); 136 ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr], 137 ichx_priv.gpio_base); 138 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 139 ichx_priv.outlvl_cache[reg_nr] = data; 140 141 tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 142 ichx_priv.gpio_base); 143 if (verify && data != tmp) 144 ret = -EPERM; 145 146 spin_unlock_irqrestore(&ichx_priv.lock, flags); 147 148 return ret; 149 } 150 151 static int ichx_read_bit(int reg, unsigned nr) 152 { 153 unsigned long flags; 154 u32 data; 155 int reg_nr = nr / 32; 156 int bit = nr & 0x1f; 157 158 spin_lock_irqsave(&ichx_priv.lock, flags); 159 160 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 161 ichx_priv.gpio_base); 162 163 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 164 data = ichx_priv.outlvl_cache[reg_nr] | data; 165 166 spin_unlock_irqrestore(&ichx_priv.lock, flags); 167 168 return data & (1 << bit) ? 1 : 0; 169 } 170 171 static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr) 172 { 173 return !!(ichx_priv.use_gpio & (1 << (nr / 32))); 174 } 175 176 static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr) 177 { 178 return ichx_read_bit(GPIO_IO_SEL, nr) ? GPIOF_DIR_IN : GPIOF_DIR_OUT; 179 } 180 181 static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 182 { 183 /* 184 * Try setting pin as an input and verify it worked since many pins 185 * are output-only. 186 */ 187 if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1)) 188 return -EINVAL; 189 190 return 0; 191 } 192 193 static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 194 int val) 195 { 196 /* Disable blink hardware which is available for GPIOs from 0 to 31. */ 197 if (nr < 32 && ichx_priv.desc->have_blink) 198 ichx_write_bit(GPO_BLINK, nr, 0, 0); 199 200 /* Set GPIO output value. */ 201 ichx_write_bit(GPIO_LVL, nr, val, 0); 202 203 /* 204 * Try setting pin as an output and verify it worked since many pins 205 * are input-only. 206 */ 207 if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1)) 208 return -EINVAL; 209 210 return 0; 211 } 212 213 static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr) 214 { 215 return ichx_read_bit(GPIO_LVL, nr); 216 } 217 218 static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr) 219 { 220 unsigned long flags; 221 u32 data; 222 223 /* 224 * GPI 0 - 15 need to be read from the power management registers on 225 * a ICH6/3100 bridge. 226 */ 227 if (nr < 16) { 228 if (!ichx_priv.pm_base) 229 return -ENXIO; 230 231 spin_lock_irqsave(&ichx_priv.lock, flags); 232 233 /* GPI 0 - 15 are latched, write 1 to clear*/ 234 ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base); 235 data = ICHX_READ(0, ichx_priv.pm_base); 236 237 spin_unlock_irqrestore(&ichx_priv.lock, flags); 238 239 return (data >> 16) & (1 << nr) ? 1 : 0; 240 } else { 241 return ichx_gpio_get(chip, nr); 242 } 243 } 244 245 static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr) 246 { 247 if (!ichx_gpio_check_available(chip, nr)) 248 return -ENXIO; 249 250 /* 251 * Note we assume the BIOS properly set a bridge's USE value. Some 252 * chips (eg Intel 3100) have bogus USE values though, so first see if 253 * the chipset's USE value can be trusted for this specific bit. 254 * If it can't be trusted, assume that the pin can be used as a GPIO. 255 */ 256 if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f))) 257 return 0; 258 259 return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV; 260 } 261 262 static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr) 263 { 264 /* 265 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100 266 * bridge as they are controlled by USE register bits 0 and 1. See 267 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for 268 * additional info. 269 */ 270 if (nr == 16 || nr == 17) 271 nr -= 16; 272 273 return ichx_gpio_request(chip, nr); 274 } 275 276 static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val) 277 { 278 ichx_write_bit(GPIO_LVL, nr, val, 0); 279 } 280 281 static void ichx_gpiolib_setup(struct gpio_chip *chip) 282 { 283 chip->owner = THIS_MODULE; 284 chip->label = DRV_NAME; 285 chip->dev = &ichx_priv.dev->dev; 286 287 /* Allow chip-specific overrides of request()/get() */ 288 chip->request = ichx_priv.desc->request ? 289 ichx_priv.desc->request : ichx_gpio_request; 290 chip->get = ichx_priv.desc->get ? 291 ichx_priv.desc->get : ichx_gpio_get; 292 293 chip->set = ichx_gpio_set; 294 chip->get_direction = ichx_gpio_get_direction; 295 chip->direction_input = ichx_gpio_direction_input; 296 chip->direction_output = ichx_gpio_direction_output; 297 chip->base = modparam_gpiobase; 298 chip->ngpio = ichx_priv.desc->ngpio; 299 chip->can_sleep = false; 300 chip->dbg_show = NULL; 301 } 302 303 /* ICH6-based, 631xesb-based */ 304 static struct ichx_desc ich6_desc = { 305 /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */ 306 .request = ich6_gpio_request, 307 .get = ich6_gpio_get, 308 309 /* GPIO 0-15 are read in the GPE0_STS PM register */ 310 .uses_gpe0 = true, 311 312 .ngpio = 50, 313 .have_blink = true, 314 .regs = ichx_regs, 315 .reglen = ichx_reglen, 316 }; 317 318 /* Intel 3100 */ 319 static struct ichx_desc i3100_desc = { 320 /* 321 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on 322 * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100 323 * Datasheet for more info. 324 */ 325 .use_sel_ignore = {0x00130000, 0x00010000, 0x0}, 326 327 /* The 3100 needs fixups for GPIO 0 - 17 */ 328 .request = ich6_gpio_request, 329 .get = ich6_gpio_get, 330 331 /* GPIO 0-15 are read in the GPE0_STS PM register */ 332 .uses_gpe0 = true, 333 334 .ngpio = 50, 335 .regs = ichx_regs, 336 .reglen = ichx_reglen, 337 }; 338 339 /* ICH7 and ICH8-based */ 340 static struct ichx_desc ich7_desc = { 341 .ngpio = 50, 342 .have_blink = true, 343 .regs = ichx_regs, 344 .reglen = ichx_reglen, 345 }; 346 347 /* ICH9-based */ 348 static struct ichx_desc ich9_desc = { 349 .ngpio = 61, 350 .have_blink = true, 351 .regs = ichx_regs, 352 .reglen = ichx_reglen, 353 }; 354 355 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */ 356 static struct ichx_desc ich10_cons_desc = { 357 .ngpio = 61, 358 .have_blink = true, 359 .regs = ichx_regs, 360 .reglen = ichx_reglen, 361 }; 362 static struct ichx_desc ich10_corp_desc = { 363 .ngpio = 72, 364 .have_blink = true, 365 .regs = ichx_regs, 366 .reglen = ichx_reglen, 367 }; 368 369 /* Intel 5 series, 6 series, 3400 series, and C200 series */ 370 static struct ichx_desc intel5_desc = { 371 .ngpio = 76, 372 .regs = ichx_regs, 373 .reglen = ichx_reglen, 374 }; 375 376 /* Avoton */ 377 static struct ichx_desc avoton_desc = { 378 /* Avoton has only 59 GPIOs, but we assume the first set of register 379 * (Core) has 32 instead of 31 to keep gpio-ich compliance 380 */ 381 .ngpio = 60, 382 .regs = avoton_regs, 383 .reglen = avoton_reglen, 384 .use_outlvl_cache = true, 385 }; 386 387 static int ichx_gpio_request_regions(struct resource *res_base, 388 const char *name, u8 use_gpio) 389 { 390 int i; 391 392 if (!res_base || !res_base->start || !res_base->end) 393 return -ENODEV; 394 395 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) { 396 if (!(use_gpio & (1 << i))) 397 continue; 398 if (!request_region( 399 res_base->start + ichx_priv.desc->regs[0][i], 400 ichx_priv.desc->reglen[i], name)) 401 goto request_err; 402 } 403 return 0; 404 405 request_err: 406 /* Clean up: release already requested regions, if any */ 407 for (i--; i >= 0; i--) { 408 if (!(use_gpio & (1 << i))) 409 continue; 410 release_region(res_base->start + ichx_priv.desc->regs[0][i], 411 ichx_priv.desc->reglen[i]); 412 } 413 return -EBUSY; 414 } 415 416 static void ichx_gpio_release_regions(struct resource *res_base, u8 use_gpio) 417 { 418 int i; 419 420 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) { 421 if (!(use_gpio & (1 << i))) 422 continue; 423 release_region(res_base->start + ichx_priv.desc->regs[0][i], 424 ichx_priv.desc->reglen[i]); 425 } 426 } 427 428 static int ichx_gpio_probe(struct platform_device *pdev) 429 { 430 struct resource *res_base, *res_pm; 431 int err; 432 struct lpc_ich_info *ich_info = dev_get_platdata(&pdev->dev); 433 434 if (!ich_info) 435 return -ENODEV; 436 437 ichx_priv.dev = pdev; 438 439 switch (ich_info->gpio_version) { 440 case ICH_I3100_GPIO: 441 ichx_priv.desc = &i3100_desc; 442 break; 443 case ICH_V5_GPIO: 444 ichx_priv.desc = &intel5_desc; 445 break; 446 case ICH_V6_GPIO: 447 ichx_priv.desc = &ich6_desc; 448 break; 449 case ICH_V7_GPIO: 450 ichx_priv.desc = &ich7_desc; 451 break; 452 case ICH_V9_GPIO: 453 ichx_priv.desc = &ich9_desc; 454 break; 455 case ICH_V10CORP_GPIO: 456 ichx_priv.desc = &ich10_corp_desc; 457 break; 458 case ICH_V10CONS_GPIO: 459 ichx_priv.desc = &ich10_cons_desc; 460 break; 461 case AVOTON_GPIO: 462 ichx_priv.desc = &avoton_desc; 463 break; 464 default: 465 return -ENODEV; 466 } 467 468 spin_lock_init(&ichx_priv.lock); 469 res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO); 470 ichx_priv.use_gpio = ich_info->use_gpio; 471 err = ichx_gpio_request_regions(res_base, pdev->name, 472 ichx_priv.use_gpio); 473 if (err) 474 return err; 475 476 ichx_priv.gpio_base = res_base; 477 478 /* 479 * If necessary, determine the I/O address of ACPI/power management 480 * registers which are needed to read the the GPE0 register for GPI pins 481 * 0 - 15 on some chipsets. 482 */ 483 if (!ichx_priv.desc->uses_gpe0) 484 goto init; 485 486 res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0); 487 if (!res_pm) { 488 pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n"); 489 goto init; 490 } 491 492 if (!request_region(res_pm->start, resource_size(res_pm), 493 pdev->name)) { 494 pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n"); 495 goto init; 496 } 497 498 ichx_priv.pm_base = res_pm; 499 500 init: 501 ichx_gpiolib_setup(&ichx_priv.chip); 502 err = gpiochip_add(&ichx_priv.chip); 503 if (err) { 504 pr_err("Failed to register GPIOs\n"); 505 goto add_err; 506 } 507 508 pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base, 509 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME); 510 511 return 0; 512 513 add_err: 514 ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio); 515 if (ichx_priv.pm_base) 516 release_region(ichx_priv.pm_base->start, 517 resource_size(ichx_priv.pm_base)); 518 return err; 519 } 520 521 static int ichx_gpio_remove(struct platform_device *pdev) 522 { 523 gpiochip_remove(&ichx_priv.chip); 524 525 ichx_gpio_release_regions(ichx_priv.gpio_base, ichx_priv.use_gpio); 526 if (ichx_priv.pm_base) 527 release_region(ichx_priv.pm_base->start, 528 resource_size(ichx_priv.pm_base)); 529 530 return 0; 531 } 532 533 static struct platform_driver ichx_gpio_driver = { 534 .driver = { 535 .name = DRV_NAME, 536 }, 537 .probe = ichx_gpio_probe, 538 .remove = ichx_gpio_remove, 539 }; 540 541 module_platform_driver(ichx_gpio_driver); 542 543 MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>"); 544 MODULE_DESCRIPTION("GPIO interface for Intel ICH series"); 545 MODULE_LICENSE("GPL"); 546 MODULE_ALIAS("platform:"DRV_NAME); 547