1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Intel ICH6-10, Series 5 and 6, Atom C2000 (Avoton/Rangeley) GPIO driver 4 * 5 * Copyright (C) 2010 Extreme Engineering Solutions. 6 */ 7 8 9 #include <linux/bitops.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/ioport.h> 12 #include <linux/mfd/lpc_ich.h> 13 #include <linux/module.h> 14 #include <linux/pci.h> 15 #include <linux/platform_device.h> 16 17 #define DRV_NAME "gpio_ich" 18 19 /* 20 * GPIO register offsets in GPIO I/O space. 21 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and 22 * LVLx registers. Logic in the read/write functions takes a register and 23 * an absolute bit number and determines the proper register offset and bit 24 * number in that register. For example, to read the value of GPIO bit 50 25 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)], 26 * bit 18 (50%32). 27 */ 28 enum GPIO_REG { 29 GPIO_USE_SEL = 0, 30 GPIO_IO_SEL, 31 GPIO_LVL, 32 GPO_BLINK 33 }; 34 35 static const u8 ichx_regs[4][3] = { 36 {0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */ 37 {0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */ 38 {0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */ 39 {0x18, 0x18, 0x18}, /* BLINK offset */ 40 }; 41 42 static const u8 ichx_reglen[3] = { 43 0x30, 0x10, 0x10, 44 }; 45 46 static const u8 avoton_regs[4][3] = { 47 {0x00, 0x80, 0x00}, 48 {0x04, 0x84, 0x00}, 49 {0x08, 0x88, 0x00}, 50 }; 51 52 static const u8 avoton_reglen[3] = { 53 0x10, 0x10, 0x00, 54 }; 55 56 #define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start) 57 #define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start) 58 59 struct ichx_desc { 60 /* Max GPIO pins the chipset can have */ 61 uint ngpio; 62 63 /* chipset registers */ 64 const u8 (*regs)[3]; 65 const u8 *reglen; 66 67 /* GPO_BLINK is available on this chipset */ 68 bool have_blink; 69 70 /* Whether the chipset has GPIO in GPE0_STS in the PM IO region */ 71 bool uses_gpe0; 72 73 /* USE_SEL is bogus on some chipsets, eg 3100 */ 74 u32 use_sel_ignore[3]; 75 76 /* Some chipsets have quirks, let these use their own request/get */ 77 int (*request)(struct gpio_chip *chip, unsigned offset); 78 int (*get)(struct gpio_chip *chip, unsigned offset); 79 80 /* 81 * Some chipsets don't let reading output values on GPIO_LVL register 82 * this option allows driver caching written output values 83 */ 84 bool use_outlvl_cache; 85 }; 86 87 static struct { 88 spinlock_t lock; 89 struct device *dev; 90 struct gpio_chip chip; 91 struct resource *gpio_base; /* GPIO IO base */ 92 struct resource *pm_base; /* Power Mangagment IO base */ 93 struct ichx_desc *desc; /* Pointer to chipset-specific description */ 94 u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */ 95 u8 use_gpio; /* Which GPIO groups are usable */ 96 int outlvl_cache[3]; /* cached output values */ 97 } ichx_priv; 98 99 static int modparam_gpiobase = -1; /* dynamic */ 100 module_param_named(gpiobase, modparam_gpiobase, int, 0444); 101 MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, which is the default."); 102 103 static int ichx_write_bit(int reg, unsigned nr, int val, int verify) 104 { 105 unsigned long flags; 106 u32 data, tmp; 107 int reg_nr = nr / 32; 108 int bit = nr & 0x1f; 109 110 spin_lock_irqsave(&ichx_priv.lock, flags); 111 112 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 113 data = ichx_priv.outlvl_cache[reg_nr]; 114 else 115 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 116 ichx_priv.gpio_base); 117 118 if (val) 119 data |= BIT(bit); 120 else 121 data &= ~BIT(bit); 122 ICHX_WRITE(data, ichx_priv.desc->regs[reg][reg_nr], 123 ichx_priv.gpio_base); 124 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 125 ichx_priv.outlvl_cache[reg_nr] = data; 126 127 tmp = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 128 ichx_priv.gpio_base); 129 130 spin_unlock_irqrestore(&ichx_priv.lock, flags); 131 132 return (verify && data != tmp) ? -EPERM : 0; 133 } 134 135 static int ichx_read_bit(int reg, unsigned nr) 136 { 137 unsigned long flags; 138 u32 data; 139 int reg_nr = nr / 32; 140 int bit = nr & 0x1f; 141 142 spin_lock_irqsave(&ichx_priv.lock, flags); 143 144 data = ICHX_READ(ichx_priv.desc->regs[reg][reg_nr], 145 ichx_priv.gpio_base); 146 147 if (reg == GPIO_LVL && ichx_priv.desc->use_outlvl_cache) 148 data = ichx_priv.outlvl_cache[reg_nr] | data; 149 150 spin_unlock_irqrestore(&ichx_priv.lock, flags); 151 152 return !!(data & BIT(bit)); 153 } 154 155 static bool ichx_gpio_check_available(struct gpio_chip *gpio, unsigned nr) 156 { 157 return !!(ichx_priv.use_gpio & BIT(nr / 32)); 158 } 159 160 static int ichx_gpio_get_direction(struct gpio_chip *gpio, unsigned nr) 161 { 162 if (ichx_read_bit(GPIO_IO_SEL, nr)) 163 return GPIO_LINE_DIRECTION_IN; 164 165 return GPIO_LINE_DIRECTION_OUT; 166 } 167 168 static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 169 { 170 /* 171 * Try setting pin as an input and verify it worked since many pins 172 * are output-only. 173 */ 174 return ichx_write_bit(GPIO_IO_SEL, nr, 1, 1); 175 } 176 177 static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 178 int val) 179 { 180 /* Disable blink hardware which is available for GPIOs from 0 to 31. */ 181 if (nr < 32 && ichx_priv.desc->have_blink) 182 ichx_write_bit(GPO_BLINK, nr, 0, 0); 183 184 /* Set GPIO output value. */ 185 ichx_write_bit(GPIO_LVL, nr, val, 0); 186 187 /* 188 * Try setting pin as an output and verify it worked since many pins 189 * are input-only. 190 */ 191 return ichx_write_bit(GPIO_IO_SEL, nr, 0, 1); 192 } 193 194 static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr) 195 { 196 return ichx_read_bit(GPIO_LVL, nr); 197 } 198 199 static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr) 200 { 201 unsigned long flags; 202 u32 data; 203 204 /* 205 * GPI 0 - 15 need to be read from the power management registers on 206 * a ICH6/3100 bridge. 207 */ 208 if (nr < 16) { 209 if (!ichx_priv.pm_base) 210 return -ENXIO; 211 212 spin_lock_irqsave(&ichx_priv.lock, flags); 213 214 /* GPI 0 - 15 are latched, write 1 to clear*/ 215 ICHX_WRITE(BIT(16 + nr), 0, ichx_priv.pm_base); 216 data = ICHX_READ(0, ichx_priv.pm_base); 217 218 spin_unlock_irqrestore(&ichx_priv.lock, flags); 219 220 return !!((data >> 16) & BIT(nr)); 221 } else { 222 return ichx_gpio_get(chip, nr); 223 } 224 } 225 226 static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr) 227 { 228 if (!ichx_gpio_check_available(chip, nr)) 229 return -ENXIO; 230 231 /* 232 * Note we assume the BIOS properly set a bridge's USE value. Some 233 * chips (eg Intel 3100) have bogus USE values though, so first see if 234 * the chipset's USE value can be trusted for this specific bit. 235 * If it can't be trusted, assume that the pin can be used as a GPIO. 236 */ 237 if (ichx_priv.desc->use_sel_ignore[nr / 32] & BIT(nr & 0x1f)) 238 return 0; 239 240 return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV; 241 } 242 243 static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr) 244 { 245 /* 246 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100 247 * bridge as they are controlled by USE register bits 0 and 1. See 248 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for 249 * additional info. 250 */ 251 if (nr == 16 || nr == 17) 252 nr -= 16; 253 254 return ichx_gpio_request(chip, nr); 255 } 256 257 static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val) 258 { 259 ichx_write_bit(GPIO_LVL, nr, val, 0); 260 } 261 262 static void ichx_gpiolib_setup(struct gpio_chip *chip) 263 { 264 chip->owner = THIS_MODULE; 265 chip->label = DRV_NAME; 266 chip->parent = ichx_priv.dev; 267 268 /* Allow chip-specific overrides of request()/get() */ 269 chip->request = ichx_priv.desc->request ? 270 ichx_priv.desc->request : ichx_gpio_request; 271 chip->get = ichx_priv.desc->get ? 272 ichx_priv.desc->get : ichx_gpio_get; 273 274 chip->set = ichx_gpio_set; 275 chip->get_direction = ichx_gpio_get_direction; 276 chip->direction_input = ichx_gpio_direction_input; 277 chip->direction_output = ichx_gpio_direction_output; 278 chip->base = modparam_gpiobase; 279 chip->ngpio = ichx_priv.desc->ngpio; 280 chip->can_sleep = false; 281 chip->dbg_show = NULL; 282 } 283 284 /* ICH6-based, 631xesb-based */ 285 static struct ichx_desc ich6_desc = { 286 /* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */ 287 .request = ich6_gpio_request, 288 .get = ich6_gpio_get, 289 290 /* GPIO 0-15 are read in the GPE0_STS PM register */ 291 .uses_gpe0 = true, 292 293 .ngpio = 50, 294 .have_blink = true, 295 .regs = ichx_regs, 296 .reglen = ichx_reglen, 297 }; 298 299 /* Intel 3100 */ 300 static struct ichx_desc i3100_desc = { 301 /* 302 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on 303 * the Intel 3100. See "Table 712. GPIO Summary Table" of 3100 304 * Datasheet for more info. 305 */ 306 .use_sel_ignore = {0x00130000, 0x00010000, 0x0}, 307 308 /* The 3100 needs fixups for GPIO 0 - 17 */ 309 .request = ich6_gpio_request, 310 .get = ich6_gpio_get, 311 312 /* GPIO 0-15 are read in the GPE0_STS PM register */ 313 .uses_gpe0 = true, 314 315 .ngpio = 50, 316 .regs = ichx_regs, 317 .reglen = ichx_reglen, 318 }; 319 320 /* ICH7 and ICH8-based */ 321 static struct ichx_desc ich7_desc = { 322 .ngpio = 50, 323 .have_blink = true, 324 .regs = ichx_regs, 325 .reglen = ichx_reglen, 326 }; 327 328 /* ICH9-based */ 329 static struct ichx_desc ich9_desc = { 330 .ngpio = 61, 331 .have_blink = true, 332 .regs = ichx_regs, 333 .reglen = ichx_reglen, 334 }; 335 336 /* ICH10-based - Consumer/corporate versions have different amount of GPIO */ 337 static struct ichx_desc ich10_cons_desc = { 338 .ngpio = 61, 339 .have_blink = true, 340 .regs = ichx_regs, 341 .reglen = ichx_reglen, 342 }; 343 static struct ichx_desc ich10_corp_desc = { 344 .ngpio = 72, 345 .have_blink = true, 346 .regs = ichx_regs, 347 .reglen = ichx_reglen, 348 }; 349 350 /* Intel 5 series, 6 series, 3400 series, and C200 series */ 351 static struct ichx_desc intel5_desc = { 352 .ngpio = 76, 353 .regs = ichx_regs, 354 .reglen = ichx_reglen, 355 }; 356 357 /* Avoton */ 358 static struct ichx_desc avoton_desc = { 359 /* Avoton has only 59 GPIOs, but we assume the first set of register 360 * (Core) has 32 instead of 31 to keep gpio-ich compliance 361 */ 362 .ngpio = 60, 363 .regs = avoton_regs, 364 .reglen = avoton_reglen, 365 .use_outlvl_cache = true, 366 }; 367 368 static int ichx_gpio_request_regions(struct device *dev, 369 struct resource *res_base, const char *name, u8 use_gpio) 370 { 371 int i; 372 373 if (!res_base || !res_base->start || !res_base->end) 374 return -ENODEV; 375 376 for (i = 0; i < ARRAY_SIZE(ichx_priv.desc->regs[0]); i++) { 377 if (!(use_gpio & BIT(i))) 378 continue; 379 if (!devm_request_region(dev, 380 res_base->start + ichx_priv.desc->regs[0][i], 381 ichx_priv.desc->reglen[i], name)) 382 return -EBUSY; 383 } 384 return 0; 385 } 386 387 static int ichx_gpio_probe(struct platform_device *pdev) 388 { 389 struct device *dev = &pdev->dev; 390 struct lpc_ich_info *ich_info = dev_get_platdata(dev); 391 struct resource *res_base, *res_pm; 392 int err; 393 394 if (!ich_info) 395 return -ENODEV; 396 397 switch (ich_info->gpio_version) { 398 case ICH_I3100_GPIO: 399 ichx_priv.desc = &i3100_desc; 400 break; 401 case ICH_V5_GPIO: 402 ichx_priv.desc = &intel5_desc; 403 break; 404 case ICH_V6_GPIO: 405 ichx_priv.desc = &ich6_desc; 406 break; 407 case ICH_V7_GPIO: 408 ichx_priv.desc = &ich7_desc; 409 break; 410 case ICH_V9_GPIO: 411 ichx_priv.desc = &ich9_desc; 412 break; 413 case ICH_V10CORP_GPIO: 414 ichx_priv.desc = &ich10_corp_desc; 415 break; 416 case ICH_V10CONS_GPIO: 417 ichx_priv.desc = &ich10_cons_desc; 418 break; 419 case AVOTON_GPIO: 420 ichx_priv.desc = &avoton_desc; 421 break; 422 default: 423 return -ENODEV; 424 } 425 426 ichx_priv.dev = dev; 427 spin_lock_init(&ichx_priv.lock); 428 429 res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO); 430 err = ichx_gpio_request_regions(dev, res_base, pdev->name, 431 ich_info->use_gpio); 432 if (err) 433 return err; 434 435 ichx_priv.gpio_base = res_base; 436 ichx_priv.use_gpio = ich_info->use_gpio; 437 438 /* 439 * If necessary, determine the I/O address of ACPI/power management 440 * registers which are needed to read the GPE0 register for GPI pins 441 * 0 - 15 on some chipsets. 442 */ 443 if (!ichx_priv.desc->uses_gpe0) 444 goto init; 445 446 res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0); 447 if (!res_pm) { 448 dev_warn(dev, "ACPI BAR is unavailable, GPI 0 - 15 unavailable\n"); 449 goto init; 450 } 451 452 if (!devm_request_region(dev, res_pm->start, resource_size(res_pm), 453 pdev->name)) { 454 dev_warn(dev, "ACPI BAR is busy, GPI 0 - 15 unavailable\n"); 455 goto init; 456 } 457 458 ichx_priv.pm_base = res_pm; 459 460 init: 461 ichx_gpiolib_setup(&ichx_priv.chip); 462 err = gpiochip_add_data(&ichx_priv.chip, NULL); 463 if (err) { 464 dev_err(dev, "Failed to register GPIOs\n"); 465 return err; 466 } 467 468 dev_info(dev, "GPIO from %d to %d\n", ichx_priv.chip.base, 469 ichx_priv.chip.base + ichx_priv.chip.ngpio - 1); 470 471 return 0; 472 } 473 474 static int ichx_gpio_remove(struct platform_device *pdev) 475 { 476 gpiochip_remove(&ichx_priv.chip); 477 478 return 0; 479 } 480 481 static struct platform_driver ichx_gpio_driver = { 482 .driver = { 483 .name = DRV_NAME, 484 }, 485 .probe = ichx_gpio_probe, 486 .remove = ichx_gpio_remove, 487 }; 488 489 module_platform_driver(ichx_gpio_driver); 490 491 MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>"); 492 MODULE_DESCRIPTION("GPIO interface for Intel ICH series"); 493 MODULE_LICENSE("GPL"); 494 MODULE_ALIAS("platform:"DRV_NAME); 495