1356b01a9SLuo Jiaxing // SPDX-License-Identifier: GPL-2.0-only
2356b01a9SLuo Jiaxing /* Copyright (c) 2020 HiSilicon Limited. */
3356b01a9SLuo Jiaxing #include <linux/gpio/driver.h>
4356b01a9SLuo Jiaxing #include <linux/module.h>
5356b01a9SLuo Jiaxing #include <linux/mod_devicetable.h>
6356b01a9SLuo Jiaxing #include <linux/platform_device.h>
7356b01a9SLuo Jiaxing #include <linux/property.h>
8356b01a9SLuo Jiaxing
9356b01a9SLuo Jiaxing #define HISI_GPIO_SWPORT_DR_SET_WX 0x000
10356b01a9SLuo Jiaxing #define HISI_GPIO_SWPORT_DR_CLR_WX 0x004
11356b01a9SLuo Jiaxing #define HISI_GPIO_SWPORT_DDR_SET_WX 0x010
12356b01a9SLuo Jiaxing #define HISI_GPIO_SWPORT_DDR_CLR_WX 0x014
13356b01a9SLuo Jiaxing #define HISI_GPIO_SWPORT_DDR_ST_WX 0x018
14356b01a9SLuo Jiaxing #define HISI_GPIO_INTEN_SET_WX 0x020
15356b01a9SLuo Jiaxing #define HISI_GPIO_INTEN_CLR_WX 0x024
16356b01a9SLuo Jiaxing #define HISI_GPIO_INTMASK_SET_WX 0x030
17356b01a9SLuo Jiaxing #define HISI_GPIO_INTMASK_CLR_WX 0x034
18356b01a9SLuo Jiaxing #define HISI_GPIO_INTTYPE_EDGE_SET_WX 0x040
19356b01a9SLuo Jiaxing #define HISI_GPIO_INTTYPE_EDGE_CLR_WX 0x044
20356b01a9SLuo Jiaxing #define HISI_GPIO_INT_POLARITY_SET_WX 0x050
21356b01a9SLuo Jiaxing #define HISI_GPIO_INT_POLARITY_CLR_WX 0x054
22356b01a9SLuo Jiaxing #define HISI_GPIO_DEBOUNCE_SET_WX 0x060
23356b01a9SLuo Jiaxing #define HISI_GPIO_DEBOUNCE_CLR_WX 0x064
24356b01a9SLuo Jiaxing #define HISI_GPIO_INTSTATUS_WX 0x070
25356b01a9SLuo Jiaxing #define HISI_GPIO_PORTA_EOI_WX 0x078
26356b01a9SLuo Jiaxing #define HISI_GPIO_EXT_PORT_WX 0x080
27356b01a9SLuo Jiaxing #define HISI_GPIO_INTCOMB_MASK_WX 0x0a0
28356b01a9SLuo Jiaxing #define HISI_GPIO_INT_DEDGE_SET 0x0b0
29356b01a9SLuo Jiaxing #define HISI_GPIO_INT_DEDGE_CLR 0x0b4
30356b01a9SLuo Jiaxing #define HISI_GPIO_INT_DEDGE_ST 0x0b8
31356b01a9SLuo Jiaxing
32356b01a9SLuo Jiaxing #define HISI_GPIO_LINE_NUM_MAX 32
33356b01a9SLuo Jiaxing #define HISI_GPIO_DRIVER_NAME "gpio-hisi"
34356b01a9SLuo Jiaxing
35356b01a9SLuo Jiaxing struct hisi_gpio {
36356b01a9SLuo Jiaxing struct gpio_chip chip;
37356b01a9SLuo Jiaxing struct device *dev;
38356b01a9SLuo Jiaxing void __iomem *reg_base;
39356b01a9SLuo Jiaxing unsigned int line_num;
40356b01a9SLuo Jiaxing int irq;
41356b01a9SLuo Jiaxing };
42356b01a9SLuo Jiaxing
hisi_gpio_read_reg(struct gpio_chip * chip,unsigned int off)43356b01a9SLuo Jiaxing static inline u32 hisi_gpio_read_reg(struct gpio_chip *chip,
44356b01a9SLuo Jiaxing unsigned int off)
45356b01a9SLuo Jiaxing {
46356b01a9SLuo Jiaxing struct hisi_gpio *hisi_gpio =
47356b01a9SLuo Jiaxing container_of(chip, struct hisi_gpio, chip);
48356b01a9SLuo Jiaxing void __iomem *reg = hisi_gpio->reg_base + off;
49356b01a9SLuo Jiaxing
50356b01a9SLuo Jiaxing return readl(reg);
51356b01a9SLuo Jiaxing }
52356b01a9SLuo Jiaxing
hisi_gpio_write_reg(struct gpio_chip * chip,unsigned int off,u32 val)53356b01a9SLuo Jiaxing static inline void hisi_gpio_write_reg(struct gpio_chip *chip,
54356b01a9SLuo Jiaxing unsigned int off, u32 val)
55356b01a9SLuo Jiaxing {
56356b01a9SLuo Jiaxing struct hisi_gpio *hisi_gpio =
57356b01a9SLuo Jiaxing container_of(chip, struct hisi_gpio, chip);
58356b01a9SLuo Jiaxing void __iomem *reg = hisi_gpio->reg_base + off;
59356b01a9SLuo Jiaxing
60356b01a9SLuo Jiaxing writel(val, reg);
61356b01a9SLuo Jiaxing }
62356b01a9SLuo Jiaxing
hisi_gpio_set_debounce(struct gpio_chip * chip,unsigned int off,u32 debounce)63356b01a9SLuo Jiaxing static void hisi_gpio_set_debounce(struct gpio_chip *chip, unsigned int off,
64356b01a9SLuo Jiaxing u32 debounce)
65356b01a9SLuo Jiaxing {
66356b01a9SLuo Jiaxing if (debounce)
67356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_SET_WX, BIT(off));
68356b01a9SLuo Jiaxing else
69356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_DEBOUNCE_CLR_WX, BIT(off));
70356b01a9SLuo Jiaxing }
71356b01a9SLuo Jiaxing
hisi_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)72356b01a9SLuo Jiaxing static int hisi_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
73356b01a9SLuo Jiaxing unsigned long config)
74356b01a9SLuo Jiaxing {
75356b01a9SLuo Jiaxing u32 config_para = pinconf_to_config_param(config);
76356b01a9SLuo Jiaxing u32 config_arg;
77356b01a9SLuo Jiaxing
78356b01a9SLuo Jiaxing switch (config_para) {
79356b01a9SLuo Jiaxing case PIN_CONFIG_INPUT_DEBOUNCE:
80356b01a9SLuo Jiaxing config_arg = pinconf_to_config_argument(config);
81356b01a9SLuo Jiaxing hisi_gpio_set_debounce(chip, offset, config_arg);
82356b01a9SLuo Jiaxing break;
83356b01a9SLuo Jiaxing default:
84356b01a9SLuo Jiaxing return -ENOTSUPP;
85356b01a9SLuo Jiaxing }
86356b01a9SLuo Jiaxing
87356b01a9SLuo Jiaxing return 0;
88356b01a9SLuo Jiaxing }
89356b01a9SLuo Jiaxing
hisi_gpio_set_ack(struct irq_data * d)90356b01a9SLuo Jiaxing static void hisi_gpio_set_ack(struct irq_data *d)
91356b01a9SLuo Jiaxing {
92356b01a9SLuo Jiaxing struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
93356b01a9SLuo Jiaxing
94356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_PORTA_EOI_WX, BIT(irqd_to_hwirq(d)));
95356b01a9SLuo Jiaxing }
96356b01a9SLuo Jiaxing
hisi_gpio_irq_set_mask(struct irq_data * d)97356b01a9SLuo Jiaxing static void hisi_gpio_irq_set_mask(struct irq_data *d)
98356b01a9SLuo Jiaxing {
99356b01a9SLuo Jiaxing struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
100356b01a9SLuo Jiaxing
101356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_SET_WX, BIT(irqd_to_hwirq(d)));
102*39bdd6bdSLinus Walleij gpiochip_disable_irq(chip, irqd_to_hwirq(d));
103356b01a9SLuo Jiaxing }
104356b01a9SLuo Jiaxing
hisi_gpio_irq_clr_mask(struct irq_data * d)105356b01a9SLuo Jiaxing static void hisi_gpio_irq_clr_mask(struct irq_data *d)
106356b01a9SLuo Jiaxing {
107356b01a9SLuo Jiaxing struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
108356b01a9SLuo Jiaxing
109*39bdd6bdSLinus Walleij gpiochip_enable_irq(chip, irqd_to_hwirq(d));
110356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INTMASK_CLR_WX, BIT(irqd_to_hwirq(d)));
111356b01a9SLuo Jiaxing }
112356b01a9SLuo Jiaxing
hisi_gpio_irq_set_type(struct irq_data * d,u32 type)113356b01a9SLuo Jiaxing static int hisi_gpio_irq_set_type(struct irq_data *d, u32 type)
114356b01a9SLuo Jiaxing {
115356b01a9SLuo Jiaxing struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
116356b01a9SLuo Jiaxing unsigned int mask = BIT(irqd_to_hwirq(d));
117356b01a9SLuo Jiaxing
118356b01a9SLuo Jiaxing switch (type) {
119356b01a9SLuo Jiaxing case IRQ_TYPE_EDGE_BOTH:
120356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_SET, mask);
121356b01a9SLuo Jiaxing break;
122356b01a9SLuo Jiaxing case IRQ_TYPE_EDGE_RISING:
123356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask);
124356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask);
125356b01a9SLuo Jiaxing break;
126356b01a9SLuo Jiaxing case IRQ_TYPE_EDGE_FALLING:
127356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_SET_WX, mask);
128356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask);
129356b01a9SLuo Jiaxing break;
130356b01a9SLuo Jiaxing case IRQ_TYPE_LEVEL_HIGH:
131356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask);
132356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_SET_WX, mask);
133356b01a9SLuo Jiaxing break;
134356b01a9SLuo Jiaxing case IRQ_TYPE_LEVEL_LOW:
135356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INTTYPE_EDGE_CLR_WX, mask);
136356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INT_POLARITY_CLR_WX, mask);
137356b01a9SLuo Jiaxing break;
138356b01a9SLuo Jiaxing default:
139356b01a9SLuo Jiaxing return -EINVAL;
140356b01a9SLuo Jiaxing }
141356b01a9SLuo Jiaxing
142356b01a9SLuo Jiaxing /*
143356b01a9SLuo Jiaxing * The dual-edge interrupt and other interrupt's registers do not
144356b01a9SLuo Jiaxing * take effect at the same time. The registers of the two-edge
145356b01a9SLuo Jiaxing * interrupts have higher priorities, the configuration of
146356b01a9SLuo Jiaxing * the dual-edge interrupts must be disabled before the configuration
147356b01a9SLuo Jiaxing * of other kind of interrupts.
148356b01a9SLuo Jiaxing */
149356b01a9SLuo Jiaxing if (type != IRQ_TYPE_EDGE_BOTH) {
150356b01a9SLuo Jiaxing unsigned int both = hisi_gpio_read_reg(chip, HISI_GPIO_INT_DEDGE_ST);
151356b01a9SLuo Jiaxing
152356b01a9SLuo Jiaxing if (both & mask)
153356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INT_DEDGE_CLR, mask);
154356b01a9SLuo Jiaxing }
155356b01a9SLuo Jiaxing
156356b01a9SLuo Jiaxing if (type & IRQ_TYPE_LEVEL_MASK)
157356b01a9SLuo Jiaxing irq_set_handler_locked(d, handle_level_irq);
158356b01a9SLuo Jiaxing else if (type & IRQ_TYPE_EDGE_BOTH)
159356b01a9SLuo Jiaxing irq_set_handler_locked(d, handle_edge_irq);
160356b01a9SLuo Jiaxing
161356b01a9SLuo Jiaxing return 0;
162356b01a9SLuo Jiaxing }
163356b01a9SLuo Jiaxing
hisi_gpio_irq_enable(struct irq_data * d)164356b01a9SLuo Jiaxing static void hisi_gpio_irq_enable(struct irq_data *d)
165356b01a9SLuo Jiaxing {
166356b01a9SLuo Jiaxing struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
167356b01a9SLuo Jiaxing
168356b01a9SLuo Jiaxing hisi_gpio_irq_clr_mask(d);
169356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_SET_WX, BIT(irqd_to_hwirq(d)));
170356b01a9SLuo Jiaxing }
171356b01a9SLuo Jiaxing
hisi_gpio_irq_disable(struct irq_data * d)172356b01a9SLuo Jiaxing static void hisi_gpio_irq_disable(struct irq_data *d)
173356b01a9SLuo Jiaxing {
174356b01a9SLuo Jiaxing struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
175356b01a9SLuo Jiaxing
176356b01a9SLuo Jiaxing hisi_gpio_irq_set_mask(d);
177356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INTEN_CLR_WX, BIT(irqd_to_hwirq(d)));
178356b01a9SLuo Jiaxing }
179356b01a9SLuo Jiaxing
hisi_gpio_irq_handler(struct irq_desc * desc)180356b01a9SLuo Jiaxing static void hisi_gpio_irq_handler(struct irq_desc *desc)
181356b01a9SLuo Jiaxing {
182356b01a9SLuo Jiaxing struct hisi_gpio *hisi_gpio = irq_desc_get_handler_data(desc);
183356b01a9SLuo Jiaxing unsigned long irq_msk = hisi_gpio_read_reg(&hisi_gpio->chip,
184356b01a9SLuo Jiaxing HISI_GPIO_INTSTATUS_WX);
185356b01a9SLuo Jiaxing struct irq_chip *irq_c = irq_desc_get_chip(desc);
186356b01a9SLuo Jiaxing int hwirq;
187356b01a9SLuo Jiaxing
188356b01a9SLuo Jiaxing chained_irq_enter(irq_c, desc);
189356b01a9SLuo Jiaxing for_each_set_bit(hwirq, &irq_msk, HISI_GPIO_LINE_NUM_MAX)
190dbd1c54fSMarc Zyngier generic_handle_domain_irq(hisi_gpio->chip.irq.domain,
191dbd1c54fSMarc Zyngier hwirq);
192356b01a9SLuo Jiaxing chained_irq_exit(irq_c, desc);
193356b01a9SLuo Jiaxing }
194356b01a9SLuo Jiaxing
195*39bdd6bdSLinus Walleij static const struct irq_chip hisi_gpio_irq_chip = {
196*39bdd6bdSLinus Walleij .name = "HISI-GPIO",
197*39bdd6bdSLinus Walleij .irq_ack = hisi_gpio_set_ack,
198*39bdd6bdSLinus Walleij .irq_mask = hisi_gpio_irq_set_mask,
199*39bdd6bdSLinus Walleij .irq_unmask = hisi_gpio_irq_clr_mask,
200*39bdd6bdSLinus Walleij .irq_set_type = hisi_gpio_irq_set_type,
201*39bdd6bdSLinus Walleij .irq_enable = hisi_gpio_irq_enable,
202*39bdd6bdSLinus Walleij .irq_disable = hisi_gpio_irq_disable,
203*39bdd6bdSLinus Walleij .flags = IRQCHIP_IMMUTABLE,
204*39bdd6bdSLinus Walleij GPIOCHIP_IRQ_RESOURCE_HELPERS,
205*39bdd6bdSLinus Walleij };
206*39bdd6bdSLinus Walleij
hisi_gpio_init_irq(struct hisi_gpio * hisi_gpio)207356b01a9SLuo Jiaxing static void hisi_gpio_init_irq(struct hisi_gpio *hisi_gpio)
208356b01a9SLuo Jiaxing {
209356b01a9SLuo Jiaxing struct gpio_chip *chip = &hisi_gpio->chip;
210356b01a9SLuo Jiaxing struct gpio_irq_chip *girq_chip = &chip->irq;
211356b01a9SLuo Jiaxing
212*39bdd6bdSLinus Walleij gpio_irq_chip_set_chip(girq_chip, &hisi_gpio_irq_chip);
213356b01a9SLuo Jiaxing girq_chip->default_type = IRQ_TYPE_NONE;
214356b01a9SLuo Jiaxing girq_chip->num_parents = 1;
215356b01a9SLuo Jiaxing girq_chip->parents = &hisi_gpio->irq;
216356b01a9SLuo Jiaxing girq_chip->parent_handler = hisi_gpio_irq_handler;
217356b01a9SLuo Jiaxing girq_chip->parent_handler_data = hisi_gpio;
218356b01a9SLuo Jiaxing
219356b01a9SLuo Jiaxing /* Clear Mask of GPIO controller combine IRQ */
220356b01a9SLuo Jiaxing hisi_gpio_write_reg(chip, HISI_GPIO_INTCOMB_MASK_WX, 1);
221356b01a9SLuo Jiaxing }
222356b01a9SLuo Jiaxing
223356b01a9SLuo Jiaxing static const struct acpi_device_id hisi_gpio_acpi_match[] = {
224356b01a9SLuo Jiaxing {"HISI0184", 0},
225356b01a9SLuo Jiaxing {}
226356b01a9SLuo Jiaxing };
227356b01a9SLuo Jiaxing MODULE_DEVICE_TABLE(acpi, hisi_gpio_acpi_match);
228356b01a9SLuo Jiaxing
22980280df7SWeilong Chen static const struct of_device_id hisi_gpio_dts_match[] = {
23080280df7SWeilong Chen { .compatible = "hisilicon,ascend910-gpio", },
23180280df7SWeilong Chen { }
23280280df7SWeilong Chen };
23380280df7SWeilong Chen MODULE_DEVICE_TABLE(of, hisi_gpio_dts_match);
23480280df7SWeilong Chen
hisi_gpio_get_pdata(struct device * dev,struct hisi_gpio * hisi_gpio)235356b01a9SLuo Jiaxing static void hisi_gpio_get_pdata(struct device *dev,
236356b01a9SLuo Jiaxing struct hisi_gpio *hisi_gpio)
237356b01a9SLuo Jiaxing {
238356b01a9SLuo Jiaxing struct platform_device *pdev = to_platform_device(dev);
239356b01a9SLuo Jiaxing struct fwnode_handle *fwnode;
240356b01a9SLuo Jiaxing int idx = 0;
241356b01a9SLuo Jiaxing
242356b01a9SLuo Jiaxing device_for_each_child_node(dev, fwnode) {
243356b01a9SLuo Jiaxing /* Cycle for once, no need for an array to save line_num */
244356b01a9SLuo Jiaxing if (fwnode_property_read_u32(fwnode, "ngpios",
245356b01a9SLuo Jiaxing &hisi_gpio->line_num)) {
246356b01a9SLuo Jiaxing dev_err(dev,
247356b01a9SLuo Jiaxing "failed to get number of lines for port%d and use default value instead\n",
248356b01a9SLuo Jiaxing idx);
249356b01a9SLuo Jiaxing hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX;
250356b01a9SLuo Jiaxing }
251356b01a9SLuo Jiaxing
252356b01a9SLuo Jiaxing if (WARN_ON(hisi_gpio->line_num > HISI_GPIO_LINE_NUM_MAX))
253356b01a9SLuo Jiaxing hisi_gpio->line_num = HISI_GPIO_LINE_NUM_MAX;
254356b01a9SLuo Jiaxing
255356b01a9SLuo Jiaxing hisi_gpio->irq = platform_get_irq(pdev, idx);
256356b01a9SLuo Jiaxing
257356b01a9SLuo Jiaxing dev_info(dev,
258356b01a9SLuo Jiaxing "get hisi_gpio[%d] with %d lines\n", idx,
259356b01a9SLuo Jiaxing hisi_gpio->line_num);
260356b01a9SLuo Jiaxing
261356b01a9SLuo Jiaxing idx++;
262356b01a9SLuo Jiaxing }
263356b01a9SLuo Jiaxing }
264356b01a9SLuo Jiaxing
hisi_gpio_probe(struct platform_device * pdev)265356b01a9SLuo Jiaxing static int hisi_gpio_probe(struct platform_device *pdev)
266356b01a9SLuo Jiaxing {
267356b01a9SLuo Jiaxing struct device *dev = &pdev->dev;
268356b01a9SLuo Jiaxing struct hisi_gpio *hisi_gpio;
269356b01a9SLuo Jiaxing int port_num;
270356b01a9SLuo Jiaxing int ret;
271356b01a9SLuo Jiaxing
272356b01a9SLuo Jiaxing /*
273356b01a9SLuo Jiaxing * One GPIO controller own one port currently,
274356b01a9SLuo Jiaxing * if we get more from ACPI table, return error.
275356b01a9SLuo Jiaxing */
276356b01a9SLuo Jiaxing port_num = device_get_child_node_count(dev);
277356b01a9SLuo Jiaxing if (WARN_ON(port_num != 1))
278356b01a9SLuo Jiaxing return -ENODEV;
279356b01a9SLuo Jiaxing
280356b01a9SLuo Jiaxing hisi_gpio = devm_kzalloc(dev, sizeof(*hisi_gpio), GFP_KERNEL);
281356b01a9SLuo Jiaxing if (!hisi_gpio)
282356b01a9SLuo Jiaxing return -ENOMEM;
283356b01a9SLuo Jiaxing
284356b01a9SLuo Jiaxing hisi_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
285356b01a9SLuo Jiaxing if (IS_ERR(hisi_gpio->reg_base))
286356b01a9SLuo Jiaxing return PTR_ERR(hisi_gpio->reg_base);
287356b01a9SLuo Jiaxing
288356b01a9SLuo Jiaxing hisi_gpio_get_pdata(dev, hisi_gpio);
289356b01a9SLuo Jiaxing
290356b01a9SLuo Jiaxing hisi_gpio->dev = dev;
291356b01a9SLuo Jiaxing
292356b01a9SLuo Jiaxing ret = bgpio_init(&hisi_gpio->chip, hisi_gpio->dev, 0x4,
293356b01a9SLuo Jiaxing hisi_gpio->reg_base + HISI_GPIO_EXT_PORT_WX,
294356b01a9SLuo Jiaxing hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_SET_WX,
295356b01a9SLuo Jiaxing hisi_gpio->reg_base + HISI_GPIO_SWPORT_DR_CLR_WX,
296356b01a9SLuo Jiaxing hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_SET_WX,
297356b01a9SLuo Jiaxing hisi_gpio->reg_base + HISI_GPIO_SWPORT_DDR_CLR_WX,
298356b01a9SLuo Jiaxing BGPIOF_NO_SET_ON_INPUT);
299356b01a9SLuo Jiaxing if (ret) {
300356b01a9SLuo Jiaxing dev_err(dev, "failed to init, ret = %d\n", ret);
301356b01a9SLuo Jiaxing return ret;
302356b01a9SLuo Jiaxing }
303356b01a9SLuo Jiaxing
304356b01a9SLuo Jiaxing hisi_gpio->chip.set_config = hisi_gpio_set_config;
305356b01a9SLuo Jiaxing hisi_gpio->chip.ngpio = hisi_gpio->line_num;
306356b01a9SLuo Jiaxing hisi_gpio->chip.bgpio_dir_unreadable = 1;
307356b01a9SLuo Jiaxing hisi_gpio->chip.base = -1;
308356b01a9SLuo Jiaxing
309356b01a9SLuo Jiaxing if (hisi_gpio->irq > 0)
310356b01a9SLuo Jiaxing hisi_gpio_init_irq(hisi_gpio);
311356b01a9SLuo Jiaxing
312356b01a9SLuo Jiaxing ret = devm_gpiochip_add_data(dev, &hisi_gpio->chip, hisi_gpio);
313356b01a9SLuo Jiaxing if (ret) {
314356b01a9SLuo Jiaxing dev_err(dev, "failed to register gpiochip, ret = %d\n", ret);
315356b01a9SLuo Jiaxing return ret;
316356b01a9SLuo Jiaxing }
317356b01a9SLuo Jiaxing
318356b01a9SLuo Jiaxing return 0;
319356b01a9SLuo Jiaxing }
320356b01a9SLuo Jiaxing
321356b01a9SLuo Jiaxing static struct platform_driver hisi_gpio_driver = {
322356b01a9SLuo Jiaxing .driver = {
323356b01a9SLuo Jiaxing .name = HISI_GPIO_DRIVER_NAME,
324356b01a9SLuo Jiaxing .acpi_match_table = hisi_gpio_acpi_match,
32580280df7SWeilong Chen .of_match_table = hisi_gpio_dts_match,
326356b01a9SLuo Jiaxing },
327356b01a9SLuo Jiaxing .probe = hisi_gpio_probe,
328356b01a9SLuo Jiaxing };
329356b01a9SLuo Jiaxing
330356b01a9SLuo Jiaxing module_platform_driver(hisi_gpio_driver);
331356b01a9SLuo Jiaxing
332356b01a9SLuo Jiaxing MODULE_LICENSE("GPL");
333356b01a9SLuo Jiaxing MODULE_AUTHOR("Luo Jiaxing <luojiaxing@huawei.com>");
334356b01a9SLuo Jiaxing MODULE_DESCRIPTION("HiSilicon GPIO controller driver");
335356b01a9SLuo Jiaxing MODULE_ALIAS("platform:" HISI_GPIO_DRIVER_NAME);
336