xref: /openbmc/linux/drivers/gpio/gpio-grgpio.c (revision d4295e12) 
1 /*
2  * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
3  *
4  * 2013 (c) Aeroflex Gaisler AB
5  *
6  * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
7  * IP core library.
8  *
9  * Full documentation of the GRGPIO core can be found here:
10  * http://www.gaisler.com/products/grlib/grip.pdf
11  *
12  * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
13  * information on open firmware properties.
14  *
15  * This program is free software; you can redistribute it and/or modify it
16  * under the terms of the GNU General Public License as published by the
17  * Free Software Foundation; either version 2 of the License, or (at your
18  * option) any later version.
19  *
20  * Contributors: Andreas Larsson <andreas@gaisler.com>
21  */
22 
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/spinlock.h>
27 #include <linux/io.h>
28 #include <linux/of.h>
29 #include <linux/of_platform.h>
30 #include <linux/gpio/driver.h>
31 #include <linux/slab.h>
32 #include <linux/err.h>
33 #include <linux/gpio/driver.h>
34 #include <linux/interrupt.h>
35 #include <linux/irq.h>
36 #include <linux/irqdomain.h>
37 #include <linux/bitops.h>
38 
39 #define GRGPIO_MAX_NGPIO 32
40 
41 #define GRGPIO_DATA		0x00
42 #define GRGPIO_OUTPUT		0x04
43 #define GRGPIO_DIR		0x08
44 #define GRGPIO_IMASK		0x0c
45 #define GRGPIO_IPOL		0x10
46 #define GRGPIO_IEDGE		0x14
47 #define GRGPIO_BYPASS		0x18
48 #define GRGPIO_IMAP_BASE	0x20
49 
50 /* Structure for an irq of the core - called an underlying irq */
51 struct grgpio_uirq {
52 	u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
53 	u8 uirq; /* Underlying irq of the gpio driver */
54 };
55 
56 /*
57  * Structure for an irq of a gpio line handed out by this driver. The index is
58  * used to map to the corresponding underlying irq.
59  */
60 struct grgpio_lirq {
61 	s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
62 	u8 irq; /* irq for the gpio line */
63 };
64 
65 struct grgpio_priv {
66 	struct gpio_chip gc;
67 	void __iomem *regs;
68 	struct device *dev;
69 
70 	u32 imask; /* irq mask shadow register */
71 
72 	/*
73 	 * The grgpio core can have multiple "underlying" irqs. The gpio lines
74 	 * can be mapped to any one or none of these underlying irqs
75 	 * independently of each other. This driver sets up an irq domain and
76 	 * hands out separate irqs to each gpio line
77 	 */
78 	struct irq_domain *domain;
79 
80 	/*
81 	 * This array contains information on each underlying irq, each
82 	 * irq of the grgpio core itself.
83 	 */
84 	struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
85 
86 	/*
87 	 * This array contains information for each gpio line on the irqs
88 	 * obtains from this driver. An index value of -1 for a certain gpio
89 	 * line indicates that the line has no irq. Otherwise the index connects
90 	 * the irq to the underlying irq by pointing into the uirqs array.
91 	 */
92 	struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
93 };
94 
95 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
96 			     int val)
97 {
98 	struct gpio_chip *gc = &priv->gc;
99 
100 	if (val)
101 		priv->imask |= BIT(offset);
102 	else
103 		priv->imask &= ~BIT(offset);
104 	gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
105 }
106 
107 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
108 {
109 	struct grgpio_priv *priv = gpiochip_get_data(gc);
110 
111 	if (offset >= gc->ngpio)
112 		return -ENXIO;
113 
114 	if (priv->lirqs[offset].index < 0)
115 		return -ENXIO;
116 
117 	return irq_create_mapping(priv->domain, offset);
118 }
119 
120 /* -------------------- IRQ chip functions -------------------- */
121 
122 static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
123 {
124 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
125 	unsigned long flags;
126 	u32 mask = BIT(d->hwirq);
127 	u32 ipol;
128 	u32 iedge;
129 	u32 pol;
130 	u32 edge;
131 
132 	switch (type) {
133 	case IRQ_TYPE_LEVEL_LOW:
134 		pol = 0;
135 		edge = 0;
136 		break;
137 	case IRQ_TYPE_LEVEL_HIGH:
138 		pol = mask;
139 		edge = 0;
140 		break;
141 	case IRQ_TYPE_EDGE_FALLING:
142 		pol = 0;
143 		edge = mask;
144 		break;
145 	case IRQ_TYPE_EDGE_RISING:
146 		pol = mask;
147 		edge = mask;
148 		break;
149 	default:
150 		return -EINVAL;
151 	}
152 
153 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
154 
155 	ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
156 	iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
157 
158 	priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
159 	priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
160 
161 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
162 
163 	return 0;
164 }
165 
166 static void grgpio_irq_mask(struct irq_data *d)
167 {
168 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
169 	int offset = d->hwirq;
170 	unsigned long flags;
171 
172 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
173 
174 	grgpio_set_imask(priv, offset, 0);
175 
176 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
177 }
178 
179 static void grgpio_irq_unmask(struct irq_data *d)
180 {
181 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
182 	int offset = d->hwirq;
183 	unsigned long flags;
184 
185 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
186 
187 	grgpio_set_imask(priv, offset, 1);
188 
189 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
190 }
191 
192 static struct irq_chip grgpio_irq_chip = {
193 	.name			= "grgpio",
194 	.irq_mask		= grgpio_irq_mask,
195 	.irq_unmask		= grgpio_irq_unmask,
196 	.irq_set_type		= grgpio_irq_set_type,
197 };
198 
199 static irqreturn_t grgpio_irq_handler(int irq, void *dev)
200 {
201 	struct grgpio_priv *priv = dev;
202 	int ngpio = priv->gc.ngpio;
203 	unsigned long flags;
204 	int i;
205 	int match = 0;
206 
207 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
208 
209 	/*
210 	 * For each gpio line, call its interrupt handler if it its underlying
211 	 * irq matches the current irq that is handled.
212 	 */
213 	for (i = 0; i < ngpio; i++) {
214 		struct grgpio_lirq *lirq = &priv->lirqs[i];
215 
216 		if (priv->imask & BIT(i) && lirq->index >= 0 &&
217 		    priv->uirqs[lirq->index].uirq == irq) {
218 			generic_handle_irq(lirq->irq);
219 			match = 1;
220 		}
221 	}
222 
223 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
224 
225 	if (!match)
226 		dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
227 
228 	return IRQ_HANDLED;
229 }
230 
231 /*
232  * This function will be called as a consequence of the call to
233  * irq_create_mapping in grgpio_to_irq
234  */
235 static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
236 			  irq_hw_number_t hwirq)
237 {
238 	struct grgpio_priv *priv = d->host_data;
239 	struct grgpio_lirq *lirq;
240 	struct grgpio_uirq *uirq;
241 	unsigned long flags;
242 	int offset = hwirq;
243 	int ret = 0;
244 
245 	if (!priv)
246 		return -EINVAL;
247 
248 	lirq = &priv->lirqs[offset];
249 	if (lirq->index < 0)
250 		return -EINVAL;
251 
252 	dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
253 		irq, offset);
254 
255 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
256 
257 	/* Request underlying irq if not already requested */
258 	lirq->irq = irq;
259 	uirq = &priv->uirqs[lirq->index];
260 	if (uirq->refcnt == 0) {
261 		ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
262 				  dev_name(priv->dev), priv);
263 		if (ret) {
264 			dev_err(priv->dev,
265 				"Could not request underlying irq %d\n",
266 				uirq->uirq);
267 
268 			spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
269 
270 			return ret;
271 		}
272 	}
273 	uirq->refcnt++;
274 
275 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
276 
277 	/* Setup irq  */
278 	irq_set_chip_data(irq, priv);
279 	irq_set_chip_and_handler(irq, &grgpio_irq_chip,
280 				 handle_simple_irq);
281 	irq_set_noprobe(irq);
282 
283 	return ret;
284 }
285 
286 static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
287 {
288 	struct grgpio_priv *priv = d->host_data;
289 	int index;
290 	struct grgpio_lirq *lirq;
291 	struct grgpio_uirq *uirq;
292 	unsigned long flags;
293 	int ngpio = priv->gc.ngpio;
294 	int i;
295 
296 	irq_set_chip_and_handler(irq, NULL, NULL);
297 	irq_set_chip_data(irq, NULL);
298 
299 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
300 
301 	/* Free underlying irq if last user unmapped */
302 	index = -1;
303 	for (i = 0; i < ngpio; i++) {
304 		lirq = &priv->lirqs[i];
305 		if (lirq->irq == irq) {
306 			grgpio_set_imask(priv, i, 0);
307 			lirq->irq = 0;
308 			index = lirq->index;
309 			break;
310 		}
311 	}
312 	WARN_ON(index < 0);
313 
314 	if (index >= 0) {
315 		uirq = &priv->uirqs[lirq->index];
316 		uirq->refcnt--;
317 		if (uirq->refcnt == 0)
318 			free_irq(uirq->uirq, priv);
319 	}
320 
321 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
322 }
323 
324 static const struct irq_domain_ops grgpio_irq_domain_ops = {
325 	.map	= grgpio_irq_map,
326 	.unmap	= grgpio_irq_unmap,
327 };
328 
329 /* ------------------------------------------------------------ */
330 
331 static int grgpio_probe(struct platform_device *ofdev)
332 {
333 	struct device_node *np = ofdev->dev.of_node;
334 	void  __iomem *regs;
335 	struct gpio_chip *gc;
336 	struct grgpio_priv *priv;
337 	struct resource *res;
338 	int err;
339 	u32 prop;
340 	s32 *irqmap;
341 	int size;
342 	int i;
343 
344 	priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
345 	if (!priv)
346 		return -ENOMEM;
347 
348 	res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
349 	regs = devm_ioremap_resource(&ofdev->dev, res);
350 	if (IS_ERR(regs))
351 		return PTR_ERR(regs);
352 
353 	gc = &priv->gc;
354 	err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
355 			 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
356 			 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
357 	if (err) {
358 		dev_err(&ofdev->dev, "bgpio_init() failed\n");
359 		return err;
360 	}
361 
362 	priv->regs = regs;
363 	priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
364 	priv->dev = &ofdev->dev;
365 
366 	gc->of_node = np;
367 	gc->owner = THIS_MODULE;
368 	gc->to_irq = grgpio_to_irq;
369 	gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
370 	gc->base = -1;
371 
372 	err = of_property_read_u32(np, "nbits", &prop);
373 	if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
374 		gc->ngpio = GRGPIO_MAX_NGPIO;
375 		dev_dbg(&ofdev->dev,
376 			"No or invalid nbits property: assume %d\n", gc->ngpio);
377 	} else {
378 		gc->ngpio = prop;
379 	}
380 
381 	/*
382 	 * The irqmap contains the index values indicating which underlying irq,
383 	 * if anyone, is connected to that line
384 	 */
385 	irqmap = (s32 *)of_get_property(np, "irqmap", &size);
386 	if (irqmap) {
387 		if (size < gc->ngpio) {
388 			dev_err(&ofdev->dev,
389 				"irqmap shorter than ngpio (%d < %d)\n",
390 				size, gc->ngpio);
391 			return -EINVAL;
392 		}
393 
394 		priv->domain = irq_domain_add_linear(np, gc->ngpio,
395 						     &grgpio_irq_domain_ops,
396 						     priv);
397 		if (!priv->domain) {
398 			dev_err(&ofdev->dev, "Could not add irq domain\n");
399 			return -EINVAL;
400 		}
401 
402 		for (i = 0; i < gc->ngpio; i++) {
403 			struct grgpio_lirq *lirq;
404 			int ret;
405 
406 			lirq = &priv->lirqs[i];
407 			lirq->index = irqmap[i];
408 
409 			if (lirq->index < 0)
410 				continue;
411 
412 			ret = platform_get_irq(ofdev, lirq->index);
413 			if (ret <= 0) {
414 				/*
415 				 * Continue without irq functionality for that
416 				 * gpio line
417 				 */
418 				dev_err(priv->dev,
419 					"Failed to get irq for offset %d\n", i);
420 				continue;
421 			}
422 			priv->uirqs[lirq->index].uirq = ret;
423 		}
424 	}
425 
426 	platform_set_drvdata(ofdev, priv);
427 
428 	err = gpiochip_add_data(gc, priv);
429 	if (err) {
430 		dev_err(&ofdev->dev, "Could not add gpiochip\n");
431 		if (priv->domain)
432 			irq_domain_remove(priv->domain);
433 		return err;
434 	}
435 
436 	dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
437 		 priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
438 
439 	return 0;
440 }
441 
442 static int grgpio_remove(struct platform_device *ofdev)
443 {
444 	struct grgpio_priv *priv = platform_get_drvdata(ofdev);
445 	unsigned long flags;
446 	int i;
447 	int ret = 0;
448 
449 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
450 
451 	if (priv->domain) {
452 		for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
453 			if (priv->uirqs[i].refcnt != 0) {
454 				ret = -EBUSY;
455 				goto out;
456 			}
457 		}
458 	}
459 
460 	gpiochip_remove(&priv->gc);
461 
462 	if (priv->domain)
463 		irq_domain_remove(priv->domain);
464 
465 out:
466 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
467 
468 	return ret;
469 }
470 
471 static const struct of_device_id grgpio_match[] = {
472 	{.name = "GAISLER_GPIO"},
473 	{.name = "01_01a"},
474 	{},
475 };
476 
477 MODULE_DEVICE_TABLE(of, grgpio_match);
478 
479 static struct platform_driver grgpio_driver = {
480 	.driver = {
481 		.name = "grgpio",
482 		.of_match_table = grgpio_match,
483 	},
484 	.probe = grgpio_probe,
485 	.remove = grgpio_remove,
486 };
487 module_platform_driver(grgpio_driver);
488 
489 MODULE_AUTHOR("Aeroflex Gaisler AB.");
490 MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
491 MODULE_LICENSE("GPL");
492