xref: /openbmc/linux/drivers/gpio/gpio-grgpio.c (revision b60a5b8d) 
1 /*
2  * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
3  *
4  * 2013 (c) Aeroflex Gaisler AB
5  *
6  * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
7  * IP core library.
8  *
9  * Full documentation of the GRGPIO core can be found here:
10  * http://www.gaisler.com/products/grlib/grip.pdf
11  *
12  * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
13  * information on open firmware properties.
14  *
15  * This program is free software; you can redistribute it and/or modify it
16  * under the terms of the GNU General Public License as published by the
17  * Free Software Foundation; either version 2 of the License, or (at your
18  * option) any later version.
19  *
20  * Contributors: Andreas Larsson <andreas@gaisler.com>
21  */
22 
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/init.h>
26 #include <linux/spinlock.h>
27 #include <linux/io.h>
28 #include <linux/of.h>
29 #include <linux/of_platform.h>
30 #include <linux/gpio/driver.h>
31 #include <linux/slab.h>
32 #include <linux/err.h>
33 #include <linux/interrupt.h>
34 #include <linux/irq.h>
35 #include <linux/irqdomain.h>
36 #include <linux/bitops.h>
37 
38 #define GRGPIO_MAX_NGPIO 32
39 
40 #define GRGPIO_DATA		0x00
41 #define GRGPIO_OUTPUT		0x04
42 #define GRGPIO_DIR		0x08
43 #define GRGPIO_IMASK		0x0c
44 #define GRGPIO_IPOL		0x10
45 #define GRGPIO_IEDGE		0x14
46 #define GRGPIO_BYPASS		0x18
47 #define GRGPIO_IMAP_BASE	0x20
48 
49 /* Structure for an irq of the core - called an underlying irq */
50 struct grgpio_uirq {
51 	u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
52 	u8 uirq; /* Underlying irq of the gpio driver */
53 };
54 
55 /*
56  * Structure for an irq of a gpio line handed out by this driver. The index is
57  * used to map to the corresponding underlying irq.
58  */
59 struct grgpio_lirq {
60 	s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
61 	u8 irq; /* irq for the gpio line */
62 };
63 
64 struct grgpio_priv {
65 	struct gpio_chip gc;
66 	void __iomem *regs;
67 	struct device *dev;
68 
69 	u32 imask; /* irq mask shadow register */
70 
71 	/*
72 	 * The grgpio core can have multiple "underlying" irqs. The gpio lines
73 	 * can be mapped to any one or none of these underlying irqs
74 	 * independently of each other. This driver sets up an irq domain and
75 	 * hands out separate irqs to each gpio line
76 	 */
77 	struct irq_domain *domain;
78 
79 	/*
80 	 * This array contains information on each underlying irq, each
81 	 * irq of the grgpio core itself.
82 	 */
83 	struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
84 
85 	/*
86 	 * This array contains information for each gpio line on the irqs
87 	 * obtains from this driver. An index value of -1 for a certain gpio
88 	 * line indicates that the line has no irq. Otherwise the index connects
89 	 * the irq to the underlying irq by pointing into the uirqs array.
90 	 */
91 	struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
92 };
93 
94 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
95 			     int val)
96 {
97 	struct gpio_chip *gc = &priv->gc;
98 
99 	if (val)
100 		priv->imask |= BIT(offset);
101 	else
102 		priv->imask &= ~BIT(offset);
103 	gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
104 }
105 
106 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
107 {
108 	struct grgpio_priv *priv = gpiochip_get_data(gc);
109 
110 	if (offset >= gc->ngpio)
111 		return -ENXIO;
112 
113 	if (priv->lirqs[offset].index < 0)
114 		return -ENXIO;
115 
116 	return irq_create_mapping(priv->domain, offset);
117 }
118 
119 /* -------------------- IRQ chip functions -------------------- */
120 
121 static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
122 {
123 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
124 	unsigned long flags;
125 	u32 mask = BIT(d->hwirq);
126 	u32 ipol;
127 	u32 iedge;
128 	u32 pol;
129 	u32 edge;
130 
131 	switch (type) {
132 	case IRQ_TYPE_LEVEL_LOW:
133 		pol = 0;
134 		edge = 0;
135 		break;
136 	case IRQ_TYPE_LEVEL_HIGH:
137 		pol = mask;
138 		edge = 0;
139 		break;
140 	case IRQ_TYPE_EDGE_FALLING:
141 		pol = 0;
142 		edge = mask;
143 		break;
144 	case IRQ_TYPE_EDGE_RISING:
145 		pol = mask;
146 		edge = mask;
147 		break;
148 	default:
149 		return -EINVAL;
150 	}
151 
152 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
153 
154 	ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
155 	iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
156 
157 	priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
158 	priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
159 
160 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
161 
162 	return 0;
163 }
164 
165 static void grgpio_irq_mask(struct irq_data *d)
166 {
167 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
168 	int offset = d->hwirq;
169 	unsigned long flags;
170 
171 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
172 
173 	grgpio_set_imask(priv, offset, 0);
174 
175 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
176 }
177 
178 static void grgpio_irq_unmask(struct irq_data *d)
179 {
180 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
181 	int offset = d->hwirq;
182 	unsigned long flags;
183 
184 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
185 
186 	grgpio_set_imask(priv, offset, 1);
187 
188 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
189 }
190 
191 static struct irq_chip grgpio_irq_chip = {
192 	.name			= "grgpio",
193 	.irq_mask		= grgpio_irq_mask,
194 	.irq_unmask		= grgpio_irq_unmask,
195 	.irq_set_type		= grgpio_irq_set_type,
196 };
197 
198 static irqreturn_t grgpio_irq_handler(int irq, void *dev)
199 {
200 	struct grgpio_priv *priv = dev;
201 	int ngpio = priv->gc.ngpio;
202 	unsigned long flags;
203 	int i;
204 	int match = 0;
205 
206 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
207 
208 	/*
209 	 * For each gpio line, call its interrupt handler if it its underlying
210 	 * irq matches the current irq that is handled.
211 	 */
212 	for (i = 0; i < ngpio; i++) {
213 		struct grgpio_lirq *lirq = &priv->lirqs[i];
214 
215 		if (priv->imask & BIT(i) && lirq->index >= 0 &&
216 		    priv->uirqs[lirq->index].uirq == irq) {
217 			generic_handle_irq(lirq->irq);
218 			match = 1;
219 		}
220 	}
221 
222 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
223 
224 	if (!match)
225 		dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
226 
227 	return IRQ_HANDLED;
228 }
229 
230 /*
231  * This function will be called as a consequence of the call to
232  * irq_create_mapping in grgpio_to_irq
233  */
234 static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
235 			  irq_hw_number_t hwirq)
236 {
237 	struct grgpio_priv *priv = d->host_data;
238 	struct grgpio_lirq *lirq;
239 	struct grgpio_uirq *uirq;
240 	unsigned long flags;
241 	int offset = hwirq;
242 	int ret = 0;
243 
244 	if (!priv)
245 		return -EINVAL;
246 
247 	lirq = &priv->lirqs[offset];
248 	if (lirq->index < 0)
249 		return -EINVAL;
250 
251 	dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
252 		irq, offset);
253 
254 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
255 
256 	/* Request underlying irq if not already requested */
257 	lirq->irq = irq;
258 	uirq = &priv->uirqs[lirq->index];
259 	if (uirq->refcnt == 0) {
260 		ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
261 				  dev_name(priv->dev), priv);
262 		if (ret) {
263 			dev_err(priv->dev,
264 				"Could not request underlying irq %d\n",
265 				uirq->uirq);
266 
267 			spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
268 
269 			return ret;
270 		}
271 	}
272 	uirq->refcnt++;
273 
274 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
275 
276 	/* Setup irq  */
277 	irq_set_chip_data(irq, priv);
278 	irq_set_chip_and_handler(irq, &grgpio_irq_chip,
279 				 handle_simple_irq);
280 	irq_set_noprobe(irq);
281 
282 	return ret;
283 }
284 
285 static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
286 {
287 	struct grgpio_priv *priv = d->host_data;
288 	int index;
289 	struct grgpio_lirq *lirq;
290 	struct grgpio_uirq *uirq;
291 	unsigned long flags;
292 	int ngpio = priv->gc.ngpio;
293 	int i;
294 
295 	irq_set_chip_and_handler(irq, NULL, NULL);
296 	irq_set_chip_data(irq, NULL);
297 
298 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
299 
300 	/* Free underlying irq if last user unmapped */
301 	index = -1;
302 	for (i = 0; i < ngpio; i++) {
303 		lirq = &priv->lirqs[i];
304 		if (lirq->irq == irq) {
305 			grgpio_set_imask(priv, i, 0);
306 			lirq->irq = 0;
307 			index = lirq->index;
308 			break;
309 		}
310 	}
311 	WARN_ON(index < 0);
312 
313 	if (index >= 0) {
314 		uirq = &priv->uirqs[lirq->index];
315 		uirq->refcnt--;
316 		if (uirq->refcnt == 0)
317 			free_irq(uirq->uirq, priv);
318 	}
319 
320 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
321 }
322 
323 static const struct irq_domain_ops grgpio_irq_domain_ops = {
324 	.map	= grgpio_irq_map,
325 	.unmap	= grgpio_irq_unmap,
326 };
327 
328 /* ------------------------------------------------------------ */
329 
330 static int grgpio_probe(struct platform_device *ofdev)
331 {
332 	struct device_node *np = ofdev->dev.of_node;
333 	void  __iomem *regs;
334 	struct gpio_chip *gc;
335 	struct grgpio_priv *priv;
336 	struct resource *res;
337 	int err;
338 	u32 prop;
339 	s32 *irqmap;
340 	int size;
341 	int i;
342 
343 	priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
344 	if (!priv)
345 		return -ENOMEM;
346 
347 	res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
348 	regs = devm_ioremap_resource(&ofdev->dev, res);
349 	if (IS_ERR(regs))
350 		return PTR_ERR(regs);
351 
352 	gc = &priv->gc;
353 	err = bgpio_init(gc, &ofdev->dev, 4, regs + GRGPIO_DATA,
354 			 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
355 			 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
356 	if (err) {
357 		dev_err(&ofdev->dev, "bgpio_init() failed\n");
358 		return err;
359 	}
360 
361 	priv->regs = regs;
362 	priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
363 	priv->dev = &ofdev->dev;
364 
365 	gc->of_node = np;
366 	gc->owner = THIS_MODULE;
367 	gc->to_irq = grgpio_to_irq;
368 	gc->label = devm_kasprintf(&ofdev->dev, GFP_KERNEL, "%pOF", np);
369 	gc->base = -1;
370 
371 	err = of_property_read_u32(np, "nbits", &prop);
372 	if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
373 		gc->ngpio = GRGPIO_MAX_NGPIO;
374 		dev_dbg(&ofdev->dev,
375 			"No or invalid nbits property: assume %d\n", gc->ngpio);
376 	} else {
377 		gc->ngpio = prop;
378 	}
379 
380 	/*
381 	 * The irqmap contains the index values indicating which underlying irq,
382 	 * if anyone, is connected to that line
383 	 */
384 	irqmap = (s32 *)of_get_property(np, "irqmap", &size);
385 	if (irqmap) {
386 		if (size < gc->ngpio) {
387 			dev_err(&ofdev->dev,
388 				"irqmap shorter than ngpio (%d < %d)\n",
389 				size, gc->ngpio);
390 			return -EINVAL;
391 		}
392 
393 		priv->domain = irq_domain_add_linear(np, gc->ngpio,
394 						     &grgpio_irq_domain_ops,
395 						     priv);
396 		if (!priv->domain) {
397 			dev_err(&ofdev->dev, "Could not add irq domain\n");
398 			return -EINVAL;
399 		}
400 
401 		for (i = 0; i < gc->ngpio; i++) {
402 			struct grgpio_lirq *lirq;
403 			int ret;
404 
405 			lirq = &priv->lirqs[i];
406 			lirq->index = irqmap[i];
407 
408 			if (lirq->index < 0)
409 				continue;
410 
411 			ret = platform_get_irq(ofdev, lirq->index);
412 			if (ret <= 0) {
413 				/*
414 				 * Continue without irq functionality for that
415 				 * gpio line
416 				 */
417 				dev_err(priv->dev,
418 					"Failed to get irq for offset %d\n", i);
419 				continue;
420 			}
421 			priv->uirqs[lirq->index].uirq = ret;
422 		}
423 	}
424 
425 	platform_set_drvdata(ofdev, priv);
426 
427 	err = gpiochip_add_data(gc, priv);
428 	if (err) {
429 		dev_err(&ofdev->dev, "Could not add gpiochip\n");
430 		if (priv->domain)
431 			irq_domain_remove(priv->domain);
432 		return err;
433 	}
434 
435 	dev_info(&ofdev->dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
436 		 priv->regs, gc->base, gc->ngpio, priv->domain ? "on" : "off");
437 
438 	return 0;
439 }
440 
441 static int grgpio_remove(struct platform_device *ofdev)
442 {
443 	struct grgpio_priv *priv = platform_get_drvdata(ofdev);
444 	unsigned long flags;
445 	int i;
446 	int ret = 0;
447 
448 	spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
449 
450 	if (priv->domain) {
451 		for (i = 0; i < GRGPIO_MAX_NGPIO; i++) {
452 			if (priv->uirqs[i].refcnt != 0) {
453 				ret = -EBUSY;
454 				goto out;
455 			}
456 		}
457 	}
458 
459 	gpiochip_remove(&priv->gc);
460 
461 	if (priv->domain)
462 		irq_domain_remove(priv->domain);
463 
464 out:
465 	spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
466 
467 	return ret;
468 }
469 
470 static const struct of_device_id grgpio_match[] = {
471 	{.name = "GAISLER_GPIO"},
472 	{.name = "01_01a"},
473 	{},
474 };
475 
476 MODULE_DEVICE_TABLE(of, grgpio_match);
477 
478 static struct platform_driver grgpio_driver = {
479 	.driver = {
480 		.name = "grgpio",
481 		.of_match_table = grgpio_match,
482 	},
483 	.probe = grgpio_probe,
484 	.remove = grgpio_remove,
485 };
486 module_platform_driver(grgpio_driver);
487 
488 MODULE_AUTHOR("Aeroflex Gaisler AB.");
489 MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
490 MODULE_LICENSE("GPL");
491