1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Faraday Technolog FTGPIO010 gpiochip and interrupt routines 4 * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org> 5 * 6 * Based on arch/arm/mach-gemini/gpio.c: 7 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> 8 * 9 * Based on plat-mxc/gpio.c: 10 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 11 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 12 */ 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/interrupt.h> 16 #include <linux/platform_device.h> 17 #include <linux/bitops.h> 18 #include <linux/clk.h> 19 20 /* GPIO registers definition */ 21 #define GPIO_DATA_OUT 0x00 22 #define GPIO_DATA_IN 0x04 23 #define GPIO_DIR 0x08 24 #define GPIO_BYPASS_IN 0x0C 25 #define GPIO_DATA_SET 0x10 26 #define GPIO_DATA_CLR 0x14 27 #define GPIO_PULL_EN 0x18 28 #define GPIO_PULL_TYPE 0x1C 29 #define GPIO_INT_EN 0x20 30 #define GPIO_INT_STAT_RAW 0x24 31 #define GPIO_INT_STAT_MASKED 0x28 32 #define GPIO_INT_MASK 0x2C 33 #define GPIO_INT_CLR 0x30 34 #define GPIO_INT_TYPE 0x34 35 #define GPIO_INT_BOTH_EDGE 0x38 36 #define GPIO_INT_LEVEL 0x3C 37 #define GPIO_DEBOUNCE_EN 0x40 38 #define GPIO_DEBOUNCE_PRESCALE 0x44 39 40 /** 41 * struct ftgpio_gpio - Gemini GPIO state container 42 * @dev: containing device for this instance 43 * @gc: gpiochip for this instance 44 * @irq: irqchip for this instance 45 * @base: remapped I/O-memory base 46 * @clk: silicon clock 47 */ 48 struct ftgpio_gpio { 49 struct device *dev; 50 struct gpio_chip gc; 51 struct irq_chip irq; 52 void __iomem *base; 53 struct clk *clk; 54 }; 55 56 static void ftgpio_gpio_ack_irq(struct irq_data *d) 57 { 58 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 59 struct ftgpio_gpio *g = gpiochip_get_data(gc); 60 61 writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR); 62 } 63 64 static void ftgpio_gpio_mask_irq(struct irq_data *d) 65 { 66 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 67 struct ftgpio_gpio *g = gpiochip_get_data(gc); 68 u32 val; 69 70 val = readl(g->base + GPIO_INT_EN); 71 val &= ~BIT(irqd_to_hwirq(d)); 72 writel(val, g->base + GPIO_INT_EN); 73 } 74 75 static void ftgpio_gpio_unmask_irq(struct irq_data *d) 76 { 77 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 78 struct ftgpio_gpio *g = gpiochip_get_data(gc); 79 u32 val; 80 81 val = readl(g->base + GPIO_INT_EN); 82 val |= BIT(irqd_to_hwirq(d)); 83 writel(val, g->base + GPIO_INT_EN); 84 } 85 86 static int ftgpio_gpio_set_irq_type(struct irq_data *d, unsigned int type) 87 { 88 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 89 struct ftgpio_gpio *g = gpiochip_get_data(gc); 90 u32 mask = BIT(irqd_to_hwirq(d)); 91 u32 reg_both, reg_level, reg_type; 92 93 reg_type = readl(g->base + GPIO_INT_TYPE); 94 reg_level = readl(g->base + GPIO_INT_LEVEL); 95 reg_both = readl(g->base + GPIO_INT_BOTH_EDGE); 96 97 switch (type) { 98 case IRQ_TYPE_EDGE_BOTH: 99 irq_set_handler_locked(d, handle_edge_irq); 100 reg_type &= ~mask; 101 reg_both |= mask; 102 break; 103 case IRQ_TYPE_EDGE_RISING: 104 irq_set_handler_locked(d, handle_edge_irq); 105 reg_type &= ~mask; 106 reg_both &= ~mask; 107 reg_level &= ~mask; 108 break; 109 case IRQ_TYPE_EDGE_FALLING: 110 irq_set_handler_locked(d, handle_edge_irq); 111 reg_type &= ~mask; 112 reg_both &= ~mask; 113 reg_level |= mask; 114 break; 115 case IRQ_TYPE_LEVEL_HIGH: 116 irq_set_handler_locked(d, handle_level_irq); 117 reg_type |= mask; 118 reg_level &= ~mask; 119 break; 120 case IRQ_TYPE_LEVEL_LOW: 121 irq_set_handler_locked(d, handle_level_irq); 122 reg_type |= mask; 123 reg_level |= mask; 124 break; 125 default: 126 irq_set_handler_locked(d, handle_bad_irq); 127 return -EINVAL; 128 } 129 130 writel(reg_type, g->base + GPIO_INT_TYPE); 131 writel(reg_level, g->base + GPIO_INT_LEVEL); 132 writel(reg_both, g->base + GPIO_INT_BOTH_EDGE); 133 134 ftgpio_gpio_ack_irq(d); 135 136 return 0; 137 } 138 139 static void ftgpio_gpio_irq_handler(struct irq_desc *desc) 140 { 141 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 142 struct ftgpio_gpio *g = gpiochip_get_data(gc); 143 struct irq_chip *irqchip = irq_desc_get_chip(desc); 144 int offset; 145 unsigned long stat; 146 147 chained_irq_enter(irqchip, desc); 148 149 stat = readl(g->base + GPIO_INT_STAT_RAW); 150 if (stat) 151 for_each_set_bit(offset, &stat, gc->ngpio) 152 generic_handle_irq(irq_find_mapping(gc->irq.domain, 153 offset)); 154 155 chained_irq_exit(irqchip, desc); 156 } 157 158 static int ftgpio_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 159 unsigned long config) 160 { 161 enum pin_config_param param = pinconf_to_config_param(config); 162 u32 arg = pinconf_to_config_argument(config); 163 struct ftgpio_gpio *g = gpiochip_get_data(gc); 164 unsigned long pclk_freq; 165 u32 deb_div; 166 u32 val; 167 168 if (param != PIN_CONFIG_INPUT_DEBOUNCE) 169 return -ENOTSUPP; 170 171 /* 172 * Debounce only works if interrupts are enabled. The manual 173 * states that if PCLK is 66 MHz, and this is set to 0x7D0, then 174 * PCLK is divided down to 33 kHz for the debounce timer. 0x7D0 is 175 * 2000 decimal, so what they mean is simply that the PCLK is 176 * divided by this value. 177 * 178 * As we get a debounce setting in microseconds, we calculate the 179 * desired period time and see if we can get a suitable debounce 180 * time. 181 */ 182 pclk_freq = clk_get_rate(g->clk); 183 deb_div = DIV_ROUND_CLOSEST(pclk_freq, arg); 184 185 /* This register is only 24 bits wide */ 186 if (deb_div > (1 << 24)) 187 return -ENOTSUPP; 188 189 dev_dbg(g->dev, "prescale divisor: %08x, resulting frequency %lu Hz\n", 190 deb_div, (pclk_freq/deb_div)); 191 192 val = readl(g->base + GPIO_DEBOUNCE_PRESCALE); 193 if (val == deb_div) { 194 /* 195 * The debounce timer happens to already be set to the 196 * desireable value, what a coincidence! We can just enable 197 * debounce on this GPIO line and return. This happens more 198 * often than you think, for example when all GPIO keys 199 * on a system are requesting the same debounce interval. 200 */ 201 val = readl(g->base + GPIO_DEBOUNCE_EN); 202 val |= BIT(offset); 203 writel(val, g->base + GPIO_DEBOUNCE_EN); 204 return 0; 205 } 206 207 val = readl(g->base + GPIO_DEBOUNCE_EN); 208 if (val) { 209 /* 210 * Oh no! Someone is already using the debounce with 211 * another setting than what we need. Bummer. 212 */ 213 return -ENOTSUPP; 214 } 215 216 /* First come, first serve */ 217 writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE); 218 /* Enable debounce */ 219 val |= BIT(offset); 220 writel(val, g->base + GPIO_DEBOUNCE_EN); 221 222 return 0; 223 } 224 225 static int ftgpio_gpio_probe(struct platform_device *pdev) 226 { 227 struct device *dev = &pdev->dev; 228 struct ftgpio_gpio *g; 229 struct gpio_irq_chip *girq; 230 int irq; 231 int ret; 232 233 g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); 234 if (!g) 235 return -ENOMEM; 236 237 g->dev = dev; 238 239 g->base = devm_platform_ioremap_resource(pdev, 0); 240 if (IS_ERR(g->base)) 241 return PTR_ERR(g->base); 242 243 irq = platform_get_irq(pdev, 0); 244 if (irq <= 0) 245 return irq ? irq : -EINVAL; 246 247 g->clk = devm_clk_get(dev, NULL); 248 if (!IS_ERR(g->clk)) { 249 ret = clk_prepare_enable(g->clk); 250 if (ret) 251 return ret; 252 } else if (PTR_ERR(g->clk) == -EPROBE_DEFER) { 253 /* 254 * Percolate deferrals, for anything else, 255 * just live without the clocking. 256 */ 257 return PTR_ERR(g->clk); 258 } 259 260 ret = bgpio_init(&g->gc, dev, 4, 261 g->base + GPIO_DATA_IN, 262 g->base + GPIO_DATA_SET, 263 g->base + GPIO_DATA_CLR, 264 g->base + GPIO_DIR, 265 NULL, 266 0); 267 if (ret) { 268 dev_err(dev, "unable to init generic GPIO\n"); 269 goto dis_clk; 270 } 271 g->gc.label = "FTGPIO010"; 272 g->gc.base = -1; 273 g->gc.parent = dev; 274 g->gc.owner = THIS_MODULE; 275 /* ngpio is set by bgpio_init() */ 276 277 /* We need a silicon clock to do debounce */ 278 if (!IS_ERR(g->clk)) 279 g->gc.set_config = ftgpio_gpio_set_config; 280 281 g->irq.name = "FTGPIO010"; 282 g->irq.irq_ack = ftgpio_gpio_ack_irq; 283 g->irq.irq_mask = ftgpio_gpio_mask_irq; 284 g->irq.irq_unmask = ftgpio_gpio_unmask_irq; 285 g->irq.irq_set_type = ftgpio_gpio_set_irq_type; 286 287 girq = &g->gc.irq; 288 girq->chip = &g->irq; 289 girq->parent_handler = ftgpio_gpio_irq_handler; 290 girq->num_parents = 1; 291 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 292 GFP_KERNEL); 293 if (!girq->parents) { 294 ret = -ENOMEM; 295 goto dis_clk; 296 } 297 girq->default_type = IRQ_TYPE_NONE; 298 girq->handler = handle_bad_irq; 299 girq->parents[0] = irq; 300 301 /* Disable, unmask and clear all interrupts */ 302 writel(0x0, g->base + GPIO_INT_EN); 303 writel(0x0, g->base + GPIO_INT_MASK); 304 writel(~0x0, g->base + GPIO_INT_CLR); 305 306 /* Clear any use of debounce */ 307 writel(0x0, g->base + GPIO_DEBOUNCE_EN); 308 309 ret = devm_gpiochip_add_data(dev, &g->gc, g); 310 if (ret) 311 goto dis_clk; 312 313 platform_set_drvdata(pdev, g); 314 dev_info(dev, "FTGPIO010 @%p registered\n", g->base); 315 316 return 0; 317 318 dis_clk: 319 if (!IS_ERR(g->clk)) 320 clk_disable_unprepare(g->clk); 321 return ret; 322 } 323 324 static int ftgpio_gpio_remove(struct platform_device *pdev) 325 { 326 struct ftgpio_gpio *g = platform_get_drvdata(pdev); 327 328 if (!IS_ERR(g->clk)) 329 clk_disable_unprepare(g->clk); 330 return 0; 331 } 332 333 static const struct of_device_id ftgpio_gpio_of_match[] = { 334 { 335 .compatible = "cortina,gemini-gpio", 336 }, 337 { 338 .compatible = "moxa,moxart-gpio", 339 }, 340 { 341 .compatible = "faraday,ftgpio010", 342 }, 343 {}, 344 }; 345 346 static struct platform_driver ftgpio_gpio_driver = { 347 .driver = { 348 .name = "ftgpio010-gpio", 349 .of_match_table = of_match_ptr(ftgpio_gpio_of_match), 350 }, 351 .probe = ftgpio_gpio_probe, 352 .remove = ftgpio_gpio_remove, 353 }; 354 builtin_platform_driver(ftgpio_gpio_driver); 355