1 /* 2 * Generic EP93xx GPIO handling 3 * 4 * Copyright (c) 2008 Ryan Mallon 5 * Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com> 6 * 7 * Based on code originally from: 8 * linux/arch/arm/mach-ep93xx/core.c 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/gpio.h> 20 #include <linux/irq.h> 21 #include <linux/slab.h> 22 #include <linux/basic_mmio_gpio.h> 23 24 #include <mach/hardware.h> 25 #include <mach/gpio-ep93xx.h> 26 27 #define irq_to_gpio(irq) ((irq) - gpio_to_irq(0)) 28 29 struct ep93xx_gpio { 30 void __iomem *mmio_base; 31 struct bgpio_chip bgc[8]; 32 }; 33 34 /************************************************************************* 35 * Interrupt handling for EP93xx on-chip GPIOs 36 *************************************************************************/ 37 static unsigned char gpio_int_unmasked[3]; 38 static unsigned char gpio_int_enabled[3]; 39 static unsigned char gpio_int_type1[3]; 40 static unsigned char gpio_int_type2[3]; 41 static unsigned char gpio_int_debounce[3]; 42 43 /* Port ordering is: A B F */ 44 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c }; 45 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 }; 46 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 }; 47 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x58 }; 48 static const u8 int_debounce_register_offset[3] = { 0xa8, 0xc4, 0x64 }; 49 50 static void ep93xx_gpio_update_int_params(unsigned port) 51 { 52 BUG_ON(port > 2); 53 54 writeb_relaxed(0, EP93XX_GPIO_REG(int_en_register_offset[port])); 55 56 writeb_relaxed(gpio_int_type2[port], 57 EP93XX_GPIO_REG(int_type2_register_offset[port])); 58 59 writeb_relaxed(gpio_int_type1[port], 60 EP93XX_GPIO_REG(int_type1_register_offset[port])); 61 62 writeb(gpio_int_unmasked[port] & gpio_int_enabled[port], 63 EP93XX_GPIO_REG(int_en_register_offset[port])); 64 } 65 66 static void ep93xx_gpio_int_debounce(unsigned int irq, bool enable) 67 { 68 int line = irq_to_gpio(irq); 69 int port = line >> 3; 70 int port_mask = 1 << (line & 7); 71 72 if (enable) 73 gpio_int_debounce[port] |= port_mask; 74 else 75 gpio_int_debounce[port] &= ~port_mask; 76 77 writeb(gpio_int_debounce[port], 78 EP93XX_GPIO_REG(int_debounce_register_offset[port])); 79 } 80 81 static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc) 82 { 83 unsigned char status; 84 int i; 85 86 status = readb(EP93XX_GPIO_A_INT_STATUS); 87 for (i = 0; i < 8; i++) { 88 if (status & (1 << i)) { 89 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i; 90 generic_handle_irq(gpio_irq); 91 } 92 } 93 94 status = readb(EP93XX_GPIO_B_INT_STATUS); 95 for (i = 0; i < 8; i++) { 96 if (status & (1 << i)) { 97 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i; 98 generic_handle_irq(gpio_irq); 99 } 100 } 101 } 102 103 static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc) 104 { 105 /* 106 * map discontiguous hw irq range to continuous sw irq range: 107 * 108 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7}) 109 */ 110 unsigned int irq = irq_desc_get_irq(desc); 111 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */ 112 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx; 113 114 generic_handle_irq(gpio_irq); 115 } 116 117 static void ep93xx_gpio_irq_ack(struct irq_data *d) 118 { 119 int line = irq_to_gpio(d->irq); 120 int port = line >> 3; 121 int port_mask = 1 << (line & 7); 122 123 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { 124 gpio_int_type2[port] ^= port_mask; /* switch edge direction */ 125 ep93xx_gpio_update_int_params(port); 126 } 127 128 writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); 129 } 130 131 static void ep93xx_gpio_irq_mask_ack(struct irq_data *d) 132 { 133 int line = irq_to_gpio(d->irq); 134 int port = line >> 3; 135 int port_mask = 1 << (line & 7); 136 137 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) 138 gpio_int_type2[port] ^= port_mask; /* switch edge direction */ 139 140 gpio_int_unmasked[port] &= ~port_mask; 141 ep93xx_gpio_update_int_params(port); 142 143 writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port])); 144 } 145 146 static void ep93xx_gpio_irq_mask(struct irq_data *d) 147 { 148 int line = irq_to_gpio(d->irq); 149 int port = line >> 3; 150 151 gpio_int_unmasked[port] &= ~(1 << (line & 7)); 152 ep93xx_gpio_update_int_params(port); 153 } 154 155 static void ep93xx_gpio_irq_unmask(struct irq_data *d) 156 { 157 int line = irq_to_gpio(d->irq); 158 int port = line >> 3; 159 160 gpio_int_unmasked[port] |= 1 << (line & 7); 161 ep93xx_gpio_update_int_params(port); 162 } 163 164 /* 165 * gpio_int_type1 controls whether the interrupt is level (0) or 166 * edge (1) triggered, while gpio_int_type2 controls whether it 167 * triggers on low/falling (0) or high/rising (1). 168 */ 169 static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type) 170 { 171 const int gpio = irq_to_gpio(d->irq); 172 const int port = gpio >> 3; 173 const int port_mask = 1 << (gpio & 7); 174 irq_flow_handler_t handler; 175 176 gpio_direction_input(gpio); 177 178 switch (type) { 179 case IRQ_TYPE_EDGE_RISING: 180 gpio_int_type1[port] |= port_mask; 181 gpio_int_type2[port] |= port_mask; 182 handler = handle_edge_irq; 183 break; 184 case IRQ_TYPE_EDGE_FALLING: 185 gpio_int_type1[port] |= port_mask; 186 gpio_int_type2[port] &= ~port_mask; 187 handler = handle_edge_irq; 188 break; 189 case IRQ_TYPE_LEVEL_HIGH: 190 gpio_int_type1[port] &= ~port_mask; 191 gpio_int_type2[port] |= port_mask; 192 handler = handle_level_irq; 193 break; 194 case IRQ_TYPE_LEVEL_LOW: 195 gpio_int_type1[port] &= ~port_mask; 196 gpio_int_type2[port] &= ~port_mask; 197 handler = handle_level_irq; 198 break; 199 case IRQ_TYPE_EDGE_BOTH: 200 gpio_int_type1[port] |= port_mask; 201 /* set initial polarity based on current input level */ 202 if (gpio_get_value(gpio)) 203 gpio_int_type2[port] &= ~port_mask; /* falling */ 204 else 205 gpio_int_type2[port] |= port_mask; /* rising */ 206 handler = handle_edge_irq; 207 break; 208 default: 209 return -EINVAL; 210 } 211 212 irq_set_handler_locked(d, handler); 213 214 gpio_int_enabled[port] |= port_mask; 215 216 ep93xx_gpio_update_int_params(port); 217 218 return 0; 219 } 220 221 static struct irq_chip ep93xx_gpio_irq_chip = { 222 .name = "GPIO", 223 .irq_ack = ep93xx_gpio_irq_ack, 224 .irq_mask_ack = ep93xx_gpio_irq_mask_ack, 225 .irq_mask = ep93xx_gpio_irq_mask, 226 .irq_unmask = ep93xx_gpio_irq_unmask, 227 .irq_set_type = ep93xx_gpio_irq_type, 228 }; 229 230 static void ep93xx_gpio_init_irq(void) 231 { 232 int gpio_irq; 233 234 for (gpio_irq = gpio_to_irq(0); 235 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { 236 irq_set_chip_and_handler(gpio_irq, &ep93xx_gpio_irq_chip, 237 handle_level_irq); 238 irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST); 239 } 240 241 irq_set_chained_handler(IRQ_EP93XX_GPIO_AB, 242 ep93xx_gpio_ab_irq_handler); 243 irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX, 244 ep93xx_gpio_f_irq_handler); 245 irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX, 246 ep93xx_gpio_f_irq_handler); 247 irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX, 248 ep93xx_gpio_f_irq_handler); 249 irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX, 250 ep93xx_gpio_f_irq_handler); 251 irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX, 252 ep93xx_gpio_f_irq_handler); 253 irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX, 254 ep93xx_gpio_f_irq_handler); 255 irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX, 256 ep93xx_gpio_f_irq_handler); 257 irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX, 258 ep93xx_gpio_f_irq_handler); 259 } 260 261 262 /************************************************************************* 263 * gpiolib interface for EP93xx on-chip GPIOs 264 *************************************************************************/ 265 struct ep93xx_gpio_bank { 266 const char *label; 267 int data; 268 int dir; 269 int base; 270 bool has_debounce; 271 }; 272 273 #define EP93XX_GPIO_BANK(_label, _data, _dir, _base, _debounce) \ 274 { \ 275 .label = _label, \ 276 .data = _data, \ 277 .dir = _dir, \ 278 .base = _base, \ 279 .has_debounce = _debounce, \ 280 } 281 282 static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = { 283 EP93XX_GPIO_BANK("A", 0x00, 0x10, 0, true), 284 EP93XX_GPIO_BANK("B", 0x04, 0x14, 8, true), 285 EP93XX_GPIO_BANK("C", 0x08, 0x18, 40, false), 286 EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 24, false), 287 EP93XX_GPIO_BANK("E", 0x20, 0x24, 32, false), 288 EP93XX_GPIO_BANK("F", 0x30, 0x34, 16, true), 289 EP93XX_GPIO_BANK("G", 0x38, 0x3c, 48, false), 290 EP93XX_GPIO_BANK("H", 0x40, 0x44, 56, false), 291 }; 292 293 static int ep93xx_gpio_set_debounce(struct gpio_chip *chip, 294 unsigned offset, unsigned debounce) 295 { 296 int gpio = chip->base + offset; 297 int irq = gpio_to_irq(gpio); 298 299 if (irq < 0) 300 return -EINVAL; 301 302 ep93xx_gpio_int_debounce(irq, debounce ? true : false); 303 304 return 0; 305 } 306 307 /* 308 * Map GPIO A0..A7 (0..7) to irq 64..71, 309 * B0..B7 (7..15) to irq 72..79, and 310 * F0..F7 (16..24) to irq 80..87. 311 */ 312 static int ep93xx_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 313 { 314 int gpio = chip->base + offset; 315 316 if (gpio > EP93XX_GPIO_LINE_MAX_IRQ) 317 return -EINVAL; 318 319 return 64 + gpio; 320 } 321 322 static int ep93xx_gpio_add_bank(struct bgpio_chip *bgc, struct device *dev, 323 void __iomem *mmio_base, struct ep93xx_gpio_bank *bank) 324 { 325 void __iomem *data = mmio_base + bank->data; 326 void __iomem *dir = mmio_base + bank->dir; 327 int err; 328 329 err = bgpio_init(bgc, dev, 1, data, NULL, NULL, dir, NULL, 0); 330 if (err) 331 return err; 332 333 bgc->gc.label = bank->label; 334 bgc->gc.base = bank->base; 335 336 if (bank->has_debounce) { 337 bgc->gc.set_debounce = ep93xx_gpio_set_debounce; 338 bgc->gc.to_irq = ep93xx_gpio_to_irq; 339 } 340 341 return gpiochip_add(&bgc->gc); 342 } 343 344 static int ep93xx_gpio_probe(struct platform_device *pdev) 345 { 346 struct ep93xx_gpio *ep93xx_gpio; 347 struct resource *res; 348 int i; 349 struct device *dev = &pdev->dev; 350 351 ep93xx_gpio = devm_kzalloc(dev, sizeof(struct ep93xx_gpio), GFP_KERNEL); 352 if (!ep93xx_gpio) 353 return -ENOMEM; 354 355 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 356 ep93xx_gpio->mmio_base = devm_ioremap_resource(dev, res); 357 if (IS_ERR(ep93xx_gpio->mmio_base)) 358 return PTR_ERR(ep93xx_gpio->mmio_base); 359 360 for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) { 361 struct bgpio_chip *bgc = &ep93xx_gpio->bgc[i]; 362 struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i]; 363 364 if (ep93xx_gpio_add_bank(bgc, &pdev->dev, 365 ep93xx_gpio->mmio_base, bank)) 366 dev_warn(&pdev->dev, "Unable to add gpio bank %s\n", 367 bank->label); 368 } 369 370 ep93xx_gpio_init_irq(); 371 372 return 0; 373 } 374 375 static struct platform_driver ep93xx_gpio_driver = { 376 .driver = { 377 .name = "gpio-ep93xx", 378 }, 379 .probe = ep93xx_gpio_probe, 380 }; 381 382 static int __init ep93xx_gpio_init(void) 383 { 384 return platform_driver_register(&ep93xx_gpio_driver); 385 } 386 postcore_initcall(ep93xx_gpio_init); 387 388 MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> " 389 "H Hartley Sweeten <hsweeten@visionengravers.com>"); 390 MODULE_DESCRIPTION("EP93XX GPIO driver"); 391 MODULE_LICENSE("GPL"); 392