1 /* 2 * Emma Mobile GPIO Support - GIO 3 * 4 * Copyright (C) 2012 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/ioport.h> 25 #include <linux/io.h> 26 #include <linux/irq.h> 27 #include <linux/irqdomain.h> 28 #include <linux/bitops.h> 29 #include <linux/err.h> 30 #include <linux/gpio/driver.h> 31 #include <linux/slab.h> 32 #include <linux/module.h> 33 #include <linux/pinctrl/consumer.h> 34 35 struct em_gio_priv { 36 void __iomem *base0; 37 void __iomem *base1; 38 spinlock_t sense_lock; 39 struct platform_device *pdev; 40 struct gpio_chip gpio_chip; 41 struct irq_chip irq_chip; 42 struct irq_domain *irq_domain; 43 }; 44 45 #define GIO_E1 0x00 46 #define GIO_E0 0x04 47 #define GIO_EM 0x04 48 #define GIO_OL 0x08 49 #define GIO_OH 0x0c 50 #define GIO_I 0x10 51 #define GIO_IIA 0x14 52 #define GIO_IEN 0x18 53 #define GIO_IDS 0x1c 54 #define GIO_IIM 0x1c 55 #define GIO_RAW 0x20 56 #define GIO_MST 0x24 57 #define GIO_IIR 0x28 58 59 #define GIO_IDT0 0x40 60 #define GIO_IDT1 0x44 61 #define GIO_IDT2 0x48 62 #define GIO_IDT3 0x4c 63 #define GIO_RAWBL 0x50 64 #define GIO_RAWBH 0x54 65 #define GIO_IRBL 0x58 66 #define GIO_IRBH 0x5c 67 68 #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4)) 69 70 static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs) 71 { 72 if (offs < GIO_IDT0) 73 return ioread32(p->base0 + offs); 74 else 75 return ioread32(p->base1 + (offs - GIO_IDT0)); 76 } 77 78 static inline void em_gio_write(struct em_gio_priv *p, int offs, 79 unsigned long value) 80 { 81 if (offs < GIO_IDT0) 82 iowrite32(value, p->base0 + offs); 83 else 84 iowrite32(value, p->base1 + (offs - GIO_IDT0)); 85 } 86 87 static void em_gio_irq_disable(struct irq_data *d) 88 { 89 struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 90 91 em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d))); 92 } 93 94 static void em_gio_irq_enable(struct irq_data *d) 95 { 96 struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 97 98 em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d))); 99 } 100 101 static int em_gio_irq_reqres(struct irq_data *d) 102 { 103 struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 104 int ret; 105 106 ret = gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); 107 if (ret) { 108 dev_err(p->gpio_chip.parent, 109 "unable to lock HW IRQ %lu for IRQ\n", 110 irqd_to_hwirq(d)); 111 return ret; 112 } 113 return 0; 114 } 115 116 static void em_gio_irq_relres(struct irq_data *d) 117 { 118 struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 119 120 gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); 121 } 122 123 124 #define GIO_ASYNC(x) (x + 8) 125 126 static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { 127 [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00), 128 [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01), 129 [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02), 130 [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03), 131 [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04), 132 }; 133 134 static int em_gio_irq_set_type(struct irq_data *d, unsigned int type) 135 { 136 unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK]; 137 struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 138 unsigned int reg, offset, shift; 139 unsigned long flags; 140 unsigned long tmp; 141 142 if (!value) 143 return -EINVAL; 144 145 offset = irqd_to_hwirq(d); 146 147 pr_debug("gio: sense irq = %d, mode = %d\n", offset, value); 148 149 /* 8 x 4 bit fields in 4 IDT registers */ 150 reg = GIO_IDT(offset >> 3); 151 shift = (offset & 0x07) << 4; 152 153 spin_lock_irqsave(&p->sense_lock, flags); 154 155 /* disable the interrupt in IIA */ 156 tmp = em_gio_read(p, GIO_IIA); 157 tmp &= ~BIT(offset); 158 em_gio_write(p, GIO_IIA, tmp); 159 160 /* change the sense setting in IDT */ 161 tmp = em_gio_read(p, reg); 162 tmp &= ~(0xf << shift); 163 tmp |= value << shift; 164 em_gio_write(p, reg, tmp); 165 166 /* clear pending interrupts */ 167 em_gio_write(p, GIO_IIR, BIT(offset)); 168 169 /* enable the interrupt in IIA */ 170 tmp = em_gio_read(p, GIO_IIA); 171 tmp |= BIT(offset); 172 em_gio_write(p, GIO_IIA, tmp); 173 174 spin_unlock_irqrestore(&p->sense_lock, flags); 175 176 return 0; 177 } 178 179 static irqreturn_t em_gio_irq_handler(int irq, void *dev_id) 180 { 181 struct em_gio_priv *p = dev_id; 182 unsigned long pending; 183 unsigned int offset, irqs_handled = 0; 184 185 while ((pending = em_gio_read(p, GIO_MST))) { 186 offset = __ffs(pending); 187 em_gio_write(p, GIO_IIR, BIT(offset)); 188 generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); 189 irqs_handled++; 190 } 191 192 return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 193 } 194 195 static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip) 196 { 197 return gpiochip_get_data(chip); 198 } 199 200 static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset) 201 { 202 em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset)); 203 return 0; 204 } 205 206 static int em_gio_get(struct gpio_chip *chip, unsigned offset) 207 { 208 return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset)); 209 } 210 211 static void __em_gio_set(struct gpio_chip *chip, unsigned int reg, 212 unsigned shift, int value) 213 { 214 /* upper 16 bits contains mask and lower 16 actual value */ 215 em_gio_write(gpio_to_priv(chip), reg, 216 (BIT(shift + 16)) | (value << shift)); 217 } 218 219 static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value) 220 { 221 /* output is split into two registers */ 222 if (offset < 16) 223 __em_gio_set(chip, GIO_OL, offset, value); 224 else 225 __em_gio_set(chip, GIO_OH, offset - 16, value); 226 } 227 228 static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset, 229 int value) 230 { 231 /* write GPIO value to output before selecting output mode of pin */ 232 em_gio_set(chip, offset, value); 233 em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset)); 234 return 0; 235 } 236 237 static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset) 238 { 239 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); 240 } 241 242 static int em_gio_request(struct gpio_chip *chip, unsigned offset) 243 { 244 return pinctrl_gpio_request(chip->base + offset); 245 } 246 247 static void em_gio_free(struct gpio_chip *chip, unsigned offset) 248 { 249 pinctrl_gpio_free(chip->base + offset); 250 251 /* Set the GPIO as an input to ensure that the next GPIO request won't 252 * drive the GPIO pin as an output. 253 */ 254 em_gio_direction_input(chip, offset); 255 } 256 257 static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq, 258 irq_hw_number_t hwirq) 259 { 260 struct em_gio_priv *p = h->host_data; 261 262 pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq); 263 264 irq_set_chip_data(irq, h->host_data); 265 irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq); 266 return 0; 267 } 268 269 static const struct irq_domain_ops em_gio_irq_domain_ops = { 270 .map = em_gio_irq_domain_map, 271 .xlate = irq_domain_xlate_twocell, 272 }; 273 274 static int em_gio_probe(struct platform_device *pdev) 275 { 276 struct em_gio_priv *p; 277 struct resource *io[2], *irq[2]; 278 struct gpio_chip *gpio_chip; 279 struct irq_chip *irq_chip; 280 const char *name = dev_name(&pdev->dev); 281 unsigned int ngpios; 282 int ret; 283 284 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); 285 if (!p) 286 return -ENOMEM; 287 288 p->pdev = pdev; 289 platform_set_drvdata(pdev, p); 290 spin_lock_init(&p->sense_lock); 291 292 io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0); 293 io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1); 294 irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 295 irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 296 297 if (!io[0] || !io[1] || !irq[0] || !irq[1]) { 298 dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); 299 return -EINVAL; 300 } 301 302 p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start, 303 resource_size(io[0])); 304 if (!p->base0) 305 return -ENOMEM; 306 307 p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start, 308 resource_size(io[1])); 309 if (!p->base1) 310 return -ENOMEM; 311 312 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 313 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 314 return -EINVAL; 315 } 316 317 gpio_chip = &p->gpio_chip; 318 gpio_chip->of_node = pdev->dev.of_node; 319 gpio_chip->direction_input = em_gio_direction_input; 320 gpio_chip->get = em_gio_get; 321 gpio_chip->direction_output = em_gio_direction_output; 322 gpio_chip->set = em_gio_set; 323 gpio_chip->to_irq = em_gio_to_irq; 324 gpio_chip->request = em_gio_request; 325 gpio_chip->free = em_gio_free; 326 gpio_chip->label = name; 327 gpio_chip->parent = &pdev->dev; 328 gpio_chip->owner = THIS_MODULE; 329 gpio_chip->base = -1; 330 gpio_chip->ngpio = ngpios; 331 332 irq_chip = &p->irq_chip; 333 irq_chip->name = name; 334 irq_chip->irq_mask = em_gio_irq_disable; 335 irq_chip->irq_unmask = em_gio_irq_enable; 336 irq_chip->irq_set_type = em_gio_irq_set_type; 337 irq_chip->irq_request_resources = em_gio_irq_reqres; 338 irq_chip->irq_release_resources = em_gio_irq_relres; 339 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; 340 341 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, ngpios, 0, 342 &em_gio_irq_domain_ops, p); 343 if (!p->irq_domain) { 344 dev_err(&pdev->dev, "cannot initialize irq domain\n"); 345 return -ENXIO; 346 } 347 348 if (devm_request_irq(&pdev->dev, irq[0]->start, 349 em_gio_irq_handler, 0, name, p)) { 350 dev_err(&pdev->dev, "failed to request low IRQ\n"); 351 ret = -ENOENT; 352 goto err1; 353 } 354 355 if (devm_request_irq(&pdev->dev, irq[1]->start, 356 em_gio_irq_handler, 0, name, p)) { 357 dev_err(&pdev->dev, "failed to request high IRQ\n"); 358 ret = -ENOENT; 359 goto err1; 360 } 361 362 ret = gpiochip_add_data(gpio_chip, p); 363 if (ret) { 364 dev_err(&pdev->dev, "failed to add GPIO controller\n"); 365 goto err1; 366 } 367 368 return 0; 369 370 err1: 371 irq_domain_remove(p->irq_domain); 372 return ret; 373 } 374 375 static int em_gio_remove(struct platform_device *pdev) 376 { 377 struct em_gio_priv *p = platform_get_drvdata(pdev); 378 379 gpiochip_remove(&p->gpio_chip); 380 381 irq_domain_remove(p->irq_domain); 382 return 0; 383 } 384 385 static const struct of_device_id em_gio_dt_ids[] = { 386 { .compatible = "renesas,em-gio", }, 387 {}, 388 }; 389 MODULE_DEVICE_TABLE(of, em_gio_dt_ids); 390 391 static struct platform_driver em_gio_device_driver = { 392 .probe = em_gio_probe, 393 .remove = em_gio_remove, 394 .driver = { 395 .name = "em_gio", 396 .of_match_table = em_gio_dt_ids, 397 } 398 }; 399 400 static int __init em_gio_init(void) 401 { 402 return platform_driver_register(&em_gio_device_driver); 403 } 404 postcore_initcall(em_gio_init); 405 406 static void __exit em_gio_exit(void) 407 { 408 platform_driver_unregister(&em_gio_device_driver); 409 } 410 module_exit(em_gio_exit); 411 412 MODULE_AUTHOR("Magnus Damm"); 413 MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver"); 414 MODULE_LICENSE("GPL v2"); 415