1a07e103eSMagnus Damm /* 2a07e103eSMagnus Damm * Emma Mobile GPIO Support - GIO 3a07e103eSMagnus Damm * 4a07e103eSMagnus Damm * Copyright (C) 2012 Magnus Damm 5a07e103eSMagnus Damm * 6a07e103eSMagnus Damm * This program is free software; you can redistribute it and/or modify 7a07e103eSMagnus Damm * it under the terms of the GNU General Public License as published by 8a07e103eSMagnus Damm * the Free Software Foundation; either version 2 of the License 9a07e103eSMagnus Damm * 10a07e103eSMagnus Damm * This program is distributed in the hope that it will be useful, 11a07e103eSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 12a07e103eSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13a07e103eSMagnus Damm * GNU General Public License for more details. 14a07e103eSMagnus Damm * 15a07e103eSMagnus Damm * You should have received a copy of the GNU General Public License 16a07e103eSMagnus Damm * along with this program; if not, write to the Free Software 17a07e103eSMagnus Damm * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18a07e103eSMagnus Damm */ 19a07e103eSMagnus Damm 20a07e103eSMagnus Damm #include <linux/init.h> 21a07e103eSMagnus Damm #include <linux/platform_device.h> 22a07e103eSMagnus Damm #include <linux/spinlock.h> 23a07e103eSMagnus Damm #include <linux/interrupt.h> 24a07e103eSMagnus Damm #include <linux/ioport.h> 25a07e103eSMagnus Damm #include <linux/io.h> 26a07e103eSMagnus Damm #include <linux/irq.h> 27a07e103eSMagnus Damm #include <linux/irqdomain.h> 28a07e103eSMagnus Damm #include <linux/bitops.h> 29a07e103eSMagnus Damm #include <linux/err.h> 30a07e103eSMagnus Damm #include <linux/gpio.h> 31a07e103eSMagnus Damm #include <linux/slab.h> 32a07e103eSMagnus Damm #include <linux/module.h> 33640efa08SMagnus Damm #include <linux/pinctrl/consumer.h> 34a07e103eSMagnus Damm #include <linux/platform_data/gpio-em.h> 35a07e103eSMagnus Damm 36a07e103eSMagnus Damm struct em_gio_priv { 37a07e103eSMagnus Damm void __iomem *base0; 38a07e103eSMagnus Damm void __iomem *base1; 39a07e103eSMagnus Damm spinlock_t sense_lock; 40a07e103eSMagnus Damm struct platform_device *pdev; 41a07e103eSMagnus Damm struct gpio_chip gpio_chip; 42a07e103eSMagnus Damm struct irq_chip irq_chip; 43a07e103eSMagnus Damm struct irq_domain *irq_domain; 44a07e103eSMagnus Damm }; 45a07e103eSMagnus Damm 46a07e103eSMagnus Damm #define GIO_E1 0x00 47a07e103eSMagnus Damm #define GIO_E0 0x04 48a07e103eSMagnus Damm #define GIO_EM 0x04 49a07e103eSMagnus Damm #define GIO_OL 0x08 50a07e103eSMagnus Damm #define GIO_OH 0x0c 51a07e103eSMagnus Damm #define GIO_I 0x10 52a07e103eSMagnus Damm #define GIO_IIA 0x14 53a07e103eSMagnus Damm #define GIO_IEN 0x18 54a07e103eSMagnus Damm #define GIO_IDS 0x1c 55a07e103eSMagnus Damm #define GIO_IIM 0x1c 56a07e103eSMagnus Damm #define GIO_RAW 0x20 57a07e103eSMagnus Damm #define GIO_MST 0x24 58a07e103eSMagnus Damm #define GIO_IIR 0x28 59a07e103eSMagnus Damm 60a07e103eSMagnus Damm #define GIO_IDT0 0x40 61a07e103eSMagnus Damm #define GIO_IDT1 0x44 62a07e103eSMagnus Damm #define GIO_IDT2 0x48 63a07e103eSMagnus Damm #define GIO_IDT3 0x4c 64a07e103eSMagnus Damm #define GIO_RAWBL 0x50 65a07e103eSMagnus Damm #define GIO_RAWBH 0x54 66a07e103eSMagnus Damm #define GIO_IRBL 0x58 67a07e103eSMagnus Damm #define GIO_IRBH 0x5c 68a07e103eSMagnus Damm 69a07e103eSMagnus Damm #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4)) 70a07e103eSMagnus Damm 71a07e103eSMagnus Damm static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs) 72a07e103eSMagnus Damm { 73a07e103eSMagnus Damm if (offs < GIO_IDT0) 74a07e103eSMagnus Damm return ioread32(p->base0 + offs); 75a07e103eSMagnus Damm else 76a07e103eSMagnus Damm return ioread32(p->base1 + (offs - GIO_IDT0)); 77a07e103eSMagnus Damm } 78a07e103eSMagnus Damm 79a07e103eSMagnus Damm static inline void em_gio_write(struct em_gio_priv *p, int offs, 80a07e103eSMagnus Damm unsigned long value) 81a07e103eSMagnus Damm { 82a07e103eSMagnus Damm if (offs < GIO_IDT0) 83a07e103eSMagnus Damm iowrite32(value, p->base0 + offs); 84a07e103eSMagnus Damm else 85a07e103eSMagnus Damm iowrite32(value, p->base1 + (offs - GIO_IDT0)); 86a07e103eSMagnus Damm } 87a07e103eSMagnus Damm 88a07e103eSMagnus Damm static void em_gio_irq_disable(struct irq_data *d) 89a07e103eSMagnus Damm { 90a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 91a07e103eSMagnus Damm 92a07e103eSMagnus Damm em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d))); 93a07e103eSMagnus Damm } 94a07e103eSMagnus Damm 95a07e103eSMagnus Damm static void em_gio_irq_enable(struct irq_data *d) 96a07e103eSMagnus Damm { 97a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 98a07e103eSMagnus Damm 99a07e103eSMagnus Damm em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d))); 100a07e103eSMagnus Damm } 101a07e103eSMagnus Damm 10257ef0428SLinus Walleij static int em_gio_irq_reqres(struct irq_data *d) 1030dc61623SLinus Walleij { 1040dc61623SLinus Walleij struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 1050dc61623SLinus Walleij 106e3a2e878SAlexandre Courbot if (gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) { 1070dc61623SLinus Walleij dev_err(p->gpio_chip.dev, 1080dc61623SLinus Walleij "unable to lock HW IRQ %lu for IRQ\n", 1090dc61623SLinus Walleij irqd_to_hwirq(d)); 11057ef0428SLinus Walleij return -EINVAL; 11157ef0428SLinus Walleij } 1120dc61623SLinus Walleij return 0; 1130dc61623SLinus Walleij } 1140dc61623SLinus Walleij 11557ef0428SLinus Walleij static void em_gio_irq_relres(struct irq_data *d) 1160dc61623SLinus Walleij { 1170dc61623SLinus Walleij struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 1180dc61623SLinus Walleij 119e3a2e878SAlexandre Courbot gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); 1200dc61623SLinus Walleij } 1210dc61623SLinus Walleij 1220dc61623SLinus Walleij 123a07e103eSMagnus Damm #define GIO_ASYNC(x) (x + 8) 124a07e103eSMagnus Damm 125a07e103eSMagnus Damm static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { 126a07e103eSMagnus Damm [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00), 127a07e103eSMagnus Damm [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01), 128a07e103eSMagnus Damm [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02), 129a07e103eSMagnus Damm [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03), 130a07e103eSMagnus Damm [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04), 131a07e103eSMagnus Damm }; 132a07e103eSMagnus Damm 133a07e103eSMagnus Damm static int em_gio_irq_set_type(struct irq_data *d, unsigned int type) 134a07e103eSMagnus Damm { 135a07e103eSMagnus Damm unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK]; 136a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 137a07e103eSMagnus Damm unsigned int reg, offset, shift; 138a07e103eSMagnus Damm unsigned long flags; 139a07e103eSMagnus Damm unsigned long tmp; 140a07e103eSMagnus Damm 141a07e103eSMagnus Damm if (!value) 142a07e103eSMagnus Damm return -EINVAL; 143a07e103eSMagnus Damm 144a07e103eSMagnus Damm offset = irqd_to_hwirq(d); 145a07e103eSMagnus Damm 146a07e103eSMagnus Damm pr_debug("gio: sense irq = %d, mode = %d\n", offset, value); 147a07e103eSMagnus Damm 148a07e103eSMagnus Damm /* 8 x 4 bit fields in 4 IDT registers */ 149a07e103eSMagnus Damm reg = GIO_IDT(offset >> 3); 150a07e103eSMagnus Damm shift = (offset & 0x07) << 4; 151a07e103eSMagnus Damm 152a07e103eSMagnus Damm spin_lock_irqsave(&p->sense_lock, flags); 153a07e103eSMagnus Damm 154a07e103eSMagnus Damm /* disable the interrupt in IIA */ 155a07e103eSMagnus Damm tmp = em_gio_read(p, GIO_IIA); 156a07e103eSMagnus Damm tmp &= ~BIT(offset); 157a07e103eSMagnus Damm em_gio_write(p, GIO_IIA, tmp); 158a07e103eSMagnus Damm 159a07e103eSMagnus Damm /* change the sense setting in IDT */ 160a07e103eSMagnus Damm tmp = em_gio_read(p, reg); 161a07e103eSMagnus Damm tmp &= ~(0xf << shift); 162a07e103eSMagnus Damm tmp |= value << shift; 163a07e103eSMagnus Damm em_gio_write(p, reg, tmp); 164a07e103eSMagnus Damm 165a07e103eSMagnus Damm /* clear pending interrupts */ 166a07e103eSMagnus Damm em_gio_write(p, GIO_IIR, BIT(offset)); 167a07e103eSMagnus Damm 168a07e103eSMagnus Damm /* enable the interrupt in IIA */ 169a07e103eSMagnus Damm tmp = em_gio_read(p, GIO_IIA); 170a07e103eSMagnus Damm tmp |= BIT(offset); 171a07e103eSMagnus Damm em_gio_write(p, GIO_IIA, tmp); 172a07e103eSMagnus Damm 173a07e103eSMagnus Damm spin_unlock_irqrestore(&p->sense_lock, flags); 174a07e103eSMagnus Damm 175a07e103eSMagnus Damm return 0; 176a07e103eSMagnus Damm } 177a07e103eSMagnus Damm 178a07e103eSMagnus Damm static irqreturn_t em_gio_irq_handler(int irq, void *dev_id) 179a07e103eSMagnus Damm { 180a07e103eSMagnus Damm struct em_gio_priv *p = dev_id; 181a07e103eSMagnus Damm unsigned long pending; 182a07e103eSMagnus Damm unsigned int offset, irqs_handled = 0; 183a07e103eSMagnus Damm 184a07e103eSMagnus Damm while ((pending = em_gio_read(p, GIO_MST))) { 185a07e103eSMagnus Damm offset = __ffs(pending); 186a07e103eSMagnus Damm em_gio_write(p, GIO_IIR, BIT(offset)); 187a07e103eSMagnus Damm generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); 188a07e103eSMagnus Damm irqs_handled++; 189a07e103eSMagnus Damm } 190a07e103eSMagnus Damm 191a07e103eSMagnus Damm return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 192a07e103eSMagnus Damm } 193a07e103eSMagnus Damm 194a07e103eSMagnus Damm static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip) 195a07e103eSMagnus Damm { 196a07e103eSMagnus Damm return container_of(chip, struct em_gio_priv, gpio_chip); 197a07e103eSMagnus Damm } 198a07e103eSMagnus Damm 199a07e103eSMagnus Damm static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset) 200a07e103eSMagnus Damm { 201a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset)); 202a07e103eSMagnus Damm return 0; 203a07e103eSMagnus Damm } 204a07e103eSMagnus Damm 205a07e103eSMagnus Damm static int em_gio_get(struct gpio_chip *chip, unsigned offset) 206a07e103eSMagnus Damm { 207a07e103eSMagnus Damm return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset)); 208a07e103eSMagnus Damm } 209a07e103eSMagnus Damm 210a07e103eSMagnus Damm static void __em_gio_set(struct gpio_chip *chip, unsigned int reg, 211a07e103eSMagnus Damm unsigned shift, int value) 212a07e103eSMagnus Damm { 213a07e103eSMagnus Damm /* upper 16 bits contains mask and lower 16 actual value */ 214a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), reg, 2155f077644SJavier Martinez Canillas (BIT(shift + 16)) | (value << shift)); 216a07e103eSMagnus Damm } 217a07e103eSMagnus Damm 218a07e103eSMagnus Damm static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value) 219a07e103eSMagnus Damm { 220a07e103eSMagnus Damm /* output is split into two registers */ 221a07e103eSMagnus Damm if (offset < 16) 222a07e103eSMagnus Damm __em_gio_set(chip, GIO_OL, offset, value); 223a07e103eSMagnus Damm else 224a07e103eSMagnus Damm __em_gio_set(chip, GIO_OH, offset - 16, value); 225a07e103eSMagnus Damm } 226a07e103eSMagnus Damm 227a07e103eSMagnus Damm static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset, 228a07e103eSMagnus Damm int value) 229a07e103eSMagnus Damm { 230a07e103eSMagnus Damm /* write GPIO value to output before selecting output mode of pin */ 231a07e103eSMagnus Damm em_gio_set(chip, offset, value); 232a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset)); 233a07e103eSMagnus Damm return 0; 234a07e103eSMagnus Damm } 235a07e103eSMagnus Damm 236a07e103eSMagnus Damm static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset) 237a07e103eSMagnus Damm { 2387385500aSLinus Walleij return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); 239a07e103eSMagnus Damm } 240a07e103eSMagnus Damm 241640efa08SMagnus Damm static int em_gio_request(struct gpio_chip *chip, unsigned offset) 242640efa08SMagnus Damm { 243640efa08SMagnus Damm return pinctrl_request_gpio(chip->base + offset); 244640efa08SMagnus Damm } 245640efa08SMagnus Damm 246640efa08SMagnus Damm static void em_gio_free(struct gpio_chip *chip, unsigned offset) 247640efa08SMagnus Damm { 248640efa08SMagnus Damm pinctrl_free_gpio(chip->base + offset); 249640efa08SMagnus Damm 250640efa08SMagnus Damm /* Set the GPIO as an input to ensure that the next GPIO request won't 251640efa08SMagnus Damm * drive the GPIO pin as an output. 252640efa08SMagnus Damm */ 253640efa08SMagnus Damm em_gio_direction_input(chip, offset); 254640efa08SMagnus Damm } 255640efa08SMagnus Damm 2562d61e3e9SLinus Walleij static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq, 2572d61e3e9SLinus Walleij irq_hw_number_t hwirq) 258a07e103eSMagnus Damm { 259a07e103eSMagnus Damm struct em_gio_priv *p = h->host_data; 260a07e103eSMagnus Damm 2612d61e3e9SLinus Walleij pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq); 262a07e103eSMagnus Damm 2632d61e3e9SLinus Walleij irq_set_chip_data(irq, h->host_data); 2642d61e3e9SLinus Walleij irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq); 2652d61e3e9SLinus Walleij set_irq_flags(irq, IRQF_VALID); /* kill me now */ 266a07e103eSMagnus Damm return 0; 267a07e103eSMagnus Damm } 268a07e103eSMagnus Damm 269a07e103eSMagnus Damm static struct irq_domain_ops em_gio_irq_domain_ops = { 270a07e103eSMagnus Damm .map = em_gio_irq_domain_map, 271753c5983SMagnus Damm .xlate = irq_domain_xlate_twocell, 272a07e103eSMagnus Damm }; 273a07e103eSMagnus Damm 2743836309dSBill Pemberton static int em_gio_probe(struct platform_device *pdev) 275a07e103eSMagnus Damm { 276753c5983SMagnus Damm struct gpio_em_config pdata_dt; 277e56aee18SJingoo Han struct gpio_em_config *pdata = dev_get_platdata(&pdev->dev); 278a07e103eSMagnus Damm struct em_gio_priv *p; 279a07e103eSMagnus Damm struct resource *io[2], *irq[2]; 280a07e103eSMagnus Damm struct gpio_chip *gpio_chip; 281a07e103eSMagnus Damm struct irq_chip *irq_chip; 282a07e103eSMagnus Damm const char *name = dev_name(&pdev->dev); 283a07e103eSMagnus Damm int ret; 284a07e103eSMagnus Damm 2851cfe6f8cSMagnus Damm p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); 286a07e103eSMagnus Damm if (!p) { 287a07e103eSMagnus Damm ret = -ENOMEM; 288a07e103eSMagnus Damm goto err0; 289a07e103eSMagnus Damm } 290a07e103eSMagnus Damm 291a07e103eSMagnus Damm p->pdev = pdev; 292a07e103eSMagnus Damm platform_set_drvdata(pdev, p); 293a07e103eSMagnus Damm spin_lock_init(&p->sense_lock); 294a07e103eSMagnus Damm 295a07e103eSMagnus Damm io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0); 296a07e103eSMagnus Damm io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1); 297a07e103eSMagnus Damm irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 298a07e103eSMagnus Damm irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 299a07e103eSMagnus Damm 300753c5983SMagnus Damm if (!io[0] || !io[1] || !irq[0] || !irq[1]) { 301753c5983SMagnus Damm dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); 302a07e103eSMagnus Damm ret = -EINVAL; 3031cfe6f8cSMagnus Damm goto err0; 304a07e103eSMagnus Damm } 305a07e103eSMagnus Damm 3061cfe6f8cSMagnus Damm p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start, 3071cfe6f8cSMagnus Damm resource_size(io[0])); 308a07e103eSMagnus Damm if (!p->base0) { 309a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to remap low I/O memory\n"); 310a07e103eSMagnus Damm ret = -ENXIO; 3111cfe6f8cSMagnus Damm goto err0; 312a07e103eSMagnus Damm } 313a07e103eSMagnus Damm 3141cfe6f8cSMagnus Damm p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start, 3151cfe6f8cSMagnus Damm resource_size(io[1])); 316a07e103eSMagnus Damm if (!p->base1) { 317a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to remap high I/O memory\n"); 318a07e103eSMagnus Damm ret = -ENXIO; 3191cfe6f8cSMagnus Damm goto err0; 320a07e103eSMagnus Damm } 321a07e103eSMagnus Damm 322753c5983SMagnus Damm if (!pdata) { 323753c5983SMagnus Damm memset(&pdata_dt, 0, sizeof(pdata_dt)); 324753c5983SMagnus Damm pdata = &pdata_dt; 325753c5983SMagnus Damm 326753c5983SMagnus Damm if (of_property_read_u32(pdev->dev.of_node, "ngpios", 327753c5983SMagnus Damm &pdata->number_of_pins)) { 328753c5983SMagnus Damm dev_err(&pdev->dev, "Missing ngpios OF property\n"); 329753c5983SMagnus Damm ret = -EINVAL; 3301cfe6f8cSMagnus Damm goto err0; 331753c5983SMagnus Damm } 332753c5983SMagnus Damm 333753c5983SMagnus Damm ret = of_alias_get_id(pdev->dev.of_node, "gpio"); 334753c5983SMagnus Damm if (ret < 0) { 335753c5983SMagnus Damm dev_err(&pdev->dev, "Couldn't get OF id\n"); 3361cfe6f8cSMagnus Damm goto err0; 337753c5983SMagnus Damm } 338753c5983SMagnus Damm pdata->gpio_base = ret * 32; /* 32 GPIOs per instance */ 339753c5983SMagnus Damm } 340753c5983SMagnus Damm 341a07e103eSMagnus Damm gpio_chip = &p->gpio_chip; 342b5927854SIan Molton gpio_chip->of_node = pdev->dev.of_node; 343a07e103eSMagnus Damm gpio_chip->direction_input = em_gio_direction_input; 344a07e103eSMagnus Damm gpio_chip->get = em_gio_get; 345a07e103eSMagnus Damm gpio_chip->direction_output = em_gio_direction_output; 346a07e103eSMagnus Damm gpio_chip->set = em_gio_set; 347a07e103eSMagnus Damm gpio_chip->to_irq = em_gio_to_irq; 348640efa08SMagnus Damm gpio_chip->request = em_gio_request; 349640efa08SMagnus Damm gpio_chip->free = em_gio_free; 350a07e103eSMagnus Damm gpio_chip->label = name; 351969bf7aeSMagnus Damm gpio_chip->dev = &pdev->dev; 352a07e103eSMagnus Damm gpio_chip->owner = THIS_MODULE; 353a07e103eSMagnus Damm gpio_chip->base = pdata->gpio_base; 354a07e103eSMagnus Damm gpio_chip->ngpio = pdata->number_of_pins; 355a07e103eSMagnus Damm 356a07e103eSMagnus Damm irq_chip = &p->irq_chip; 357a07e103eSMagnus Damm irq_chip->name = name; 358a07e103eSMagnus Damm irq_chip->irq_mask = em_gio_irq_disable; 359a07e103eSMagnus Damm irq_chip->irq_unmask = em_gio_irq_enable; 360a07e103eSMagnus Damm irq_chip->irq_set_type = em_gio_irq_set_type; 36157ef0428SLinus Walleij irq_chip->irq_request_resources = em_gio_irq_reqres; 36257ef0428SLinus Walleij irq_chip->irq_release_resources = em_gio_irq_relres; 36303621b60SMagnus Damm irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; 364a07e103eSMagnus Damm 365c7886b18SMagnus Damm p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 3667385500aSLinus Walleij pdata->number_of_pins, 367c7886b18SMagnus Damm pdata->irq_base, 3687385500aSLinus Walleij &em_gio_irq_domain_ops, p); 36916310819SAxel Lin if (!p->irq_domain) { 37016310819SAxel Lin ret = -ENXIO; 371a07e103eSMagnus Damm dev_err(&pdev->dev, "cannot initialize irq domain\n"); 3721cfe6f8cSMagnus Damm goto err0; 373a07e103eSMagnus Damm } 374a07e103eSMagnus Damm 3751cfe6f8cSMagnus Damm if (devm_request_irq(&pdev->dev, irq[0]->start, 3761cfe6f8cSMagnus Damm em_gio_irq_handler, 0, name, p)) { 377a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to request low IRQ\n"); 378a07e103eSMagnus Damm ret = -ENOENT; 3791cfe6f8cSMagnus Damm goto err1; 380a07e103eSMagnus Damm } 381a07e103eSMagnus Damm 3821cfe6f8cSMagnus Damm if (devm_request_irq(&pdev->dev, irq[1]->start, 3831cfe6f8cSMagnus Damm em_gio_irq_handler, 0, name, p)) { 384a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to request high IRQ\n"); 385a07e103eSMagnus Damm ret = -ENOENT; 3861cfe6f8cSMagnus Damm goto err1; 387a07e103eSMagnus Damm } 388a07e103eSMagnus Damm 389a07e103eSMagnus Damm ret = gpiochip_add(gpio_chip); 390a07e103eSMagnus Damm if (ret) { 391a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to add GPIO controller\n"); 3921cfe6f8cSMagnus Damm goto err1; 393a07e103eSMagnus Damm } 394640efa08SMagnus Damm 395640efa08SMagnus Damm if (pdata->pctl_name) { 396640efa08SMagnus Damm ret = gpiochip_add_pin_range(gpio_chip, pdata->pctl_name, 0, 397640efa08SMagnus Damm gpio_chip->base, gpio_chip->ngpio); 398640efa08SMagnus Damm if (ret < 0) 399640efa08SMagnus Damm dev_warn(&pdev->dev, "failed to add pin range\n"); 400640efa08SMagnus Damm } 401a07e103eSMagnus Damm return 0; 402a07e103eSMagnus Damm 403a07e103eSMagnus Damm err1: 4041cfe6f8cSMagnus Damm irq_domain_remove(p->irq_domain); 405a07e103eSMagnus Damm err0: 406a07e103eSMagnus Damm return ret; 407a07e103eSMagnus Damm } 408a07e103eSMagnus Damm 409206210ceSBill Pemberton static int em_gio_remove(struct platform_device *pdev) 410a07e103eSMagnus Damm { 411a07e103eSMagnus Damm struct em_gio_priv *p = platform_get_drvdata(pdev); 412a07e103eSMagnus Damm 4139f5132aeSabdoulaye berthe gpiochip_remove(&p->gpio_chip); 414a07e103eSMagnus Damm 41516310819SAxel Lin irq_domain_remove(p->irq_domain); 416a07e103eSMagnus Damm return 0; 417a07e103eSMagnus Damm } 418a07e103eSMagnus Damm 419753c5983SMagnus Damm static const struct of_device_id em_gio_dt_ids[] = { 420753c5983SMagnus Damm { .compatible = "renesas,em-gio", }, 421753c5983SMagnus Damm {}, 422753c5983SMagnus Damm }; 423753c5983SMagnus Damm MODULE_DEVICE_TABLE(of, em_gio_dt_ids); 424753c5983SMagnus Damm 425a07e103eSMagnus Damm static struct platform_driver em_gio_device_driver = { 426a07e103eSMagnus Damm .probe = em_gio_probe, 4278283c4ffSBill Pemberton .remove = em_gio_remove, 428a07e103eSMagnus Damm .driver = { 429a07e103eSMagnus Damm .name = "em_gio", 430753c5983SMagnus Damm .of_match_table = em_gio_dt_ids, 431753c5983SMagnus Damm .owner = THIS_MODULE, 432a07e103eSMagnus Damm } 433a07e103eSMagnus Damm }; 434a07e103eSMagnus Damm 435753c5983SMagnus Damm static int __init em_gio_init(void) 436753c5983SMagnus Damm { 437753c5983SMagnus Damm return platform_driver_register(&em_gio_device_driver); 438753c5983SMagnus Damm } 439753c5983SMagnus Damm postcore_initcall(em_gio_init); 440753c5983SMagnus Damm 441753c5983SMagnus Damm static void __exit em_gio_exit(void) 442753c5983SMagnus Damm { 443753c5983SMagnus Damm platform_driver_unregister(&em_gio_device_driver); 444753c5983SMagnus Damm } 445753c5983SMagnus Damm module_exit(em_gio_exit); 446a07e103eSMagnus Damm 447a07e103eSMagnus Damm MODULE_AUTHOR("Magnus Damm"); 448a07e103eSMagnus Damm MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver"); 449a07e103eSMagnus Damm MODULE_LICENSE("GPL v2"); 450