1a07e103eSMagnus Damm /* 2a07e103eSMagnus Damm * Emma Mobile GPIO Support - GIO 3a07e103eSMagnus Damm * 4a07e103eSMagnus Damm * Copyright (C) 2012 Magnus Damm 5a07e103eSMagnus Damm * 6a07e103eSMagnus Damm * This program is free software; you can redistribute it and/or modify 7a07e103eSMagnus Damm * it under the terms of the GNU General Public License as published by 8a07e103eSMagnus Damm * the Free Software Foundation; either version 2 of the License 9a07e103eSMagnus Damm * 10a07e103eSMagnus Damm * This program is distributed in the hope that it will be useful, 11a07e103eSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 12a07e103eSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13a07e103eSMagnus Damm * GNU General Public License for more details. 14a07e103eSMagnus Damm * 15a07e103eSMagnus Damm * You should have received a copy of the GNU General Public License 16a07e103eSMagnus Damm * along with this program; if not, write to the Free Software 17a07e103eSMagnus Damm * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18a07e103eSMagnus Damm */ 19a07e103eSMagnus Damm 20a07e103eSMagnus Damm #include <linux/init.h> 21a07e103eSMagnus Damm #include <linux/platform_device.h> 22a07e103eSMagnus Damm #include <linux/spinlock.h> 23a07e103eSMagnus Damm #include <linux/interrupt.h> 24a07e103eSMagnus Damm #include <linux/ioport.h> 25a07e103eSMagnus Damm #include <linux/io.h> 26a07e103eSMagnus Damm #include <linux/irq.h> 27a07e103eSMagnus Damm #include <linux/irqdomain.h> 28a07e103eSMagnus Damm #include <linux/bitops.h> 29a07e103eSMagnus Damm #include <linux/err.h> 30a07e103eSMagnus Damm #include <linux/gpio.h> 31a07e103eSMagnus Damm #include <linux/slab.h> 32a07e103eSMagnus Damm #include <linux/module.h> 33640efa08SMagnus Damm #include <linux/pinctrl/consumer.h> 34a07e103eSMagnus Damm #include <linux/platform_data/gpio-em.h> 35a07e103eSMagnus Damm 36a07e103eSMagnus Damm struct em_gio_priv { 37a07e103eSMagnus Damm void __iomem *base0; 38a07e103eSMagnus Damm void __iomem *base1; 39a07e103eSMagnus Damm spinlock_t sense_lock; 40a07e103eSMagnus Damm struct platform_device *pdev; 41a07e103eSMagnus Damm struct gpio_chip gpio_chip; 42a07e103eSMagnus Damm struct irq_chip irq_chip; 43a07e103eSMagnus Damm struct irq_domain *irq_domain; 44a07e103eSMagnus Damm }; 45a07e103eSMagnus Damm 46a07e103eSMagnus Damm #define GIO_E1 0x00 47a07e103eSMagnus Damm #define GIO_E0 0x04 48a07e103eSMagnus Damm #define GIO_EM 0x04 49a07e103eSMagnus Damm #define GIO_OL 0x08 50a07e103eSMagnus Damm #define GIO_OH 0x0c 51a07e103eSMagnus Damm #define GIO_I 0x10 52a07e103eSMagnus Damm #define GIO_IIA 0x14 53a07e103eSMagnus Damm #define GIO_IEN 0x18 54a07e103eSMagnus Damm #define GIO_IDS 0x1c 55a07e103eSMagnus Damm #define GIO_IIM 0x1c 56a07e103eSMagnus Damm #define GIO_RAW 0x20 57a07e103eSMagnus Damm #define GIO_MST 0x24 58a07e103eSMagnus Damm #define GIO_IIR 0x28 59a07e103eSMagnus Damm 60a07e103eSMagnus Damm #define GIO_IDT0 0x40 61a07e103eSMagnus Damm #define GIO_IDT1 0x44 62a07e103eSMagnus Damm #define GIO_IDT2 0x48 63a07e103eSMagnus Damm #define GIO_IDT3 0x4c 64a07e103eSMagnus Damm #define GIO_RAWBL 0x50 65a07e103eSMagnus Damm #define GIO_RAWBH 0x54 66a07e103eSMagnus Damm #define GIO_IRBL 0x58 67a07e103eSMagnus Damm #define GIO_IRBH 0x5c 68a07e103eSMagnus Damm 69a07e103eSMagnus Damm #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4)) 70a07e103eSMagnus Damm 71a07e103eSMagnus Damm static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs) 72a07e103eSMagnus Damm { 73a07e103eSMagnus Damm if (offs < GIO_IDT0) 74a07e103eSMagnus Damm return ioread32(p->base0 + offs); 75a07e103eSMagnus Damm else 76a07e103eSMagnus Damm return ioread32(p->base1 + (offs - GIO_IDT0)); 77a07e103eSMagnus Damm } 78a07e103eSMagnus Damm 79a07e103eSMagnus Damm static inline void em_gio_write(struct em_gio_priv *p, int offs, 80a07e103eSMagnus Damm unsigned long value) 81a07e103eSMagnus Damm { 82a07e103eSMagnus Damm if (offs < GIO_IDT0) 83a07e103eSMagnus Damm iowrite32(value, p->base0 + offs); 84a07e103eSMagnus Damm else 85a07e103eSMagnus Damm iowrite32(value, p->base1 + (offs - GIO_IDT0)); 86a07e103eSMagnus Damm } 87a07e103eSMagnus Damm 88a07e103eSMagnus Damm static void em_gio_irq_disable(struct irq_data *d) 89a07e103eSMagnus Damm { 90a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 91a07e103eSMagnus Damm 92a07e103eSMagnus Damm em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d))); 93a07e103eSMagnus Damm } 94a07e103eSMagnus Damm 95a07e103eSMagnus Damm static void em_gio_irq_enable(struct irq_data *d) 96a07e103eSMagnus Damm { 97a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 98a07e103eSMagnus Damm 99a07e103eSMagnus Damm em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d))); 100a07e103eSMagnus Damm } 101a07e103eSMagnus Damm 102a07e103eSMagnus Damm #define GIO_ASYNC(x) (x + 8) 103a07e103eSMagnus Damm 104a07e103eSMagnus Damm static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { 105a07e103eSMagnus Damm [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00), 106a07e103eSMagnus Damm [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01), 107a07e103eSMagnus Damm [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02), 108a07e103eSMagnus Damm [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03), 109a07e103eSMagnus Damm [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04), 110a07e103eSMagnus Damm }; 111a07e103eSMagnus Damm 112a07e103eSMagnus Damm static int em_gio_irq_set_type(struct irq_data *d, unsigned int type) 113a07e103eSMagnus Damm { 114a07e103eSMagnus Damm unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK]; 115a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 116a07e103eSMagnus Damm unsigned int reg, offset, shift; 117a07e103eSMagnus Damm unsigned long flags; 118a07e103eSMagnus Damm unsigned long tmp; 119a07e103eSMagnus Damm 120a07e103eSMagnus Damm if (!value) 121a07e103eSMagnus Damm return -EINVAL; 122a07e103eSMagnus Damm 123a07e103eSMagnus Damm offset = irqd_to_hwirq(d); 124a07e103eSMagnus Damm 125a07e103eSMagnus Damm pr_debug("gio: sense irq = %d, mode = %d\n", offset, value); 126a07e103eSMagnus Damm 127a07e103eSMagnus Damm /* 8 x 4 bit fields in 4 IDT registers */ 128a07e103eSMagnus Damm reg = GIO_IDT(offset >> 3); 129a07e103eSMagnus Damm shift = (offset & 0x07) << 4; 130a07e103eSMagnus Damm 131a07e103eSMagnus Damm spin_lock_irqsave(&p->sense_lock, flags); 132a07e103eSMagnus Damm 133a07e103eSMagnus Damm /* disable the interrupt in IIA */ 134a07e103eSMagnus Damm tmp = em_gio_read(p, GIO_IIA); 135a07e103eSMagnus Damm tmp &= ~BIT(offset); 136a07e103eSMagnus Damm em_gio_write(p, GIO_IIA, tmp); 137a07e103eSMagnus Damm 138a07e103eSMagnus Damm /* change the sense setting in IDT */ 139a07e103eSMagnus Damm tmp = em_gio_read(p, reg); 140a07e103eSMagnus Damm tmp &= ~(0xf << shift); 141a07e103eSMagnus Damm tmp |= value << shift; 142a07e103eSMagnus Damm em_gio_write(p, reg, tmp); 143a07e103eSMagnus Damm 144a07e103eSMagnus Damm /* clear pending interrupts */ 145a07e103eSMagnus Damm em_gio_write(p, GIO_IIR, BIT(offset)); 146a07e103eSMagnus Damm 147a07e103eSMagnus Damm /* enable the interrupt in IIA */ 148a07e103eSMagnus Damm tmp = em_gio_read(p, GIO_IIA); 149a07e103eSMagnus Damm tmp |= BIT(offset); 150a07e103eSMagnus Damm em_gio_write(p, GIO_IIA, tmp); 151a07e103eSMagnus Damm 152a07e103eSMagnus Damm spin_unlock_irqrestore(&p->sense_lock, flags); 153a07e103eSMagnus Damm 154a07e103eSMagnus Damm return 0; 155a07e103eSMagnus Damm } 156a07e103eSMagnus Damm 157a07e103eSMagnus Damm static irqreturn_t em_gio_irq_handler(int irq, void *dev_id) 158a07e103eSMagnus Damm { 159a07e103eSMagnus Damm struct em_gio_priv *p = dev_id; 160a07e103eSMagnus Damm unsigned long pending; 161a07e103eSMagnus Damm unsigned int offset, irqs_handled = 0; 162a07e103eSMagnus Damm 163a07e103eSMagnus Damm while ((pending = em_gio_read(p, GIO_MST))) { 164a07e103eSMagnus Damm offset = __ffs(pending); 165a07e103eSMagnus Damm em_gio_write(p, GIO_IIR, BIT(offset)); 166a07e103eSMagnus Damm generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); 167a07e103eSMagnus Damm irqs_handled++; 168a07e103eSMagnus Damm } 169a07e103eSMagnus Damm 170a07e103eSMagnus Damm return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 171a07e103eSMagnus Damm } 172a07e103eSMagnus Damm 173a07e103eSMagnus Damm static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip) 174a07e103eSMagnus Damm { 175a07e103eSMagnus Damm return container_of(chip, struct em_gio_priv, gpio_chip); 176a07e103eSMagnus Damm } 177a07e103eSMagnus Damm 178a07e103eSMagnus Damm static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset) 179a07e103eSMagnus Damm { 180a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset)); 181a07e103eSMagnus Damm return 0; 182a07e103eSMagnus Damm } 183a07e103eSMagnus Damm 184a07e103eSMagnus Damm static int em_gio_get(struct gpio_chip *chip, unsigned offset) 185a07e103eSMagnus Damm { 186a07e103eSMagnus Damm return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset)); 187a07e103eSMagnus Damm } 188a07e103eSMagnus Damm 189a07e103eSMagnus Damm static void __em_gio_set(struct gpio_chip *chip, unsigned int reg, 190a07e103eSMagnus Damm unsigned shift, int value) 191a07e103eSMagnus Damm { 192a07e103eSMagnus Damm /* upper 16 bits contains mask and lower 16 actual value */ 193a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), reg, 194a07e103eSMagnus Damm (1 << (shift + 16)) | (value << shift)); 195a07e103eSMagnus Damm } 196a07e103eSMagnus Damm 197a07e103eSMagnus Damm static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value) 198a07e103eSMagnus Damm { 199a07e103eSMagnus Damm /* output is split into two registers */ 200a07e103eSMagnus Damm if (offset < 16) 201a07e103eSMagnus Damm __em_gio_set(chip, GIO_OL, offset, value); 202a07e103eSMagnus Damm else 203a07e103eSMagnus Damm __em_gio_set(chip, GIO_OH, offset - 16, value); 204a07e103eSMagnus Damm } 205a07e103eSMagnus Damm 206a07e103eSMagnus Damm static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset, 207a07e103eSMagnus Damm int value) 208a07e103eSMagnus Damm { 209a07e103eSMagnus Damm /* write GPIO value to output before selecting output mode of pin */ 210a07e103eSMagnus Damm em_gio_set(chip, offset, value); 211a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset)); 212a07e103eSMagnus Damm return 0; 213a07e103eSMagnus Damm } 214a07e103eSMagnus Damm 215a07e103eSMagnus Damm static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset) 216a07e103eSMagnus Damm { 2177385500aSLinus Walleij return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); 218a07e103eSMagnus Damm } 219a07e103eSMagnus Damm 220640efa08SMagnus Damm static int em_gio_request(struct gpio_chip *chip, unsigned offset) 221640efa08SMagnus Damm { 222640efa08SMagnus Damm return pinctrl_request_gpio(chip->base + offset); 223640efa08SMagnus Damm } 224640efa08SMagnus Damm 225640efa08SMagnus Damm static void em_gio_free(struct gpio_chip *chip, unsigned offset) 226640efa08SMagnus Damm { 227640efa08SMagnus Damm pinctrl_free_gpio(chip->base + offset); 228640efa08SMagnus Damm 229640efa08SMagnus Damm /* Set the GPIO as an input to ensure that the next GPIO request won't 230640efa08SMagnus Damm * drive the GPIO pin as an output. 231640efa08SMagnus Damm */ 232640efa08SMagnus Damm em_gio_direction_input(chip, offset); 233640efa08SMagnus Damm } 234640efa08SMagnus Damm 2352d61e3e9SLinus Walleij static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq, 2362d61e3e9SLinus Walleij irq_hw_number_t hwirq) 237a07e103eSMagnus Damm { 238a07e103eSMagnus Damm struct em_gio_priv *p = h->host_data; 239a07e103eSMagnus Damm 2402d61e3e9SLinus Walleij pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq); 241a07e103eSMagnus Damm 2422d61e3e9SLinus Walleij irq_set_chip_data(irq, h->host_data); 2432d61e3e9SLinus Walleij irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq); 2442d61e3e9SLinus Walleij set_irq_flags(irq, IRQF_VALID); /* kill me now */ 245a07e103eSMagnus Damm return 0; 246a07e103eSMagnus Damm } 247a07e103eSMagnus Damm 248a07e103eSMagnus Damm static struct irq_domain_ops em_gio_irq_domain_ops = { 249a07e103eSMagnus Damm .map = em_gio_irq_domain_map, 250753c5983SMagnus Damm .xlate = irq_domain_xlate_twocell, 251a07e103eSMagnus Damm }; 252a07e103eSMagnus Damm 2533836309dSBill Pemberton static int em_gio_probe(struct platform_device *pdev) 254a07e103eSMagnus Damm { 255753c5983SMagnus Damm struct gpio_em_config pdata_dt; 256e56aee18SJingoo Han struct gpio_em_config *pdata = dev_get_platdata(&pdev->dev); 257a07e103eSMagnus Damm struct em_gio_priv *p; 258a07e103eSMagnus Damm struct resource *io[2], *irq[2]; 259a07e103eSMagnus Damm struct gpio_chip *gpio_chip; 260a07e103eSMagnus Damm struct irq_chip *irq_chip; 261a07e103eSMagnus Damm const char *name = dev_name(&pdev->dev); 262a07e103eSMagnus Damm int ret; 263a07e103eSMagnus Damm 2641cfe6f8cSMagnus Damm p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); 265a07e103eSMagnus Damm if (!p) { 266a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to allocate driver data\n"); 267a07e103eSMagnus Damm ret = -ENOMEM; 268a07e103eSMagnus Damm goto err0; 269a07e103eSMagnus Damm } 270a07e103eSMagnus Damm 271a07e103eSMagnus Damm p->pdev = pdev; 272a07e103eSMagnus Damm platform_set_drvdata(pdev, p); 273a07e103eSMagnus Damm spin_lock_init(&p->sense_lock); 274a07e103eSMagnus Damm 275a07e103eSMagnus Damm io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0); 276a07e103eSMagnus Damm io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1); 277a07e103eSMagnus Damm irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 278a07e103eSMagnus Damm irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 279a07e103eSMagnus Damm 280753c5983SMagnus Damm if (!io[0] || !io[1] || !irq[0] || !irq[1]) { 281753c5983SMagnus Damm dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); 282a07e103eSMagnus Damm ret = -EINVAL; 2831cfe6f8cSMagnus Damm goto err0; 284a07e103eSMagnus Damm } 285a07e103eSMagnus Damm 2861cfe6f8cSMagnus Damm p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start, 2871cfe6f8cSMagnus Damm resource_size(io[0])); 288a07e103eSMagnus Damm if (!p->base0) { 289a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to remap low I/O memory\n"); 290a07e103eSMagnus Damm ret = -ENXIO; 2911cfe6f8cSMagnus Damm goto err0; 292a07e103eSMagnus Damm } 293a07e103eSMagnus Damm 2941cfe6f8cSMagnus Damm p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start, 2951cfe6f8cSMagnus Damm resource_size(io[1])); 296a07e103eSMagnus Damm if (!p->base1) { 297a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to remap high I/O memory\n"); 298a07e103eSMagnus Damm ret = -ENXIO; 2991cfe6f8cSMagnus Damm goto err0; 300a07e103eSMagnus Damm } 301a07e103eSMagnus Damm 302753c5983SMagnus Damm if (!pdata) { 303753c5983SMagnus Damm memset(&pdata_dt, 0, sizeof(pdata_dt)); 304753c5983SMagnus Damm pdata = &pdata_dt; 305753c5983SMagnus Damm 306753c5983SMagnus Damm if (of_property_read_u32(pdev->dev.of_node, "ngpios", 307753c5983SMagnus Damm &pdata->number_of_pins)) { 308753c5983SMagnus Damm dev_err(&pdev->dev, "Missing ngpios OF property\n"); 309753c5983SMagnus Damm ret = -EINVAL; 3101cfe6f8cSMagnus Damm goto err0; 311753c5983SMagnus Damm } 312753c5983SMagnus Damm 313753c5983SMagnus Damm ret = of_alias_get_id(pdev->dev.of_node, "gpio"); 314753c5983SMagnus Damm if (ret < 0) { 315753c5983SMagnus Damm dev_err(&pdev->dev, "Couldn't get OF id\n"); 3161cfe6f8cSMagnus Damm goto err0; 317753c5983SMagnus Damm } 318753c5983SMagnus Damm pdata->gpio_base = ret * 32; /* 32 GPIOs per instance */ 319753c5983SMagnus Damm } 320753c5983SMagnus Damm 321a07e103eSMagnus Damm gpio_chip = &p->gpio_chip; 322b5927854SIan Molton gpio_chip->of_node = pdev->dev.of_node; 323a07e103eSMagnus Damm gpio_chip->direction_input = em_gio_direction_input; 324a07e103eSMagnus Damm gpio_chip->get = em_gio_get; 325a07e103eSMagnus Damm gpio_chip->direction_output = em_gio_direction_output; 326a07e103eSMagnus Damm gpio_chip->set = em_gio_set; 327a07e103eSMagnus Damm gpio_chip->to_irq = em_gio_to_irq; 328640efa08SMagnus Damm gpio_chip->request = em_gio_request; 329640efa08SMagnus Damm gpio_chip->free = em_gio_free; 330a07e103eSMagnus Damm gpio_chip->label = name; 331969bf7aeSMagnus Damm gpio_chip->dev = &pdev->dev; 332a07e103eSMagnus Damm gpio_chip->owner = THIS_MODULE; 333a07e103eSMagnus Damm gpio_chip->base = pdata->gpio_base; 334a07e103eSMagnus Damm gpio_chip->ngpio = pdata->number_of_pins; 335a07e103eSMagnus Damm 336a07e103eSMagnus Damm irq_chip = &p->irq_chip; 337a07e103eSMagnus Damm irq_chip->name = name; 338a07e103eSMagnus Damm irq_chip->irq_mask = em_gio_irq_disable; 339a07e103eSMagnus Damm irq_chip->irq_unmask = em_gio_irq_enable; 340a07e103eSMagnus Damm irq_chip->irq_enable = em_gio_irq_enable; 341a07e103eSMagnus Damm irq_chip->irq_disable = em_gio_irq_disable; 342a07e103eSMagnus Damm irq_chip->irq_set_type = em_gio_irq_set_type; 343a07e103eSMagnus Damm irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; 344a07e103eSMagnus Damm 345c7886b18SMagnus Damm p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 3467385500aSLinus Walleij pdata->number_of_pins, 347c7886b18SMagnus Damm pdata->irq_base, 3487385500aSLinus Walleij &em_gio_irq_domain_ops, p); 34916310819SAxel Lin if (!p->irq_domain) { 35016310819SAxel Lin ret = -ENXIO; 351a07e103eSMagnus Damm dev_err(&pdev->dev, "cannot initialize irq domain\n"); 3521cfe6f8cSMagnus Damm goto err0; 353a07e103eSMagnus Damm } 354a07e103eSMagnus Damm 3551cfe6f8cSMagnus Damm if (devm_request_irq(&pdev->dev, irq[0]->start, 3561cfe6f8cSMagnus Damm em_gio_irq_handler, 0, name, p)) { 357a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to request low IRQ\n"); 358a07e103eSMagnus Damm ret = -ENOENT; 3591cfe6f8cSMagnus Damm goto err1; 360a07e103eSMagnus Damm } 361a07e103eSMagnus Damm 3621cfe6f8cSMagnus Damm if (devm_request_irq(&pdev->dev, irq[1]->start, 3631cfe6f8cSMagnus Damm em_gio_irq_handler, 0, name, p)) { 364a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to request high IRQ\n"); 365a07e103eSMagnus Damm ret = -ENOENT; 3661cfe6f8cSMagnus Damm goto err1; 367a07e103eSMagnus Damm } 368a07e103eSMagnus Damm 369a07e103eSMagnus Damm ret = gpiochip_add(gpio_chip); 370a07e103eSMagnus Damm if (ret) { 371a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to add GPIO controller\n"); 3721cfe6f8cSMagnus Damm goto err1; 373a07e103eSMagnus Damm } 374640efa08SMagnus Damm 375640efa08SMagnus Damm if (pdata->pctl_name) { 376640efa08SMagnus Damm ret = gpiochip_add_pin_range(gpio_chip, pdata->pctl_name, 0, 377640efa08SMagnus Damm gpio_chip->base, gpio_chip->ngpio); 378640efa08SMagnus Damm if (ret < 0) 379640efa08SMagnus Damm dev_warn(&pdev->dev, "failed to add pin range\n"); 380640efa08SMagnus Damm } 381a07e103eSMagnus Damm return 0; 382a07e103eSMagnus Damm 383a07e103eSMagnus Damm err1: 3841cfe6f8cSMagnus Damm irq_domain_remove(p->irq_domain); 385a07e103eSMagnus Damm err0: 386a07e103eSMagnus Damm return ret; 387a07e103eSMagnus Damm } 388a07e103eSMagnus Damm 389206210ceSBill Pemberton static int em_gio_remove(struct platform_device *pdev) 390a07e103eSMagnus Damm { 391a07e103eSMagnus Damm struct em_gio_priv *p = platform_get_drvdata(pdev); 392a07e103eSMagnus Damm int ret; 393a07e103eSMagnus Damm 394a07e103eSMagnus Damm ret = gpiochip_remove(&p->gpio_chip); 395a07e103eSMagnus Damm if (ret) 396a07e103eSMagnus Damm return ret; 397a07e103eSMagnus Damm 39816310819SAxel Lin irq_domain_remove(p->irq_domain); 399a07e103eSMagnus Damm return 0; 400a07e103eSMagnus Damm } 401a07e103eSMagnus Damm 402753c5983SMagnus Damm static const struct of_device_id em_gio_dt_ids[] = { 403753c5983SMagnus Damm { .compatible = "renesas,em-gio", }, 404753c5983SMagnus Damm {}, 405753c5983SMagnus Damm }; 406753c5983SMagnus Damm MODULE_DEVICE_TABLE(of, em_gio_dt_ids); 407753c5983SMagnus Damm 408a07e103eSMagnus Damm static struct platform_driver em_gio_device_driver = { 409a07e103eSMagnus Damm .probe = em_gio_probe, 4108283c4ffSBill Pemberton .remove = em_gio_remove, 411a07e103eSMagnus Damm .driver = { 412a07e103eSMagnus Damm .name = "em_gio", 413753c5983SMagnus Damm .of_match_table = em_gio_dt_ids, 414753c5983SMagnus Damm .owner = THIS_MODULE, 415a07e103eSMagnus Damm } 416a07e103eSMagnus Damm }; 417a07e103eSMagnus Damm 418753c5983SMagnus Damm static int __init em_gio_init(void) 419753c5983SMagnus Damm { 420753c5983SMagnus Damm return platform_driver_register(&em_gio_device_driver); 421753c5983SMagnus Damm } 422753c5983SMagnus Damm postcore_initcall(em_gio_init); 423753c5983SMagnus Damm 424753c5983SMagnus Damm static void __exit em_gio_exit(void) 425753c5983SMagnus Damm { 426753c5983SMagnus Damm platform_driver_unregister(&em_gio_device_driver); 427753c5983SMagnus Damm } 428753c5983SMagnus Damm module_exit(em_gio_exit); 429a07e103eSMagnus Damm 430a07e103eSMagnus Damm MODULE_AUTHOR("Magnus Damm"); 431a07e103eSMagnus Damm MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver"); 432a07e103eSMagnus Damm MODULE_LICENSE("GPL v2"); 433