1a07e103eSMagnus Damm /* 2a07e103eSMagnus Damm * Emma Mobile GPIO Support - GIO 3a07e103eSMagnus Damm * 4a07e103eSMagnus Damm * Copyright (C) 2012 Magnus Damm 5a07e103eSMagnus Damm * 6a07e103eSMagnus Damm * This program is free software; you can redistribute it and/or modify 7a07e103eSMagnus Damm * it under the terms of the GNU General Public License as published by 8a07e103eSMagnus Damm * the Free Software Foundation; either version 2 of the License 9a07e103eSMagnus Damm * 10a07e103eSMagnus Damm * This program is distributed in the hope that it will be useful, 11a07e103eSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 12a07e103eSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13a07e103eSMagnus Damm * GNU General Public License for more details. 14a07e103eSMagnus Damm * 15a07e103eSMagnus Damm * You should have received a copy of the GNU General Public License 16a07e103eSMagnus Damm * along with this program; if not, write to the Free Software 17a07e103eSMagnus Damm * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18a07e103eSMagnus Damm */ 19a07e103eSMagnus Damm 20a07e103eSMagnus Damm #include <linux/init.h> 21a07e103eSMagnus Damm #include <linux/platform_device.h> 22a07e103eSMagnus Damm #include <linux/spinlock.h> 23a07e103eSMagnus Damm #include <linux/interrupt.h> 24a07e103eSMagnus Damm #include <linux/ioport.h> 25a07e103eSMagnus Damm #include <linux/io.h> 26a07e103eSMagnus Damm #include <linux/irq.h> 27a07e103eSMagnus Damm #include <linux/irqdomain.h> 28a07e103eSMagnus Damm #include <linux/bitops.h> 29a07e103eSMagnus Damm #include <linux/err.h> 30a07e103eSMagnus Damm #include <linux/gpio.h> 31a07e103eSMagnus Damm #include <linux/slab.h> 32a07e103eSMagnus Damm #include <linux/module.h> 33a07e103eSMagnus Damm #include <linux/platform_data/gpio-em.h> 34a07e103eSMagnus Damm 35a07e103eSMagnus Damm struct em_gio_priv { 36a07e103eSMagnus Damm void __iomem *base0; 37a07e103eSMagnus Damm void __iomem *base1; 38a07e103eSMagnus Damm spinlock_t sense_lock; 39a07e103eSMagnus Damm struct platform_device *pdev; 40a07e103eSMagnus Damm struct gpio_chip gpio_chip; 41a07e103eSMagnus Damm struct irq_chip irq_chip; 42a07e103eSMagnus Damm struct irq_domain *irq_domain; 43a07e103eSMagnus Damm }; 44a07e103eSMagnus Damm 45a07e103eSMagnus Damm #define GIO_E1 0x00 46a07e103eSMagnus Damm #define GIO_E0 0x04 47a07e103eSMagnus Damm #define GIO_EM 0x04 48a07e103eSMagnus Damm #define GIO_OL 0x08 49a07e103eSMagnus Damm #define GIO_OH 0x0c 50a07e103eSMagnus Damm #define GIO_I 0x10 51a07e103eSMagnus Damm #define GIO_IIA 0x14 52a07e103eSMagnus Damm #define GIO_IEN 0x18 53a07e103eSMagnus Damm #define GIO_IDS 0x1c 54a07e103eSMagnus Damm #define GIO_IIM 0x1c 55a07e103eSMagnus Damm #define GIO_RAW 0x20 56a07e103eSMagnus Damm #define GIO_MST 0x24 57a07e103eSMagnus Damm #define GIO_IIR 0x28 58a07e103eSMagnus Damm 59a07e103eSMagnus Damm #define GIO_IDT0 0x40 60a07e103eSMagnus Damm #define GIO_IDT1 0x44 61a07e103eSMagnus Damm #define GIO_IDT2 0x48 62a07e103eSMagnus Damm #define GIO_IDT3 0x4c 63a07e103eSMagnus Damm #define GIO_RAWBL 0x50 64a07e103eSMagnus Damm #define GIO_RAWBH 0x54 65a07e103eSMagnus Damm #define GIO_IRBL 0x58 66a07e103eSMagnus Damm #define GIO_IRBH 0x5c 67a07e103eSMagnus Damm 68a07e103eSMagnus Damm #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4)) 69a07e103eSMagnus Damm 70a07e103eSMagnus Damm static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs) 71a07e103eSMagnus Damm { 72a07e103eSMagnus Damm if (offs < GIO_IDT0) 73a07e103eSMagnus Damm return ioread32(p->base0 + offs); 74a07e103eSMagnus Damm else 75a07e103eSMagnus Damm return ioread32(p->base1 + (offs - GIO_IDT0)); 76a07e103eSMagnus Damm } 77a07e103eSMagnus Damm 78a07e103eSMagnus Damm static inline void em_gio_write(struct em_gio_priv *p, int offs, 79a07e103eSMagnus Damm unsigned long value) 80a07e103eSMagnus Damm { 81a07e103eSMagnus Damm if (offs < GIO_IDT0) 82a07e103eSMagnus Damm iowrite32(value, p->base0 + offs); 83a07e103eSMagnus Damm else 84a07e103eSMagnus Damm iowrite32(value, p->base1 + (offs - GIO_IDT0)); 85a07e103eSMagnus Damm } 86a07e103eSMagnus Damm 87a07e103eSMagnus Damm static void em_gio_irq_disable(struct irq_data *d) 88a07e103eSMagnus Damm { 89a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 90a07e103eSMagnus Damm 91a07e103eSMagnus Damm em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d))); 92a07e103eSMagnus Damm } 93a07e103eSMagnus Damm 94a07e103eSMagnus Damm static void em_gio_irq_enable(struct irq_data *d) 95a07e103eSMagnus Damm { 96a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 97a07e103eSMagnus Damm 98a07e103eSMagnus Damm em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d))); 99a07e103eSMagnus Damm } 100a07e103eSMagnus Damm 101a07e103eSMagnus Damm #define GIO_ASYNC(x) (x + 8) 102a07e103eSMagnus Damm 103a07e103eSMagnus Damm static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { 104a07e103eSMagnus Damm [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00), 105a07e103eSMagnus Damm [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01), 106a07e103eSMagnus Damm [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02), 107a07e103eSMagnus Damm [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03), 108a07e103eSMagnus Damm [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04), 109a07e103eSMagnus Damm }; 110a07e103eSMagnus Damm 111a07e103eSMagnus Damm static int em_gio_irq_set_type(struct irq_data *d, unsigned int type) 112a07e103eSMagnus Damm { 113a07e103eSMagnus Damm unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK]; 114a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 115a07e103eSMagnus Damm unsigned int reg, offset, shift; 116a07e103eSMagnus Damm unsigned long flags; 117a07e103eSMagnus Damm unsigned long tmp; 118a07e103eSMagnus Damm 119a07e103eSMagnus Damm if (!value) 120a07e103eSMagnus Damm return -EINVAL; 121a07e103eSMagnus Damm 122a07e103eSMagnus Damm offset = irqd_to_hwirq(d); 123a07e103eSMagnus Damm 124a07e103eSMagnus Damm pr_debug("gio: sense irq = %d, mode = %d\n", offset, value); 125a07e103eSMagnus Damm 126a07e103eSMagnus Damm /* 8 x 4 bit fields in 4 IDT registers */ 127a07e103eSMagnus Damm reg = GIO_IDT(offset >> 3); 128a07e103eSMagnus Damm shift = (offset & 0x07) << 4; 129a07e103eSMagnus Damm 130a07e103eSMagnus Damm spin_lock_irqsave(&p->sense_lock, flags); 131a07e103eSMagnus Damm 132a07e103eSMagnus Damm /* disable the interrupt in IIA */ 133a07e103eSMagnus Damm tmp = em_gio_read(p, GIO_IIA); 134a07e103eSMagnus Damm tmp &= ~BIT(offset); 135a07e103eSMagnus Damm em_gio_write(p, GIO_IIA, tmp); 136a07e103eSMagnus Damm 137a07e103eSMagnus Damm /* change the sense setting in IDT */ 138a07e103eSMagnus Damm tmp = em_gio_read(p, reg); 139a07e103eSMagnus Damm tmp &= ~(0xf << shift); 140a07e103eSMagnus Damm tmp |= value << shift; 141a07e103eSMagnus Damm em_gio_write(p, reg, tmp); 142a07e103eSMagnus Damm 143a07e103eSMagnus Damm /* clear pending interrupts */ 144a07e103eSMagnus Damm em_gio_write(p, GIO_IIR, BIT(offset)); 145a07e103eSMagnus Damm 146a07e103eSMagnus Damm /* enable the interrupt in IIA */ 147a07e103eSMagnus Damm tmp = em_gio_read(p, GIO_IIA); 148a07e103eSMagnus Damm tmp |= BIT(offset); 149a07e103eSMagnus Damm em_gio_write(p, GIO_IIA, tmp); 150a07e103eSMagnus Damm 151a07e103eSMagnus Damm spin_unlock_irqrestore(&p->sense_lock, flags); 152a07e103eSMagnus Damm 153a07e103eSMagnus Damm return 0; 154a07e103eSMagnus Damm } 155a07e103eSMagnus Damm 156a07e103eSMagnus Damm static irqreturn_t em_gio_irq_handler(int irq, void *dev_id) 157a07e103eSMagnus Damm { 158a07e103eSMagnus Damm struct em_gio_priv *p = dev_id; 159a07e103eSMagnus Damm unsigned long pending; 160a07e103eSMagnus Damm unsigned int offset, irqs_handled = 0; 161a07e103eSMagnus Damm 162a07e103eSMagnus Damm while ((pending = em_gio_read(p, GIO_MST))) { 163a07e103eSMagnus Damm offset = __ffs(pending); 164a07e103eSMagnus Damm em_gio_write(p, GIO_IIR, BIT(offset)); 165a07e103eSMagnus Damm generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); 166a07e103eSMagnus Damm irqs_handled++; 167a07e103eSMagnus Damm } 168a07e103eSMagnus Damm 169a07e103eSMagnus Damm return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 170a07e103eSMagnus Damm } 171a07e103eSMagnus Damm 172a07e103eSMagnus Damm static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip) 173a07e103eSMagnus Damm { 174a07e103eSMagnus Damm return container_of(chip, struct em_gio_priv, gpio_chip); 175a07e103eSMagnus Damm } 176a07e103eSMagnus Damm 177a07e103eSMagnus Damm static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset) 178a07e103eSMagnus Damm { 179a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset)); 180a07e103eSMagnus Damm return 0; 181a07e103eSMagnus Damm } 182a07e103eSMagnus Damm 183a07e103eSMagnus Damm static int em_gio_get(struct gpio_chip *chip, unsigned offset) 184a07e103eSMagnus Damm { 185a07e103eSMagnus Damm return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset)); 186a07e103eSMagnus Damm } 187a07e103eSMagnus Damm 188a07e103eSMagnus Damm static void __em_gio_set(struct gpio_chip *chip, unsigned int reg, 189a07e103eSMagnus Damm unsigned shift, int value) 190a07e103eSMagnus Damm { 191a07e103eSMagnus Damm /* upper 16 bits contains mask and lower 16 actual value */ 192a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), reg, 193a07e103eSMagnus Damm (1 << (shift + 16)) | (value << shift)); 194a07e103eSMagnus Damm } 195a07e103eSMagnus Damm 196a07e103eSMagnus Damm static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value) 197a07e103eSMagnus Damm { 198a07e103eSMagnus Damm /* output is split into two registers */ 199a07e103eSMagnus Damm if (offset < 16) 200a07e103eSMagnus Damm __em_gio_set(chip, GIO_OL, offset, value); 201a07e103eSMagnus Damm else 202a07e103eSMagnus Damm __em_gio_set(chip, GIO_OH, offset - 16, value); 203a07e103eSMagnus Damm } 204a07e103eSMagnus Damm 205a07e103eSMagnus Damm static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset, 206a07e103eSMagnus Damm int value) 207a07e103eSMagnus Damm { 208a07e103eSMagnus Damm /* write GPIO value to output before selecting output mode of pin */ 209a07e103eSMagnus Damm em_gio_set(chip, offset, value); 210a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset)); 211a07e103eSMagnus Damm return 0; 212a07e103eSMagnus Damm } 213a07e103eSMagnus Damm 214a07e103eSMagnus Damm static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset) 215a07e103eSMagnus Damm { 2167385500aSLinus Walleij return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); 217a07e103eSMagnus Damm } 218a07e103eSMagnus Damm 219a07e103eSMagnus Damm static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int virq, 220a07e103eSMagnus Damm irq_hw_number_t hw) 221a07e103eSMagnus Damm { 222a07e103eSMagnus Damm struct em_gio_priv *p = h->host_data; 223a07e103eSMagnus Damm 224a07e103eSMagnus Damm pr_debug("gio: map hw irq = %d, virq = %d\n", (int)hw, virq); 225a07e103eSMagnus Damm 226a07e103eSMagnus Damm irq_set_chip_data(virq, h->host_data); 227a07e103eSMagnus Damm irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); 228a07e103eSMagnus Damm set_irq_flags(virq, IRQF_VALID); /* kill me now */ 229a07e103eSMagnus Damm return 0; 230a07e103eSMagnus Damm } 231a07e103eSMagnus Damm 232a07e103eSMagnus Damm static struct irq_domain_ops em_gio_irq_domain_ops = { 233a07e103eSMagnus Damm .map = em_gio_irq_domain_map, 234753c5983SMagnus Damm .xlate = irq_domain_xlate_twocell, 235a07e103eSMagnus Damm }; 236a07e103eSMagnus Damm 2373836309dSBill Pemberton static int em_gio_probe(struct platform_device *pdev) 238a07e103eSMagnus Damm { 239753c5983SMagnus Damm struct gpio_em_config pdata_dt; 240a07e103eSMagnus Damm struct gpio_em_config *pdata = pdev->dev.platform_data; 241a07e103eSMagnus Damm struct em_gio_priv *p; 242a07e103eSMagnus Damm struct resource *io[2], *irq[2]; 243a07e103eSMagnus Damm struct gpio_chip *gpio_chip; 244a07e103eSMagnus Damm struct irq_chip *irq_chip; 245a07e103eSMagnus Damm const char *name = dev_name(&pdev->dev); 246a07e103eSMagnus Damm int ret; 247a07e103eSMagnus Damm 248a07e103eSMagnus Damm p = kzalloc(sizeof(*p), GFP_KERNEL); 249a07e103eSMagnus Damm if (!p) { 250a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to allocate driver data\n"); 251a07e103eSMagnus Damm ret = -ENOMEM; 252a07e103eSMagnus Damm goto err0; 253a07e103eSMagnus Damm } 254a07e103eSMagnus Damm 255a07e103eSMagnus Damm p->pdev = pdev; 256a07e103eSMagnus Damm platform_set_drvdata(pdev, p); 257a07e103eSMagnus Damm spin_lock_init(&p->sense_lock); 258a07e103eSMagnus Damm 259a07e103eSMagnus Damm io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0); 260a07e103eSMagnus Damm io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1); 261a07e103eSMagnus Damm irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 262a07e103eSMagnus Damm irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 263a07e103eSMagnus Damm 264753c5983SMagnus Damm if (!io[0] || !io[1] || !irq[0] || !irq[1]) { 265753c5983SMagnus Damm dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); 266a07e103eSMagnus Damm ret = -EINVAL; 267a07e103eSMagnus Damm goto err1; 268a07e103eSMagnus Damm } 269a07e103eSMagnus Damm 270a07e103eSMagnus Damm p->base0 = ioremap_nocache(io[0]->start, resource_size(io[0])); 271a07e103eSMagnus Damm if (!p->base0) { 272a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to remap low I/O memory\n"); 273a07e103eSMagnus Damm ret = -ENXIO; 274a07e103eSMagnus Damm goto err1; 275a07e103eSMagnus Damm } 276a07e103eSMagnus Damm 277a07e103eSMagnus Damm p->base1 = ioremap_nocache(io[1]->start, resource_size(io[1])); 278a07e103eSMagnus Damm if (!p->base1) { 279a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to remap high I/O memory\n"); 280a07e103eSMagnus Damm ret = -ENXIO; 281a07e103eSMagnus Damm goto err2; 282a07e103eSMagnus Damm } 283a07e103eSMagnus Damm 284753c5983SMagnus Damm if (!pdata) { 285753c5983SMagnus Damm memset(&pdata_dt, 0, sizeof(pdata_dt)); 286753c5983SMagnus Damm pdata = &pdata_dt; 287753c5983SMagnus Damm 288753c5983SMagnus Damm if (of_property_read_u32(pdev->dev.of_node, "ngpios", 289753c5983SMagnus Damm &pdata->number_of_pins)) { 290753c5983SMagnus Damm dev_err(&pdev->dev, "Missing ngpios OF property\n"); 291753c5983SMagnus Damm ret = -EINVAL; 292753c5983SMagnus Damm goto err3; 293753c5983SMagnus Damm } 294753c5983SMagnus Damm 295753c5983SMagnus Damm ret = of_alias_get_id(pdev->dev.of_node, "gpio"); 296753c5983SMagnus Damm if (ret < 0) { 297753c5983SMagnus Damm dev_err(&pdev->dev, "Couldn't get OF id\n"); 298753c5983SMagnus Damm goto err3; 299753c5983SMagnus Damm } 300753c5983SMagnus Damm pdata->gpio_base = ret * 32; /* 32 GPIOs per instance */ 301753c5983SMagnus Damm } 302753c5983SMagnus Damm 303a07e103eSMagnus Damm gpio_chip = &p->gpio_chip; 304a07e103eSMagnus Damm gpio_chip->direction_input = em_gio_direction_input; 305a07e103eSMagnus Damm gpio_chip->get = em_gio_get; 306a07e103eSMagnus Damm gpio_chip->direction_output = em_gio_direction_output; 307a07e103eSMagnus Damm gpio_chip->set = em_gio_set; 308a07e103eSMagnus Damm gpio_chip->to_irq = em_gio_to_irq; 309a07e103eSMagnus Damm gpio_chip->label = name; 310a07e103eSMagnus Damm gpio_chip->owner = THIS_MODULE; 311a07e103eSMagnus Damm gpio_chip->base = pdata->gpio_base; 312a07e103eSMagnus Damm gpio_chip->ngpio = pdata->number_of_pins; 313a07e103eSMagnus Damm 314a07e103eSMagnus Damm irq_chip = &p->irq_chip; 315a07e103eSMagnus Damm irq_chip->name = name; 316a07e103eSMagnus Damm irq_chip->irq_mask = em_gio_irq_disable; 317a07e103eSMagnus Damm irq_chip->irq_unmask = em_gio_irq_enable; 318a07e103eSMagnus Damm irq_chip->irq_enable = em_gio_irq_enable; 319a07e103eSMagnus Damm irq_chip->irq_disable = em_gio_irq_disable; 320a07e103eSMagnus Damm irq_chip->irq_set_type = em_gio_irq_set_type; 321a07e103eSMagnus Damm irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; 322a07e103eSMagnus Damm 323c7886b18SMagnus Damm p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 3247385500aSLinus Walleij pdata->number_of_pins, 325c7886b18SMagnus Damm pdata->irq_base, 3267385500aSLinus Walleij &em_gio_irq_domain_ops, p); 32716310819SAxel Lin if (!p->irq_domain) { 32816310819SAxel Lin ret = -ENXIO; 329a07e103eSMagnus Damm dev_err(&pdev->dev, "cannot initialize irq domain\n"); 330a07e103eSMagnus Damm goto err3; 331a07e103eSMagnus Damm } 332a07e103eSMagnus Damm 333a07e103eSMagnus Damm if (request_irq(irq[0]->start, em_gio_irq_handler, 0, name, p)) { 334a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to request low IRQ\n"); 335a07e103eSMagnus Damm ret = -ENOENT; 336a07e103eSMagnus Damm goto err4; 337a07e103eSMagnus Damm } 338a07e103eSMagnus Damm 339a07e103eSMagnus Damm if (request_irq(irq[1]->start, em_gio_irq_handler, 0, name, p)) { 340a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to request high IRQ\n"); 341a07e103eSMagnus Damm ret = -ENOENT; 342a07e103eSMagnus Damm goto err5; 343a07e103eSMagnus Damm } 344a07e103eSMagnus Damm 345a07e103eSMagnus Damm ret = gpiochip_add(gpio_chip); 346a07e103eSMagnus Damm if (ret) { 347a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to add GPIO controller\n"); 348a07e103eSMagnus Damm goto err6; 349a07e103eSMagnus Damm } 350a07e103eSMagnus Damm return 0; 351a07e103eSMagnus Damm 352a07e103eSMagnus Damm err6: 353a07e103eSMagnus Damm free_irq(irq[1]->start, pdev); 354a07e103eSMagnus Damm err5: 355a07e103eSMagnus Damm free_irq(irq[0]->start, pdev); 356a07e103eSMagnus Damm err4: 3577385500aSLinus Walleij irq_domain_remove(p->irq_domain); 358a07e103eSMagnus Damm err3: 359a07e103eSMagnus Damm iounmap(p->base1); 360a07e103eSMagnus Damm err2: 361a07e103eSMagnus Damm iounmap(p->base0); 362a07e103eSMagnus Damm err1: 363a07e103eSMagnus Damm kfree(p); 364a07e103eSMagnus Damm err0: 365a07e103eSMagnus Damm return ret; 366a07e103eSMagnus Damm } 367a07e103eSMagnus Damm 368206210ceSBill Pemberton static int em_gio_remove(struct platform_device *pdev) 369a07e103eSMagnus Damm { 370a07e103eSMagnus Damm struct em_gio_priv *p = platform_get_drvdata(pdev); 371a07e103eSMagnus Damm struct resource *irq[2]; 372a07e103eSMagnus Damm int ret; 373a07e103eSMagnus Damm 374a07e103eSMagnus Damm ret = gpiochip_remove(&p->gpio_chip); 375a07e103eSMagnus Damm if (ret) 376a07e103eSMagnus Damm return ret; 377a07e103eSMagnus Damm 378a07e103eSMagnus Damm irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 379a07e103eSMagnus Damm irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 380a07e103eSMagnus Damm 381a07e103eSMagnus Damm free_irq(irq[1]->start, pdev); 382a07e103eSMagnus Damm free_irq(irq[0]->start, pdev); 38316310819SAxel Lin irq_domain_remove(p->irq_domain); 384a07e103eSMagnus Damm iounmap(p->base1); 385a07e103eSMagnus Damm iounmap(p->base0); 386a07e103eSMagnus Damm kfree(p); 387a07e103eSMagnus Damm return 0; 388a07e103eSMagnus Damm } 389a07e103eSMagnus Damm 390753c5983SMagnus Damm static const struct of_device_id em_gio_dt_ids[] = { 391753c5983SMagnus Damm { .compatible = "renesas,em-gio", }, 392753c5983SMagnus Damm {}, 393753c5983SMagnus Damm }; 394753c5983SMagnus Damm MODULE_DEVICE_TABLE(of, em_gio_dt_ids); 395753c5983SMagnus Damm 396a07e103eSMagnus Damm static struct platform_driver em_gio_device_driver = { 397a07e103eSMagnus Damm .probe = em_gio_probe, 3988283c4ffSBill Pemberton .remove = em_gio_remove, 399a07e103eSMagnus Damm .driver = { 400a07e103eSMagnus Damm .name = "em_gio", 401753c5983SMagnus Damm .of_match_table = em_gio_dt_ids, 402753c5983SMagnus Damm .owner = THIS_MODULE, 403a07e103eSMagnus Damm } 404a07e103eSMagnus Damm }; 405a07e103eSMagnus Damm 406753c5983SMagnus Damm static int __init em_gio_init(void) 407753c5983SMagnus Damm { 408753c5983SMagnus Damm return platform_driver_register(&em_gio_device_driver); 409753c5983SMagnus Damm } 410753c5983SMagnus Damm postcore_initcall(em_gio_init); 411753c5983SMagnus Damm 412753c5983SMagnus Damm static void __exit em_gio_exit(void) 413753c5983SMagnus Damm { 414753c5983SMagnus Damm platform_driver_unregister(&em_gio_device_driver); 415753c5983SMagnus Damm } 416753c5983SMagnus Damm module_exit(em_gio_exit); 417a07e103eSMagnus Damm 418a07e103eSMagnus Damm MODULE_AUTHOR("Magnus Damm"); 419a07e103eSMagnus Damm MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver"); 420a07e103eSMagnus Damm MODULE_LICENSE("GPL v2"); 421