1a07e103eSMagnus Damm /* 2a07e103eSMagnus Damm * Emma Mobile GPIO Support - GIO 3a07e103eSMagnus Damm * 4a07e103eSMagnus Damm * Copyright (C) 2012 Magnus Damm 5a07e103eSMagnus Damm * 6a07e103eSMagnus Damm * This program is free software; you can redistribute it and/or modify 7a07e103eSMagnus Damm * it under the terms of the GNU General Public License as published by 8a07e103eSMagnus Damm * the Free Software Foundation; either version 2 of the License 9a07e103eSMagnus Damm * 10a07e103eSMagnus Damm * This program is distributed in the hope that it will be useful, 11a07e103eSMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 12a07e103eSMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13a07e103eSMagnus Damm * GNU General Public License for more details. 14a07e103eSMagnus Damm * 15a07e103eSMagnus Damm * You should have received a copy of the GNU General Public License 16a07e103eSMagnus Damm * along with this program; if not, write to the Free Software 17a07e103eSMagnus Damm * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18a07e103eSMagnus Damm */ 19a07e103eSMagnus Damm 20a07e103eSMagnus Damm #include <linux/init.h> 21a07e103eSMagnus Damm #include <linux/platform_device.h> 22a07e103eSMagnus Damm #include <linux/spinlock.h> 23a07e103eSMagnus Damm #include <linux/interrupt.h> 24a07e103eSMagnus Damm #include <linux/ioport.h> 25a07e103eSMagnus Damm #include <linux/io.h> 26a07e103eSMagnus Damm #include <linux/irq.h> 27a07e103eSMagnus Damm #include <linux/irqdomain.h> 28a07e103eSMagnus Damm #include <linux/bitops.h> 29a07e103eSMagnus Damm #include <linux/err.h> 30a07e103eSMagnus Damm #include <linux/gpio.h> 31a07e103eSMagnus Damm #include <linux/slab.h> 32a07e103eSMagnus Damm #include <linux/module.h> 33640efa08SMagnus Damm #include <linux/pinctrl/consumer.h> 34a07e103eSMagnus Damm 35a07e103eSMagnus Damm struct em_gio_priv { 36a07e103eSMagnus Damm void __iomem *base0; 37a07e103eSMagnus Damm void __iomem *base1; 38a07e103eSMagnus Damm spinlock_t sense_lock; 39a07e103eSMagnus Damm struct platform_device *pdev; 40a07e103eSMagnus Damm struct gpio_chip gpio_chip; 41a07e103eSMagnus Damm struct irq_chip irq_chip; 42a07e103eSMagnus Damm struct irq_domain *irq_domain; 43a07e103eSMagnus Damm }; 44a07e103eSMagnus Damm 45a07e103eSMagnus Damm #define GIO_E1 0x00 46a07e103eSMagnus Damm #define GIO_E0 0x04 47a07e103eSMagnus Damm #define GIO_EM 0x04 48a07e103eSMagnus Damm #define GIO_OL 0x08 49a07e103eSMagnus Damm #define GIO_OH 0x0c 50a07e103eSMagnus Damm #define GIO_I 0x10 51a07e103eSMagnus Damm #define GIO_IIA 0x14 52a07e103eSMagnus Damm #define GIO_IEN 0x18 53a07e103eSMagnus Damm #define GIO_IDS 0x1c 54a07e103eSMagnus Damm #define GIO_IIM 0x1c 55a07e103eSMagnus Damm #define GIO_RAW 0x20 56a07e103eSMagnus Damm #define GIO_MST 0x24 57a07e103eSMagnus Damm #define GIO_IIR 0x28 58a07e103eSMagnus Damm 59a07e103eSMagnus Damm #define GIO_IDT0 0x40 60a07e103eSMagnus Damm #define GIO_IDT1 0x44 61a07e103eSMagnus Damm #define GIO_IDT2 0x48 62a07e103eSMagnus Damm #define GIO_IDT3 0x4c 63a07e103eSMagnus Damm #define GIO_RAWBL 0x50 64a07e103eSMagnus Damm #define GIO_RAWBH 0x54 65a07e103eSMagnus Damm #define GIO_IRBL 0x58 66a07e103eSMagnus Damm #define GIO_IRBH 0x5c 67a07e103eSMagnus Damm 68a07e103eSMagnus Damm #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4)) 69a07e103eSMagnus Damm 70a07e103eSMagnus Damm static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs) 71a07e103eSMagnus Damm { 72a07e103eSMagnus Damm if (offs < GIO_IDT0) 73a07e103eSMagnus Damm return ioread32(p->base0 + offs); 74a07e103eSMagnus Damm else 75a07e103eSMagnus Damm return ioread32(p->base1 + (offs - GIO_IDT0)); 76a07e103eSMagnus Damm } 77a07e103eSMagnus Damm 78a07e103eSMagnus Damm static inline void em_gio_write(struct em_gio_priv *p, int offs, 79a07e103eSMagnus Damm unsigned long value) 80a07e103eSMagnus Damm { 81a07e103eSMagnus Damm if (offs < GIO_IDT0) 82a07e103eSMagnus Damm iowrite32(value, p->base0 + offs); 83a07e103eSMagnus Damm else 84a07e103eSMagnus Damm iowrite32(value, p->base1 + (offs - GIO_IDT0)); 85a07e103eSMagnus Damm } 86a07e103eSMagnus Damm 87a07e103eSMagnus Damm static void em_gio_irq_disable(struct irq_data *d) 88a07e103eSMagnus Damm { 89a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 90a07e103eSMagnus Damm 91a07e103eSMagnus Damm em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d))); 92a07e103eSMagnus Damm } 93a07e103eSMagnus Damm 94a07e103eSMagnus Damm static void em_gio_irq_enable(struct irq_data *d) 95a07e103eSMagnus Damm { 96a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 97a07e103eSMagnus Damm 98a07e103eSMagnus Damm em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d))); 99a07e103eSMagnus Damm } 100a07e103eSMagnus Damm 10157ef0428SLinus Walleij static int em_gio_irq_reqres(struct irq_data *d) 1020dc61623SLinus Walleij { 1030dc61623SLinus Walleij struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 1040dc61623SLinus Walleij 105e3a2e878SAlexandre Courbot if (gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) { 10658383c78SLinus Walleij dev_err(p->gpio_chip.parent, 1070dc61623SLinus Walleij "unable to lock HW IRQ %lu for IRQ\n", 1080dc61623SLinus Walleij irqd_to_hwirq(d)); 10957ef0428SLinus Walleij return -EINVAL; 11057ef0428SLinus Walleij } 1110dc61623SLinus Walleij return 0; 1120dc61623SLinus Walleij } 1130dc61623SLinus Walleij 11457ef0428SLinus Walleij static void em_gio_irq_relres(struct irq_data *d) 1150dc61623SLinus Walleij { 1160dc61623SLinus Walleij struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 1170dc61623SLinus Walleij 118e3a2e878SAlexandre Courbot gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d)); 1190dc61623SLinus Walleij } 1200dc61623SLinus Walleij 1210dc61623SLinus Walleij 122a07e103eSMagnus Damm #define GIO_ASYNC(x) (x + 8) 123a07e103eSMagnus Damm 124a07e103eSMagnus Damm static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = { 125a07e103eSMagnus Damm [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00), 126a07e103eSMagnus Damm [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01), 127a07e103eSMagnus Damm [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02), 128a07e103eSMagnus Damm [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03), 129a07e103eSMagnus Damm [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04), 130a07e103eSMagnus Damm }; 131a07e103eSMagnus Damm 132a07e103eSMagnus Damm static int em_gio_irq_set_type(struct irq_data *d, unsigned int type) 133a07e103eSMagnus Damm { 134a07e103eSMagnus Damm unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK]; 135a9f77c93SAxel Lin struct em_gio_priv *p = irq_data_get_irq_chip_data(d); 136a07e103eSMagnus Damm unsigned int reg, offset, shift; 137a07e103eSMagnus Damm unsigned long flags; 138a07e103eSMagnus Damm unsigned long tmp; 139a07e103eSMagnus Damm 140a07e103eSMagnus Damm if (!value) 141a07e103eSMagnus Damm return -EINVAL; 142a07e103eSMagnus Damm 143a07e103eSMagnus Damm offset = irqd_to_hwirq(d); 144a07e103eSMagnus Damm 145a07e103eSMagnus Damm pr_debug("gio: sense irq = %d, mode = %d\n", offset, value); 146a07e103eSMagnus Damm 147a07e103eSMagnus Damm /* 8 x 4 bit fields in 4 IDT registers */ 148a07e103eSMagnus Damm reg = GIO_IDT(offset >> 3); 149a07e103eSMagnus Damm shift = (offset & 0x07) << 4; 150a07e103eSMagnus Damm 151a07e103eSMagnus Damm spin_lock_irqsave(&p->sense_lock, flags); 152a07e103eSMagnus Damm 153a07e103eSMagnus Damm /* disable the interrupt in IIA */ 154a07e103eSMagnus Damm tmp = em_gio_read(p, GIO_IIA); 155a07e103eSMagnus Damm tmp &= ~BIT(offset); 156a07e103eSMagnus Damm em_gio_write(p, GIO_IIA, tmp); 157a07e103eSMagnus Damm 158a07e103eSMagnus Damm /* change the sense setting in IDT */ 159a07e103eSMagnus Damm tmp = em_gio_read(p, reg); 160a07e103eSMagnus Damm tmp &= ~(0xf << shift); 161a07e103eSMagnus Damm tmp |= value << shift; 162a07e103eSMagnus Damm em_gio_write(p, reg, tmp); 163a07e103eSMagnus Damm 164a07e103eSMagnus Damm /* clear pending interrupts */ 165a07e103eSMagnus Damm em_gio_write(p, GIO_IIR, BIT(offset)); 166a07e103eSMagnus Damm 167a07e103eSMagnus Damm /* enable the interrupt in IIA */ 168a07e103eSMagnus Damm tmp = em_gio_read(p, GIO_IIA); 169a07e103eSMagnus Damm tmp |= BIT(offset); 170a07e103eSMagnus Damm em_gio_write(p, GIO_IIA, tmp); 171a07e103eSMagnus Damm 172a07e103eSMagnus Damm spin_unlock_irqrestore(&p->sense_lock, flags); 173a07e103eSMagnus Damm 174a07e103eSMagnus Damm return 0; 175a07e103eSMagnus Damm } 176a07e103eSMagnus Damm 177a07e103eSMagnus Damm static irqreturn_t em_gio_irq_handler(int irq, void *dev_id) 178a07e103eSMagnus Damm { 179a07e103eSMagnus Damm struct em_gio_priv *p = dev_id; 180a07e103eSMagnus Damm unsigned long pending; 181a07e103eSMagnus Damm unsigned int offset, irqs_handled = 0; 182a07e103eSMagnus Damm 183a07e103eSMagnus Damm while ((pending = em_gio_read(p, GIO_MST))) { 184a07e103eSMagnus Damm offset = __ffs(pending); 185a07e103eSMagnus Damm em_gio_write(p, GIO_IIR, BIT(offset)); 186a07e103eSMagnus Damm generic_handle_irq(irq_find_mapping(p->irq_domain, offset)); 187a07e103eSMagnus Damm irqs_handled++; 188a07e103eSMagnus Damm } 189a07e103eSMagnus Damm 190a07e103eSMagnus Damm return irqs_handled ? IRQ_HANDLED : IRQ_NONE; 191a07e103eSMagnus Damm } 192a07e103eSMagnus Damm 193a07e103eSMagnus Damm static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip) 194a07e103eSMagnus Damm { 195a07e103eSMagnus Damm return container_of(chip, struct em_gio_priv, gpio_chip); 196a07e103eSMagnus Damm } 197a07e103eSMagnus Damm 198a07e103eSMagnus Damm static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset) 199a07e103eSMagnus Damm { 200a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset)); 201a07e103eSMagnus Damm return 0; 202a07e103eSMagnus Damm } 203a07e103eSMagnus Damm 204a07e103eSMagnus Damm static int em_gio_get(struct gpio_chip *chip, unsigned offset) 205a07e103eSMagnus Damm { 206a07e103eSMagnus Damm return (int)(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset)); 207a07e103eSMagnus Damm } 208a07e103eSMagnus Damm 209a07e103eSMagnus Damm static void __em_gio_set(struct gpio_chip *chip, unsigned int reg, 210a07e103eSMagnus Damm unsigned shift, int value) 211a07e103eSMagnus Damm { 212a07e103eSMagnus Damm /* upper 16 bits contains mask and lower 16 actual value */ 213a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), reg, 2145f077644SJavier Martinez Canillas (BIT(shift + 16)) | (value << shift)); 215a07e103eSMagnus Damm } 216a07e103eSMagnus Damm 217a07e103eSMagnus Damm static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value) 218a07e103eSMagnus Damm { 219a07e103eSMagnus Damm /* output is split into two registers */ 220a07e103eSMagnus Damm if (offset < 16) 221a07e103eSMagnus Damm __em_gio_set(chip, GIO_OL, offset, value); 222a07e103eSMagnus Damm else 223a07e103eSMagnus Damm __em_gio_set(chip, GIO_OH, offset - 16, value); 224a07e103eSMagnus Damm } 225a07e103eSMagnus Damm 226a07e103eSMagnus Damm static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset, 227a07e103eSMagnus Damm int value) 228a07e103eSMagnus Damm { 229a07e103eSMagnus Damm /* write GPIO value to output before selecting output mode of pin */ 230a07e103eSMagnus Damm em_gio_set(chip, offset, value); 231a07e103eSMagnus Damm em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset)); 232a07e103eSMagnus Damm return 0; 233a07e103eSMagnus Damm } 234a07e103eSMagnus Damm 235a07e103eSMagnus Damm static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset) 236a07e103eSMagnus Damm { 2377385500aSLinus Walleij return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset); 238a07e103eSMagnus Damm } 239a07e103eSMagnus Damm 240640efa08SMagnus Damm static int em_gio_request(struct gpio_chip *chip, unsigned offset) 241640efa08SMagnus Damm { 242640efa08SMagnus Damm return pinctrl_request_gpio(chip->base + offset); 243640efa08SMagnus Damm } 244640efa08SMagnus Damm 245640efa08SMagnus Damm static void em_gio_free(struct gpio_chip *chip, unsigned offset) 246640efa08SMagnus Damm { 247640efa08SMagnus Damm pinctrl_free_gpio(chip->base + offset); 248640efa08SMagnus Damm 249640efa08SMagnus Damm /* Set the GPIO as an input to ensure that the next GPIO request won't 250640efa08SMagnus Damm * drive the GPIO pin as an output. 251640efa08SMagnus Damm */ 252640efa08SMagnus Damm em_gio_direction_input(chip, offset); 253640efa08SMagnus Damm } 254640efa08SMagnus Damm 2552d61e3e9SLinus Walleij static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq, 2562d61e3e9SLinus Walleij irq_hw_number_t hwirq) 257a07e103eSMagnus Damm { 258a07e103eSMagnus Damm struct em_gio_priv *p = h->host_data; 259a07e103eSMagnus Damm 2602d61e3e9SLinus Walleij pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq); 261a07e103eSMagnus Damm 2622d61e3e9SLinus Walleij irq_set_chip_data(irq, h->host_data); 2632d61e3e9SLinus Walleij irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq); 264a07e103eSMagnus Damm return 0; 265a07e103eSMagnus Damm } 266a07e103eSMagnus Damm 2670b354dc4SKrzysztof Kozlowski static const struct irq_domain_ops em_gio_irq_domain_ops = { 268a07e103eSMagnus Damm .map = em_gio_irq_domain_map, 269753c5983SMagnus Damm .xlate = irq_domain_xlate_twocell, 270a07e103eSMagnus Damm }; 271a07e103eSMagnus Damm 2723836309dSBill Pemberton static int em_gio_probe(struct platform_device *pdev) 273a07e103eSMagnus Damm { 274a07e103eSMagnus Damm struct em_gio_priv *p; 275a07e103eSMagnus Damm struct resource *io[2], *irq[2]; 276a07e103eSMagnus Damm struct gpio_chip *gpio_chip; 277a07e103eSMagnus Damm struct irq_chip *irq_chip; 278a07e103eSMagnus Damm const char *name = dev_name(&pdev->dev); 279527b397aSGeert Uytterhoeven unsigned int ngpios; 280a07e103eSMagnus Damm int ret; 281a07e103eSMagnus Damm 2821cfe6f8cSMagnus Damm p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); 283a07e103eSMagnus Damm if (!p) { 284a07e103eSMagnus Damm ret = -ENOMEM; 285a07e103eSMagnus Damm goto err0; 286a07e103eSMagnus Damm } 287a07e103eSMagnus Damm 288a07e103eSMagnus Damm p->pdev = pdev; 289a07e103eSMagnus Damm platform_set_drvdata(pdev, p); 290a07e103eSMagnus Damm spin_lock_init(&p->sense_lock); 291a07e103eSMagnus Damm 292a07e103eSMagnus Damm io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0); 293a07e103eSMagnus Damm io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1); 294a07e103eSMagnus Damm irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 295a07e103eSMagnus Damm irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1); 296a07e103eSMagnus Damm 297753c5983SMagnus Damm if (!io[0] || !io[1] || !irq[0] || !irq[1]) { 298753c5983SMagnus Damm dev_err(&pdev->dev, "missing IRQ or IOMEM\n"); 299a07e103eSMagnus Damm ret = -EINVAL; 3001cfe6f8cSMagnus Damm goto err0; 301a07e103eSMagnus Damm } 302a07e103eSMagnus Damm 3031cfe6f8cSMagnus Damm p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start, 3041cfe6f8cSMagnus Damm resource_size(io[0])); 305a07e103eSMagnus Damm if (!p->base0) { 306a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to remap low I/O memory\n"); 307a07e103eSMagnus Damm ret = -ENXIO; 3081cfe6f8cSMagnus Damm goto err0; 309a07e103eSMagnus Damm } 310a07e103eSMagnus Damm 3111cfe6f8cSMagnus Damm p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start, 3121cfe6f8cSMagnus Damm resource_size(io[1])); 313a07e103eSMagnus Damm if (!p->base1) { 314a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to remap high I/O memory\n"); 315a07e103eSMagnus Damm ret = -ENXIO; 3161cfe6f8cSMagnus Damm goto err0; 317a07e103eSMagnus Damm } 318a07e103eSMagnus Damm 319527b397aSGeert Uytterhoeven if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 320753c5983SMagnus Damm dev_err(&pdev->dev, "Missing ngpios OF property\n"); 321753c5983SMagnus Damm ret = -EINVAL; 3221cfe6f8cSMagnus Damm goto err0; 323753c5983SMagnus Damm } 324753c5983SMagnus Damm 325a07e103eSMagnus Damm gpio_chip = &p->gpio_chip; 326b5927854SIan Molton gpio_chip->of_node = pdev->dev.of_node; 327a07e103eSMagnus Damm gpio_chip->direction_input = em_gio_direction_input; 328a07e103eSMagnus Damm gpio_chip->get = em_gio_get; 329a07e103eSMagnus Damm gpio_chip->direction_output = em_gio_direction_output; 330a07e103eSMagnus Damm gpio_chip->set = em_gio_set; 331a07e103eSMagnus Damm gpio_chip->to_irq = em_gio_to_irq; 332640efa08SMagnus Damm gpio_chip->request = em_gio_request; 333640efa08SMagnus Damm gpio_chip->free = em_gio_free; 334a07e103eSMagnus Damm gpio_chip->label = name; 33558383c78SLinus Walleij gpio_chip->parent = &pdev->dev; 336a07e103eSMagnus Damm gpio_chip->owner = THIS_MODULE; 337527b397aSGeert Uytterhoeven gpio_chip->base = -1; 338527b397aSGeert Uytterhoeven gpio_chip->ngpio = ngpios; 339a07e103eSMagnus Damm 340a07e103eSMagnus Damm irq_chip = &p->irq_chip; 341a07e103eSMagnus Damm irq_chip->name = name; 342a07e103eSMagnus Damm irq_chip->irq_mask = em_gio_irq_disable; 343a07e103eSMagnus Damm irq_chip->irq_unmask = em_gio_irq_enable; 344a07e103eSMagnus Damm irq_chip->irq_set_type = em_gio_irq_set_type; 34557ef0428SLinus Walleij irq_chip->irq_request_resources = em_gio_irq_reqres; 34657ef0428SLinus Walleij irq_chip->irq_release_resources = em_gio_irq_relres; 34703621b60SMagnus Damm irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; 348a07e103eSMagnus Damm 349527b397aSGeert Uytterhoeven p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, ngpios, 0, 3507385500aSLinus Walleij &em_gio_irq_domain_ops, p); 35116310819SAxel Lin if (!p->irq_domain) { 35216310819SAxel Lin ret = -ENXIO; 353a07e103eSMagnus Damm dev_err(&pdev->dev, "cannot initialize irq domain\n"); 3541cfe6f8cSMagnus Damm goto err0; 355a07e103eSMagnus Damm } 356a07e103eSMagnus Damm 3571cfe6f8cSMagnus Damm if (devm_request_irq(&pdev->dev, irq[0]->start, 3581cfe6f8cSMagnus Damm em_gio_irq_handler, 0, name, p)) { 359a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to request low IRQ\n"); 360a07e103eSMagnus Damm ret = -ENOENT; 3611cfe6f8cSMagnus Damm goto err1; 362a07e103eSMagnus Damm } 363a07e103eSMagnus Damm 3641cfe6f8cSMagnus Damm if (devm_request_irq(&pdev->dev, irq[1]->start, 3651cfe6f8cSMagnus Damm em_gio_irq_handler, 0, name, p)) { 366a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to request high IRQ\n"); 367a07e103eSMagnus Damm ret = -ENOENT; 3681cfe6f8cSMagnus Damm goto err1; 369a07e103eSMagnus Damm } 370a07e103eSMagnus Damm 371a07e103eSMagnus Damm ret = gpiochip_add(gpio_chip); 372a07e103eSMagnus Damm if (ret) { 373a07e103eSMagnus Damm dev_err(&pdev->dev, "failed to add GPIO controller\n"); 3741cfe6f8cSMagnus Damm goto err1; 375a07e103eSMagnus Damm } 376640efa08SMagnus Damm 377a07e103eSMagnus Damm return 0; 378a07e103eSMagnus Damm 379a07e103eSMagnus Damm err1: 3801cfe6f8cSMagnus Damm irq_domain_remove(p->irq_domain); 381a07e103eSMagnus Damm err0: 382a07e103eSMagnus Damm return ret; 383a07e103eSMagnus Damm } 384a07e103eSMagnus Damm 385206210ceSBill Pemberton static int em_gio_remove(struct platform_device *pdev) 386a07e103eSMagnus Damm { 387a07e103eSMagnus Damm struct em_gio_priv *p = platform_get_drvdata(pdev); 388a07e103eSMagnus Damm 3899f5132aeSabdoulaye berthe gpiochip_remove(&p->gpio_chip); 390a07e103eSMagnus Damm 39116310819SAxel Lin irq_domain_remove(p->irq_domain); 392a07e103eSMagnus Damm return 0; 393a07e103eSMagnus Damm } 394a07e103eSMagnus Damm 395753c5983SMagnus Damm static const struct of_device_id em_gio_dt_ids[] = { 396753c5983SMagnus Damm { .compatible = "renesas,em-gio", }, 397753c5983SMagnus Damm {}, 398753c5983SMagnus Damm }; 399753c5983SMagnus Damm MODULE_DEVICE_TABLE(of, em_gio_dt_ids); 400753c5983SMagnus Damm 401a07e103eSMagnus Damm static struct platform_driver em_gio_device_driver = { 402a07e103eSMagnus Damm .probe = em_gio_probe, 4038283c4ffSBill Pemberton .remove = em_gio_remove, 404a07e103eSMagnus Damm .driver = { 405a07e103eSMagnus Damm .name = "em_gio", 406753c5983SMagnus Damm .of_match_table = em_gio_dt_ids, 407a07e103eSMagnus Damm } 408a07e103eSMagnus Damm }; 409a07e103eSMagnus Damm 410753c5983SMagnus Damm static int __init em_gio_init(void) 411753c5983SMagnus Damm { 412753c5983SMagnus Damm return platform_driver_register(&em_gio_device_driver); 413753c5983SMagnus Damm } 414753c5983SMagnus Damm postcore_initcall(em_gio_init); 415753c5983SMagnus Damm 416753c5983SMagnus Damm static void __exit em_gio_exit(void) 417753c5983SMagnus Damm { 418753c5983SMagnus Damm platform_driver_unregister(&em_gio_device_driver); 419753c5983SMagnus Damm } 420753c5983SMagnus Damm module_exit(em_gio_exit); 421a07e103eSMagnus Damm 422a07e103eSMagnus Damm MODULE_AUTHOR("Magnus Damm"); 423a07e103eSMagnus Damm MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver"); 424a07e103eSMagnus Damm MODULE_LICENSE("GPL v2"); 425