1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Spreadtrum Communications Inc. 4 * Copyright (C) 2018 Linaro Ltd. 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/gpio/driver.h> 9 #include <linux/interrupt.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/spinlock.h> 15 16 /* EIC registers definition */ 17 #define SPRD_EIC_DBNC_DATA 0x0 18 #define SPRD_EIC_DBNC_DMSK 0x4 19 #define SPRD_EIC_DBNC_IEV 0x14 20 #define SPRD_EIC_DBNC_IE 0x18 21 #define SPRD_EIC_DBNC_RIS 0x1c 22 #define SPRD_EIC_DBNC_MIS 0x20 23 #define SPRD_EIC_DBNC_IC 0x24 24 #define SPRD_EIC_DBNC_TRIG 0x28 25 #define SPRD_EIC_DBNC_CTRL0 0x40 26 27 #define SPRD_EIC_LATCH_INTEN 0x0 28 #define SPRD_EIC_LATCH_INTRAW 0x4 29 #define SPRD_EIC_LATCH_INTMSK 0x8 30 #define SPRD_EIC_LATCH_INTCLR 0xc 31 #define SPRD_EIC_LATCH_INTPOL 0x10 32 #define SPRD_EIC_LATCH_INTMODE 0x14 33 34 #define SPRD_EIC_ASYNC_INTIE 0x0 35 #define SPRD_EIC_ASYNC_INTRAW 0x4 36 #define SPRD_EIC_ASYNC_INTMSK 0x8 37 #define SPRD_EIC_ASYNC_INTCLR 0xc 38 #define SPRD_EIC_ASYNC_INTMODE 0x10 39 #define SPRD_EIC_ASYNC_INTBOTH 0x14 40 #define SPRD_EIC_ASYNC_INTPOL 0x18 41 #define SPRD_EIC_ASYNC_DATA 0x1c 42 43 #define SPRD_EIC_SYNC_INTIE 0x0 44 #define SPRD_EIC_SYNC_INTRAW 0x4 45 #define SPRD_EIC_SYNC_INTMSK 0x8 46 #define SPRD_EIC_SYNC_INTCLR 0xc 47 #define SPRD_EIC_SYNC_INTMODE 0x10 48 #define SPRD_EIC_SYNC_INTBOTH 0x14 49 #define SPRD_EIC_SYNC_INTPOL 0x18 50 #define SPRD_EIC_SYNC_DATA 0x1c 51 52 /* 53 * The digital-chip EIC controller can support maximum 3 banks, and each bank 54 * contains 8 EICs. 55 */ 56 #define SPRD_EIC_MAX_BANK 3 57 #define SPRD_EIC_PER_BANK_NR 8 58 #define SPRD_EIC_DATA_MASK GENMASK(7, 0) 59 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1)) 60 #define SPRD_EIC_DBNC_MASK GENMASK(11, 0) 61 62 /* 63 * The Spreadtrum EIC (external interrupt controller) can be used only in 64 * input mode to generate interrupts if detecting input signals. 65 * 66 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules: 67 * debounce EIC, latch EIC, async EIC and sync EIC, 68 * 69 * The debounce EIC is used to capture the input signals' stable status 70 * (millisecond resolution) and a single-trigger mechanism is introduced 71 * into this sub-module to enhance the input event detection reliability. 72 * The debounce range is from 1ms to 4s with a step size of 1ms. 73 * 74 * The latch EIC is used to latch some special power down signals and 75 * generate interrupts, since the latch EIC does not depend on the APB clock 76 * to capture signals. 77 * 78 * The async EIC uses a 32k clock to capture the short signals (microsecond 79 * resolution) to generate interrupts by level or edge trigger. 80 * 81 * The EIC-sync is similar with GPIO's input function, which is a synchronized 82 * signal input register. 83 */ 84 enum sprd_eic_type { 85 SPRD_EIC_DEBOUNCE, 86 SPRD_EIC_LATCH, 87 SPRD_EIC_ASYNC, 88 SPRD_EIC_SYNC, 89 SPRD_EIC_MAX, 90 }; 91 92 struct sprd_eic { 93 struct gpio_chip chip; 94 void __iomem *base[SPRD_EIC_MAX_BANK]; 95 enum sprd_eic_type type; 96 spinlock_t lock; 97 int irq; 98 }; 99 100 struct sprd_eic_variant_data { 101 enum sprd_eic_type type; 102 u32 num_eics; 103 }; 104 105 static const char *sprd_eic_label_name[SPRD_EIC_MAX] = { 106 "eic-debounce", "eic-latch", "eic-async", 107 "eic-sync", 108 }; 109 110 static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = { 111 .type = SPRD_EIC_DEBOUNCE, 112 .num_eics = 8, 113 }; 114 115 static const struct sprd_eic_variant_data sc9860_eic_latch_data = { 116 .type = SPRD_EIC_LATCH, 117 .num_eics = 8, 118 }; 119 120 static const struct sprd_eic_variant_data sc9860_eic_async_data = { 121 .type = SPRD_EIC_ASYNC, 122 .num_eics = 8, 123 }; 124 125 static const struct sprd_eic_variant_data sc9860_eic_sync_data = { 126 .type = SPRD_EIC_SYNC, 127 .num_eics = 8, 128 }; 129 130 static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic, 131 unsigned int bank) 132 { 133 if (bank >= SPRD_EIC_MAX_BANK) 134 return NULL; 135 136 return sprd_eic->base[bank]; 137 } 138 139 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset, 140 u16 reg, unsigned int val) 141 { 142 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 143 void __iomem *base = 144 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 145 unsigned long flags; 146 u32 tmp; 147 148 spin_lock_irqsave(&sprd_eic->lock, flags); 149 tmp = readl_relaxed(base + reg); 150 151 if (val) 152 tmp |= BIT(SPRD_EIC_BIT(offset)); 153 else 154 tmp &= ~BIT(SPRD_EIC_BIT(offset)); 155 156 writel_relaxed(tmp, base + reg); 157 spin_unlock_irqrestore(&sprd_eic->lock, flags); 158 } 159 160 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg) 161 { 162 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 163 void __iomem *base = 164 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 165 166 return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset))); 167 } 168 169 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset) 170 { 171 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1); 172 return 0; 173 } 174 175 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset) 176 { 177 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0); 178 } 179 180 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset) 181 { 182 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 183 184 switch (sprd_eic->type) { 185 case SPRD_EIC_DEBOUNCE: 186 return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA); 187 case SPRD_EIC_ASYNC: 188 return sprd_eic_read(chip, offset, SPRD_EIC_ASYNC_DATA); 189 case SPRD_EIC_SYNC: 190 return sprd_eic_read(chip, offset, SPRD_EIC_SYNC_DATA); 191 default: 192 return -ENOTSUPP; 193 } 194 } 195 196 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset) 197 { 198 /* EICs are always input, nothing need to do here. */ 199 return 0; 200 } 201 202 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value) 203 { 204 /* EICs are always input, nothing need to do here. */ 205 } 206 207 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset, 208 unsigned int debounce) 209 { 210 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 211 void __iomem *base = 212 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR); 213 u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4; 214 u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK; 215 216 value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK; 217 writel_relaxed(value, base + reg); 218 219 return 0; 220 } 221 222 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset, 223 unsigned long config) 224 { 225 unsigned long param = pinconf_to_config_param(config); 226 u32 arg = pinconf_to_config_argument(config); 227 228 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 229 return sprd_eic_set_debounce(chip, offset, arg); 230 231 return -ENOTSUPP; 232 } 233 234 static void sprd_eic_irq_mask(struct irq_data *data) 235 { 236 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 237 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 238 u32 offset = irqd_to_hwirq(data); 239 240 switch (sprd_eic->type) { 241 case SPRD_EIC_DEBOUNCE: 242 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0); 243 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0); 244 break; 245 case SPRD_EIC_LATCH: 246 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0); 247 break; 248 case SPRD_EIC_ASYNC: 249 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0); 250 break; 251 case SPRD_EIC_SYNC: 252 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0); 253 break; 254 default: 255 dev_err(chip->parent, "Unsupported EIC type.\n"); 256 } 257 258 gpiochip_disable_irq(chip, offset); 259 } 260 261 static void sprd_eic_irq_unmask(struct irq_data *data) 262 { 263 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 264 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 265 u32 offset = irqd_to_hwirq(data); 266 267 gpiochip_enable_irq(chip, offset); 268 269 switch (sprd_eic->type) { 270 case SPRD_EIC_DEBOUNCE: 271 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1); 272 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1); 273 break; 274 case SPRD_EIC_LATCH: 275 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1); 276 break; 277 case SPRD_EIC_ASYNC: 278 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1); 279 break; 280 case SPRD_EIC_SYNC: 281 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1); 282 break; 283 default: 284 dev_err(chip->parent, "Unsupported EIC type.\n"); 285 } 286 } 287 288 static void sprd_eic_irq_ack(struct irq_data *data) 289 { 290 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 291 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 292 u32 offset = irqd_to_hwirq(data); 293 294 switch (sprd_eic->type) { 295 case SPRD_EIC_DEBOUNCE: 296 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1); 297 break; 298 case SPRD_EIC_LATCH: 299 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1); 300 break; 301 case SPRD_EIC_ASYNC: 302 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1); 303 break; 304 case SPRD_EIC_SYNC: 305 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1); 306 break; 307 default: 308 dev_err(chip->parent, "Unsupported EIC type.\n"); 309 } 310 } 311 312 static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type) 313 { 314 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 315 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 316 u32 offset = irqd_to_hwirq(data); 317 int state; 318 319 switch (sprd_eic->type) { 320 case SPRD_EIC_DEBOUNCE: 321 switch (flow_type) { 322 case IRQ_TYPE_LEVEL_HIGH: 323 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); 324 break; 325 case IRQ_TYPE_LEVEL_LOW: 326 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); 327 break; 328 case IRQ_TYPE_EDGE_RISING: 329 case IRQ_TYPE_EDGE_FALLING: 330 case IRQ_TYPE_EDGE_BOTH: 331 state = sprd_eic_get(chip, offset); 332 if (state) 333 sprd_eic_update(chip, offset, 334 SPRD_EIC_DBNC_IEV, 0); 335 else 336 sprd_eic_update(chip, offset, 337 SPRD_EIC_DBNC_IEV, 1); 338 break; 339 default: 340 return -ENOTSUPP; 341 } 342 343 irq_set_handler_locked(data, handle_level_irq); 344 break; 345 case SPRD_EIC_LATCH: 346 switch (flow_type) { 347 case IRQ_TYPE_LEVEL_HIGH: 348 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); 349 break; 350 case IRQ_TYPE_LEVEL_LOW: 351 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); 352 break; 353 case IRQ_TYPE_EDGE_RISING: 354 case IRQ_TYPE_EDGE_FALLING: 355 case IRQ_TYPE_EDGE_BOTH: 356 state = sprd_eic_get(chip, offset); 357 if (state) 358 sprd_eic_update(chip, offset, 359 SPRD_EIC_LATCH_INTPOL, 0); 360 else 361 sprd_eic_update(chip, offset, 362 SPRD_EIC_LATCH_INTPOL, 1); 363 break; 364 default: 365 return -ENOTSUPP; 366 } 367 368 irq_set_handler_locked(data, handle_level_irq); 369 break; 370 case SPRD_EIC_ASYNC: 371 switch (flow_type) { 372 case IRQ_TYPE_EDGE_RISING: 373 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 374 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 375 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); 376 irq_set_handler_locked(data, handle_edge_irq); 377 break; 378 case IRQ_TYPE_EDGE_FALLING: 379 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 380 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 381 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); 382 irq_set_handler_locked(data, handle_edge_irq); 383 break; 384 case IRQ_TYPE_EDGE_BOTH: 385 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0); 386 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1); 387 irq_set_handler_locked(data, handle_edge_irq); 388 break; 389 case IRQ_TYPE_LEVEL_HIGH: 390 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 391 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); 392 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1); 393 irq_set_handler_locked(data, handle_level_irq); 394 break; 395 case IRQ_TYPE_LEVEL_LOW: 396 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0); 397 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1); 398 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0); 399 irq_set_handler_locked(data, handle_level_irq); 400 break; 401 default: 402 return -ENOTSUPP; 403 } 404 break; 405 case SPRD_EIC_SYNC: 406 switch (flow_type) { 407 case IRQ_TYPE_EDGE_RISING: 408 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 409 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 410 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); 411 irq_set_handler_locked(data, handle_edge_irq); 412 break; 413 case IRQ_TYPE_EDGE_FALLING: 414 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 415 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 416 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); 417 irq_set_handler_locked(data, handle_edge_irq); 418 break; 419 case IRQ_TYPE_EDGE_BOTH: 420 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0); 421 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1); 422 irq_set_handler_locked(data, handle_edge_irq); 423 break; 424 case IRQ_TYPE_LEVEL_HIGH: 425 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 426 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); 427 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1); 428 irq_set_handler_locked(data, handle_level_irq); 429 break; 430 case IRQ_TYPE_LEVEL_LOW: 431 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0); 432 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1); 433 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0); 434 irq_set_handler_locked(data, handle_level_irq); 435 break; 436 default: 437 return -ENOTSUPP; 438 } 439 break; 440 default: 441 dev_err(chip->parent, "Unsupported EIC type.\n"); 442 return -ENOTSUPP; 443 } 444 445 return 0; 446 } 447 448 static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq, 449 unsigned int offset) 450 { 451 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 452 struct irq_data *data = irq_get_irq_data(irq); 453 u32 trigger = irqd_get_trigger_type(data); 454 int state, post_state; 455 456 /* 457 * The debounce EIC and latch EIC can only support level trigger, so we 458 * can toggle the level trigger to emulate the edge trigger. 459 */ 460 if ((sprd_eic->type != SPRD_EIC_DEBOUNCE && 461 sprd_eic->type != SPRD_EIC_LATCH) || 462 !(trigger & IRQ_TYPE_EDGE_BOTH)) 463 return; 464 465 sprd_eic_irq_mask(data); 466 state = sprd_eic_get(chip, offset); 467 468 retry: 469 switch (sprd_eic->type) { 470 case SPRD_EIC_DEBOUNCE: 471 if (state) 472 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0); 473 else 474 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1); 475 break; 476 case SPRD_EIC_LATCH: 477 if (state) 478 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0); 479 else 480 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1); 481 break; 482 default: 483 sprd_eic_irq_unmask(data); 484 return; 485 } 486 487 post_state = sprd_eic_get(chip, offset); 488 if (state != post_state) { 489 dev_warn(chip->parent, "EIC level was changed.\n"); 490 state = post_state; 491 goto retry; 492 } 493 494 sprd_eic_irq_unmask(data); 495 } 496 497 static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data) 498 { 499 enum sprd_eic_type type = *(enum sprd_eic_type *)data; 500 501 return !strcmp(chip->label, sprd_eic_label_name[type]); 502 } 503 504 static void sprd_eic_handle_one_type(struct gpio_chip *chip) 505 { 506 struct sprd_eic *sprd_eic = gpiochip_get_data(chip); 507 u32 bank, n, girq; 508 509 for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) { 510 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank); 511 unsigned long reg; 512 513 switch (sprd_eic->type) { 514 case SPRD_EIC_DEBOUNCE: 515 reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) & 516 SPRD_EIC_DATA_MASK; 517 break; 518 case SPRD_EIC_LATCH: 519 reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) & 520 SPRD_EIC_DATA_MASK; 521 break; 522 case SPRD_EIC_ASYNC: 523 reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) & 524 SPRD_EIC_DATA_MASK; 525 break; 526 case SPRD_EIC_SYNC: 527 reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) & 528 SPRD_EIC_DATA_MASK; 529 break; 530 default: 531 dev_err(chip->parent, "Unsupported EIC type.\n"); 532 return; 533 } 534 535 for_each_set_bit(n, ®, SPRD_EIC_PER_BANK_NR) { 536 u32 offset = bank * SPRD_EIC_PER_BANK_NR + n; 537 538 girq = irq_find_mapping(chip->irq.domain, offset); 539 540 generic_handle_irq(girq); 541 sprd_eic_toggle_trigger(chip, girq, offset); 542 } 543 } 544 } 545 546 static void sprd_eic_irq_handler(struct irq_desc *desc) 547 { 548 struct irq_chip *ic = irq_desc_get_chip(desc); 549 struct gpio_chip *chip; 550 enum sprd_eic_type type; 551 552 chained_irq_enter(ic, desc); 553 554 /* 555 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async 556 * and sync) share one same interrupt line, we should iterate each 557 * EIC module to check if there are EIC interrupts were triggered. 558 */ 559 for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) { 560 chip = gpiochip_find(&type, sprd_eic_match_chip_by_type); 561 if (!chip) 562 continue; 563 564 sprd_eic_handle_one_type(chip); 565 } 566 567 chained_irq_exit(ic, desc); 568 } 569 570 static const struct irq_chip sprd_eic_irq = { 571 .name = "sprd-eic", 572 .irq_ack = sprd_eic_irq_ack, 573 .irq_mask = sprd_eic_irq_mask, 574 .irq_unmask = sprd_eic_irq_unmask, 575 .irq_set_type = sprd_eic_irq_set_type, 576 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 577 GPIOCHIP_IRQ_RESOURCE_HELPERS, 578 }; 579 static int sprd_eic_probe(struct platform_device *pdev) 580 { 581 const struct sprd_eic_variant_data *pdata; 582 struct gpio_irq_chip *irq; 583 struct sprd_eic *sprd_eic; 584 struct resource *res; 585 int ret, i; 586 587 pdata = of_device_get_match_data(&pdev->dev); 588 if (!pdata) { 589 dev_err(&pdev->dev, "No matching driver data found.\n"); 590 return -EINVAL; 591 } 592 593 sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL); 594 if (!sprd_eic) 595 return -ENOMEM; 596 597 spin_lock_init(&sprd_eic->lock); 598 sprd_eic->type = pdata->type; 599 600 sprd_eic->irq = platform_get_irq(pdev, 0); 601 if (sprd_eic->irq < 0) 602 return sprd_eic->irq; 603 604 for (i = 0; i < SPRD_EIC_MAX_BANK; i++) { 605 /* 606 * We can have maximum 3 banks EICs, and each EIC has 607 * its own base address. But some platform maybe only 608 * have one bank EIC, thus base[1] and base[2] can be 609 * optional. 610 */ 611 res = platform_get_resource(pdev, IORESOURCE_MEM, i); 612 if (!res) 613 break; 614 615 sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res); 616 if (IS_ERR(sprd_eic->base[i])) 617 return PTR_ERR(sprd_eic->base[i]); 618 } 619 620 sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type]; 621 sprd_eic->chip.ngpio = pdata->num_eics; 622 sprd_eic->chip.base = -1; 623 sprd_eic->chip.parent = &pdev->dev; 624 sprd_eic->chip.direction_input = sprd_eic_direction_input; 625 switch (sprd_eic->type) { 626 case SPRD_EIC_DEBOUNCE: 627 sprd_eic->chip.request = sprd_eic_request; 628 sprd_eic->chip.free = sprd_eic_free; 629 sprd_eic->chip.set_config = sprd_eic_set_config; 630 sprd_eic->chip.set = sprd_eic_set; 631 fallthrough; 632 case SPRD_EIC_ASYNC: 633 case SPRD_EIC_SYNC: 634 sprd_eic->chip.get = sprd_eic_get; 635 break; 636 case SPRD_EIC_LATCH: 637 default: 638 break; 639 } 640 641 irq = &sprd_eic->chip.irq; 642 gpio_irq_chip_set_chip(irq, &sprd_eic_irq); 643 irq->handler = handle_bad_irq; 644 irq->default_type = IRQ_TYPE_NONE; 645 irq->parent_handler = sprd_eic_irq_handler; 646 irq->parent_handler_data = sprd_eic; 647 irq->num_parents = 1; 648 irq->parents = &sprd_eic->irq; 649 650 ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic); 651 if (ret < 0) { 652 dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret); 653 return ret; 654 } 655 656 platform_set_drvdata(pdev, sprd_eic); 657 return 0; 658 } 659 660 static const struct of_device_id sprd_eic_of_match[] = { 661 { 662 .compatible = "sprd,sc9860-eic-debounce", 663 .data = &sc9860_eic_dbnc_data, 664 }, 665 { 666 .compatible = "sprd,sc9860-eic-latch", 667 .data = &sc9860_eic_latch_data, 668 }, 669 { 670 .compatible = "sprd,sc9860-eic-async", 671 .data = &sc9860_eic_async_data, 672 }, 673 { 674 .compatible = "sprd,sc9860-eic-sync", 675 .data = &sc9860_eic_sync_data, 676 }, 677 { 678 /* end of list */ 679 } 680 }; 681 MODULE_DEVICE_TABLE(of, sprd_eic_of_match); 682 683 static struct platform_driver sprd_eic_driver = { 684 .probe = sprd_eic_probe, 685 .driver = { 686 .name = "sprd-eic", 687 .of_match_table = sprd_eic_of_match, 688 }, 689 }; 690 691 module_platform_driver(sprd_eic_driver); 692 693 MODULE_DESCRIPTION("Spreadtrum EIC driver"); 694 MODULE_LICENSE("GPL v2"); 695