xref: /openbmc/linux/drivers/gpio/gpio-eic-sprd.c (revision 62ea22c4) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2018 Spreadtrum Communications Inc.
4  * Copyright (C) 2018 Linaro Ltd.
5  */
6 
7 #include <linux/bitops.h>
8 #include <linux/gpio/driver.h>
9 #include <linux/interrupt.h>
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/spinlock.h>
15 
16 /* EIC registers definition */
17 #define SPRD_EIC_DBNC_DATA		0x0
18 #define SPRD_EIC_DBNC_DMSK		0x4
19 #define SPRD_EIC_DBNC_IEV		0x14
20 #define SPRD_EIC_DBNC_IE		0x18
21 #define SPRD_EIC_DBNC_RIS		0x1c
22 #define SPRD_EIC_DBNC_MIS		0x20
23 #define SPRD_EIC_DBNC_IC		0x24
24 #define SPRD_EIC_DBNC_TRIG		0x28
25 #define SPRD_EIC_DBNC_CTRL0		0x40
26 
27 #define SPRD_EIC_LATCH_INTEN		0x0
28 #define SPRD_EIC_LATCH_INTRAW		0x4
29 #define SPRD_EIC_LATCH_INTMSK		0x8
30 #define SPRD_EIC_LATCH_INTCLR		0xc
31 #define SPRD_EIC_LATCH_INTPOL		0x10
32 #define SPRD_EIC_LATCH_INTMODE		0x14
33 
34 #define SPRD_EIC_ASYNC_INTIE		0x0
35 #define SPRD_EIC_ASYNC_INTRAW		0x4
36 #define SPRD_EIC_ASYNC_INTMSK		0x8
37 #define SPRD_EIC_ASYNC_INTCLR		0xc
38 #define SPRD_EIC_ASYNC_INTMODE		0x10
39 #define SPRD_EIC_ASYNC_INTBOTH		0x14
40 #define SPRD_EIC_ASYNC_INTPOL		0x18
41 #define SPRD_EIC_ASYNC_DATA		0x1c
42 
43 #define SPRD_EIC_SYNC_INTIE		0x0
44 #define SPRD_EIC_SYNC_INTRAW		0x4
45 #define SPRD_EIC_SYNC_INTMSK		0x8
46 #define SPRD_EIC_SYNC_INTCLR		0xc
47 #define SPRD_EIC_SYNC_INTMODE		0x10
48 #define SPRD_EIC_SYNC_INTBOTH		0x14
49 #define SPRD_EIC_SYNC_INTPOL		0x18
50 #define SPRD_EIC_SYNC_DATA		0x1c
51 
52 /*
53  * The digital-chip EIC controller can support maximum 3 banks, and each bank
54  * contains 8 EICs.
55  */
56 #define SPRD_EIC_MAX_BANK		3
57 #define SPRD_EIC_PER_BANK_NR		8
58 #define SPRD_EIC_DATA_MASK		GENMASK(7, 0)
59 #define SPRD_EIC_BIT(x)			((x) & (SPRD_EIC_PER_BANK_NR - 1))
60 #define SPRD_EIC_DBNC_MASK		GENMASK(11, 0)
61 
62 /*
63  * The Spreadtrum EIC (external interrupt controller) can be used only in
64  * input mode to generate interrupts if detecting input signals.
65  *
66  * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
67  * debounce EIC, latch EIC, async EIC and sync EIC,
68  *
69  * The debounce EIC is used to capture the input signals' stable status
70  * (millisecond resolution) and a single-trigger mechanism is introduced
71  * into this sub-module to enhance the input event detection reliability.
72  * The debounce range is from 1ms to 4s with a step size of 1ms.
73  *
74  * The latch EIC is used to latch some special power down signals and
75  * generate interrupts, since the latch EIC does not depend on the APB clock
76  * to capture signals.
77  *
78  * The async EIC uses a 32k clock to capture the short signals (microsecond
79  * resolution) to generate interrupts by level or edge trigger.
80  *
81  * The EIC-sync is similar with GPIO's input function, which is a synchronized
82  * signal input register.
83  */
84 enum sprd_eic_type {
85 	SPRD_EIC_DEBOUNCE,
86 	SPRD_EIC_LATCH,
87 	SPRD_EIC_ASYNC,
88 	SPRD_EIC_SYNC,
89 	SPRD_EIC_MAX,
90 };
91 
92 struct sprd_eic {
93 	struct gpio_chip chip;
94 	struct irq_chip intc;
95 	void __iomem *base[SPRD_EIC_MAX_BANK];
96 	enum sprd_eic_type type;
97 	spinlock_t lock;
98 	int irq;
99 };
100 
101 struct sprd_eic_variant_data {
102 	enum sprd_eic_type type;
103 	u32 num_eics;
104 };
105 
106 static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
107 	"eic-debounce", "eic-latch", "eic-async",
108 	"eic-sync",
109 };
110 
111 static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
112 	.type = SPRD_EIC_DEBOUNCE,
113 	.num_eics = 8,
114 };
115 
116 static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
117 	.type = SPRD_EIC_LATCH,
118 	.num_eics = 8,
119 };
120 
121 static const struct sprd_eic_variant_data sc9860_eic_async_data = {
122 	.type = SPRD_EIC_ASYNC,
123 	.num_eics = 8,
124 };
125 
126 static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
127 	.type = SPRD_EIC_SYNC,
128 	.num_eics = 8,
129 };
130 
131 static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
132 						 unsigned int bank)
133 {
134 	if (bank >= SPRD_EIC_MAX_BANK)
135 		return NULL;
136 
137 	return sprd_eic->base[bank];
138 }
139 
140 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
141 			    u16 reg, unsigned int val)
142 {
143 	struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
144 	void __iomem *base =
145 		sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
146 	unsigned long flags;
147 	u32 tmp;
148 
149 	spin_lock_irqsave(&sprd_eic->lock, flags);
150 	tmp = readl_relaxed(base + reg);
151 
152 	if (val)
153 		tmp |= BIT(SPRD_EIC_BIT(offset));
154 	else
155 		tmp &= ~BIT(SPRD_EIC_BIT(offset));
156 
157 	writel_relaxed(tmp, base + reg);
158 	spin_unlock_irqrestore(&sprd_eic->lock, flags);
159 }
160 
161 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
162 {
163 	struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
164 	void __iomem *base =
165 		sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
166 
167 	return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
168 }
169 
170 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
171 {
172 	sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
173 	return 0;
174 }
175 
176 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
177 {
178 	sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
179 }
180 
181 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
182 {
183 	return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
184 }
185 
186 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
187 {
188 	/* EICs are always input, nothing need to do here. */
189 	return 0;
190 }
191 
192 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
193 {
194 	/* EICs are always input, nothing need to do here. */
195 }
196 
197 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
198 				 unsigned int debounce)
199 {
200 	struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
201 	void __iomem *base =
202 		sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
203 	u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
204 	u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
205 
206 	value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
207 	writel_relaxed(value, base + reg);
208 
209 	return 0;
210 }
211 
212 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
213 			       unsigned long config)
214 {
215 	unsigned long param = pinconf_to_config_param(config);
216 	u32 arg = pinconf_to_config_argument(config);
217 
218 	if (param == PIN_CONFIG_INPUT_DEBOUNCE)
219 		return sprd_eic_set_debounce(chip, offset, arg);
220 
221 	return -ENOTSUPP;
222 }
223 
224 static void sprd_eic_irq_mask(struct irq_data *data)
225 {
226 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
227 	struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
228 	u32 offset = irqd_to_hwirq(data);
229 
230 	switch (sprd_eic->type) {
231 	case SPRD_EIC_DEBOUNCE:
232 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
233 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
234 		break;
235 	case SPRD_EIC_LATCH:
236 		sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
237 		break;
238 	case SPRD_EIC_ASYNC:
239 		sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
240 		break;
241 	case SPRD_EIC_SYNC:
242 		sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
243 		break;
244 	default:
245 		dev_err(chip->parent, "Unsupported EIC type.\n");
246 	}
247 }
248 
249 static void sprd_eic_irq_unmask(struct irq_data *data)
250 {
251 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
252 	struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
253 	u32 offset = irqd_to_hwirq(data);
254 
255 	switch (sprd_eic->type) {
256 	case SPRD_EIC_DEBOUNCE:
257 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
258 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
259 		break;
260 	case SPRD_EIC_LATCH:
261 		sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
262 		break;
263 	case SPRD_EIC_ASYNC:
264 		sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
265 		break;
266 	case SPRD_EIC_SYNC:
267 		sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
268 		break;
269 	default:
270 		dev_err(chip->parent, "Unsupported EIC type.\n");
271 	}
272 }
273 
274 static void sprd_eic_irq_ack(struct irq_data *data)
275 {
276 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
277 	struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
278 	u32 offset = irqd_to_hwirq(data);
279 
280 	switch (sprd_eic->type) {
281 	case SPRD_EIC_DEBOUNCE:
282 		sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
283 		break;
284 	case SPRD_EIC_LATCH:
285 		sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
286 		break;
287 	case SPRD_EIC_ASYNC:
288 		sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
289 		break;
290 	case SPRD_EIC_SYNC:
291 		sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
292 		break;
293 	default:
294 		dev_err(chip->parent, "Unsupported EIC type.\n");
295 	}
296 }
297 
298 static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
299 {
300 	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
301 	struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
302 	u32 offset = irqd_to_hwirq(data);
303 
304 	switch (sprd_eic->type) {
305 	case SPRD_EIC_DEBOUNCE:
306 		switch (flow_type) {
307 		case IRQ_TYPE_LEVEL_HIGH:
308 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
309 			break;
310 		case IRQ_TYPE_LEVEL_LOW:
311 			sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
312 			break;
313 		default:
314 			return -ENOTSUPP;
315 		}
316 
317 		irq_set_handler_locked(data, handle_level_irq);
318 		break;
319 	case SPRD_EIC_LATCH:
320 		switch (flow_type) {
321 		case IRQ_TYPE_LEVEL_HIGH:
322 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
323 			break;
324 		case IRQ_TYPE_LEVEL_LOW:
325 			sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
326 			break;
327 		default:
328 			return -ENOTSUPP;
329 		}
330 
331 		irq_set_handler_locked(data, handle_level_irq);
332 		break;
333 	case SPRD_EIC_ASYNC:
334 		switch (flow_type) {
335 		case IRQ_TYPE_EDGE_RISING:
336 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
337 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
338 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
339 			irq_set_handler_locked(data, handle_edge_irq);
340 			break;
341 		case IRQ_TYPE_EDGE_FALLING:
342 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
343 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
344 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
345 			irq_set_handler_locked(data, handle_edge_irq);
346 			break;
347 		case IRQ_TYPE_EDGE_BOTH:
348 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
349 			irq_set_handler_locked(data, handle_edge_irq);
350 			break;
351 		case IRQ_TYPE_LEVEL_HIGH:
352 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
353 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
354 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
355 			irq_set_handler_locked(data, handle_level_irq);
356 			break;
357 		case IRQ_TYPE_LEVEL_LOW:
358 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
359 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
360 			sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
361 			irq_set_handler_locked(data, handle_level_irq);
362 			break;
363 		default:
364 			return -ENOTSUPP;
365 		}
366 		break;
367 	case SPRD_EIC_SYNC:
368 		switch (flow_type) {
369 		case IRQ_TYPE_EDGE_RISING:
370 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
371 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
372 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
373 			irq_set_handler_locked(data, handle_edge_irq);
374 			break;
375 		case IRQ_TYPE_EDGE_FALLING:
376 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
377 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
378 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
379 			irq_set_handler_locked(data, handle_edge_irq);
380 			break;
381 		case IRQ_TYPE_EDGE_BOTH:
382 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
383 			irq_set_handler_locked(data, handle_edge_irq);
384 			break;
385 		case IRQ_TYPE_LEVEL_HIGH:
386 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
387 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
388 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
389 			irq_set_handler_locked(data, handle_level_irq);
390 			break;
391 		case IRQ_TYPE_LEVEL_LOW:
392 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
393 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
394 			sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
395 			irq_set_handler_locked(data, handle_level_irq);
396 			break;
397 		default:
398 			return -ENOTSUPP;
399 		}
400 	default:
401 		dev_err(chip->parent, "Unsupported EIC type.\n");
402 		return -ENOTSUPP;
403 	}
404 
405 	return 0;
406 }
407 
408 static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data)
409 {
410 	enum sprd_eic_type type = *(enum sprd_eic_type *)data;
411 
412 	return !strcmp(chip->label, sprd_eic_label_name[type]);
413 }
414 
415 static void sprd_eic_handle_one_type(struct gpio_chip *chip)
416 {
417 	struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
418 	u32 bank, n, girq;
419 
420 	for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
421 		void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
422 		unsigned long reg;
423 
424 		switch (sprd_eic->type) {
425 		case SPRD_EIC_DEBOUNCE:
426 			reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
427 				SPRD_EIC_DATA_MASK;
428 			break;
429 		case SPRD_EIC_LATCH:
430 			reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
431 				SPRD_EIC_DATA_MASK;
432 			break;
433 		case SPRD_EIC_ASYNC:
434 			reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
435 				SPRD_EIC_DATA_MASK;
436 			break;
437 		case SPRD_EIC_SYNC:
438 			reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
439 				SPRD_EIC_DATA_MASK;
440 			break;
441 		default:
442 			dev_err(chip->parent, "Unsupported EIC type.\n");
443 			return;
444 		}
445 
446 		for_each_set_bit(n, &reg, SPRD_EIC_PER_BANK_NR) {
447 			girq = irq_find_mapping(chip->irq.domain,
448 					bank * SPRD_EIC_PER_BANK_NR + n);
449 
450 			generic_handle_irq(girq);
451 		}
452 	}
453 }
454 
455 static void sprd_eic_irq_handler(struct irq_desc *desc)
456 {
457 	struct irq_chip *ic = irq_desc_get_chip(desc);
458 	struct gpio_chip *chip;
459 	enum sprd_eic_type type;
460 
461 	chained_irq_enter(ic, desc);
462 
463 	/*
464 	 * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
465 	 * and sync) share one same interrupt line, we should iterate each
466 	 * EIC module to check if there are EIC interrupts were triggered.
467 	 */
468 	for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) {
469 		chip = gpiochip_find(&type, sprd_eic_match_chip_by_type);
470 		if (!chip)
471 			continue;
472 
473 		sprd_eic_handle_one_type(chip);
474 	}
475 
476 	chained_irq_exit(ic, desc);
477 }
478 
479 static int sprd_eic_probe(struct platform_device *pdev)
480 {
481 	const struct sprd_eic_variant_data *pdata;
482 	struct gpio_irq_chip *irq;
483 	struct sprd_eic *sprd_eic;
484 	struct resource *res;
485 	int ret, i;
486 
487 	pdata = of_device_get_match_data(&pdev->dev);
488 	if (!pdata) {
489 		dev_err(&pdev->dev, "No matching driver data found.\n");
490 		return -EINVAL;
491 	}
492 
493 	sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL);
494 	if (!sprd_eic)
495 		return -ENOMEM;
496 
497 	spin_lock_init(&sprd_eic->lock);
498 	sprd_eic->type = pdata->type;
499 
500 	sprd_eic->irq = platform_get_irq(pdev, 0);
501 	if (sprd_eic->irq < 0) {
502 		dev_err(&pdev->dev, "Failed to get EIC interrupt.\n");
503 		return sprd_eic->irq;
504 	}
505 
506 	for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
507 		/*
508 		 * We can have maximum 3 banks EICs, and each EIC has
509 		 * its own base address. But some platform maybe only
510 		 * have one bank EIC, thus base[1] and base[2] can be
511 		 * optional.
512 		 */
513 		res = platform_get_resource(pdev, IORESOURCE_MEM, i);
514 		if (!res)
515 			continue;
516 
517 		sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res);
518 		if (IS_ERR(sprd_eic->base[i]))
519 			return PTR_ERR(sprd_eic->base[i]);
520 	}
521 
522 	sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
523 	sprd_eic->chip.ngpio = pdata->num_eics;
524 	sprd_eic->chip.base = -1;
525 	sprd_eic->chip.parent = &pdev->dev;
526 	sprd_eic->chip.of_node = pdev->dev.of_node;
527 	sprd_eic->chip.direction_input = sprd_eic_direction_input;
528 	switch (sprd_eic->type) {
529 	case SPRD_EIC_DEBOUNCE:
530 		sprd_eic->chip.request = sprd_eic_request;
531 		sprd_eic->chip.free = sprd_eic_free;
532 		sprd_eic->chip.set_config = sprd_eic_set_config;
533 		sprd_eic->chip.set = sprd_eic_set;
534 		/* fall-through */
535 	case SPRD_EIC_ASYNC:
536 		/* fall-through */
537 	case SPRD_EIC_SYNC:
538 		sprd_eic->chip.get = sprd_eic_get;
539 		break;
540 	case SPRD_EIC_LATCH:
541 		/* fall-through */
542 	default:
543 		break;
544 	}
545 
546 	sprd_eic->intc.name = dev_name(&pdev->dev);
547 	sprd_eic->intc.irq_ack = sprd_eic_irq_ack;
548 	sprd_eic->intc.irq_mask = sprd_eic_irq_mask;
549 	sprd_eic->intc.irq_unmask = sprd_eic_irq_unmask;
550 	sprd_eic->intc.irq_set_type = sprd_eic_irq_set_type;
551 	sprd_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
552 
553 	irq = &sprd_eic->chip.irq;
554 	irq->chip = &sprd_eic->intc;
555 	irq->handler = handle_bad_irq;
556 	irq->default_type = IRQ_TYPE_NONE;
557 	irq->parent_handler = sprd_eic_irq_handler;
558 	irq->parent_handler_data = sprd_eic;
559 	irq->num_parents = 1;
560 	irq->parents = &sprd_eic->irq;
561 
562 	ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic);
563 	if (ret < 0) {
564 		dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
565 		return ret;
566 	}
567 
568 	platform_set_drvdata(pdev, sprd_eic);
569 	return 0;
570 }
571 
572 static const struct of_device_id sprd_eic_of_match[] = {
573 	{
574 		.compatible = "sprd,sc9860-eic-debounce",
575 		.data = &sc9860_eic_dbnc_data,
576 	},
577 	{
578 		.compatible = "sprd,sc9860-eic-latch",
579 		.data = &sc9860_eic_latch_data,
580 	},
581 	{
582 		.compatible = "sprd,sc9860-eic-async",
583 		.data = &sc9860_eic_async_data,
584 	},
585 	{
586 		.compatible = "sprd,sc9860-eic-sync",
587 		.data = &sc9860_eic_sync_data,
588 	},
589 	{
590 		/* end of list */
591 	}
592 };
593 MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
594 
595 static struct platform_driver sprd_eic_driver = {
596 	.probe = sprd_eic_probe,
597 	.driver = {
598 		.name = "sprd-eic",
599 		.of_match_table	= sprd_eic_of_match,
600 	},
601 };
602 
603 module_platform_driver(sprd_eic_driver);
604 
605 MODULE_DESCRIPTION("Spreadtrum EIC driver");
606 MODULE_LICENSE("GPL v2");
607