1 /* 2 * Copyright (c) 2011 Jamie Iles 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * All enquiries to support@picochip.com 9 */ 10 #include <linux/acpi.h> 11 #include <linux/clk.h> 12 #include <linux/err.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/ioport.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_address.h> 23 #include <linux/of_device.h> 24 #include <linux/of_irq.h> 25 #include <linux/platform_device.h> 26 #include <linux/property.h> 27 #include <linux/reset.h> 28 #include <linux/spinlock.h> 29 #include <linux/platform_data/gpio-dwapb.h> 30 #include <linux/slab.h> 31 32 #include "gpiolib.h" 33 34 #define GPIO_SWPORTA_DR 0x00 35 #define GPIO_SWPORTA_DDR 0x04 36 #define GPIO_SWPORTB_DR 0x0c 37 #define GPIO_SWPORTB_DDR 0x10 38 #define GPIO_SWPORTC_DR 0x18 39 #define GPIO_SWPORTC_DDR 0x1c 40 #define GPIO_SWPORTD_DR 0x24 41 #define GPIO_SWPORTD_DDR 0x28 42 #define GPIO_INTEN 0x30 43 #define GPIO_INTMASK 0x34 44 #define GPIO_INTTYPE_LEVEL 0x38 45 #define GPIO_INT_POLARITY 0x3c 46 #define GPIO_INTSTATUS 0x40 47 #define GPIO_PORTA_DEBOUNCE 0x48 48 #define GPIO_PORTA_EOI 0x4c 49 #define GPIO_EXT_PORTA 0x50 50 #define GPIO_EXT_PORTB 0x54 51 #define GPIO_EXT_PORTC 0x58 52 #define GPIO_EXT_PORTD 0x5c 53 54 #define DWAPB_MAX_PORTS 4 55 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */ 56 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */ 57 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */ 58 59 #define GPIO_REG_OFFSET_V2 1 60 61 #define GPIO_INTMASK_V2 0x44 62 #define GPIO_INTTYPE_LEVEL_V2 0x34 63 #define GPIO_INT_POLARITY_V2 0x38 64 #define GPIO_INTSTATUS_V2 0x3c 65 #define GPIO_PORTA_EOI_V2 0x40 66 67 struct dwapb_gpio; 68 69 #ifdef CONFIG_PM_SLEEP 70 /* Store GPIO context across system-wide suspend/resume transitions */ 71 struct dwapb_context { 72 u32 data; 73 u32 dir; 74 u32 ext; 75 u32 int_en; 76 u32 int_mask; 77 u32 int_type; 78 u32 int_pol; 79 u32 int_deb; 80 u32 wake_en; 81 }; 82 #endif 83 84 struct dwapb_gpio_port { 85 struct gpio_chip gc; 86 bool is_registered; 87 struct dwapb_gpio *gpio; 88 #ifdef CONFIG_PM_SLEEP 89 struct dwapb_context *ctx; 90 #endif 91 unsigned int idx; 92 }; 93 94 struct dwapb_gpio { 95 struct device *dev; 96 void __iomem *regs; 97 struct dwapb_gpio_port *ports; 98 unsigned int nr_ports; 99 struct irq_domain *domain; 100 unsigned int flags; 101 struct reset_control *rst; 102 struct clk *clk; 103 }; 104 105 static inline u32 gpio_reg_v2_convert(unsigned int offset) 106 { 107 switch (offset) { 108 case GPIO_INTMASK: 109 return GPIO_INTMASK_V2; 110 case GPIO_INTTYPE_LEVEL: 111 return GPIO_INTTYPE_LEVEL_V2; 112 case GPIO_INT_POLARITY: 113 return GPIO_INT_POLARITY_V2; 114 case GPIO_INTSTATUS: 115 return GPIO_INTSTATUS_V2; 116 case GPIO_PORTA_EOI: 117 return GPIO_PORTA_EOI_V2; 118 } 119 120 return offset; 121 } 122 123 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) 124 { 125 if (gpio->flags & GPIO_REG_OFFSET_V2) 126 return gpio_reg_v2_convert(offset); 127 128 return offset; 129 } 130 131 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) 132 { 133 struct gpio_chip *gc = &gpio->ports[0].gc; 134 void __iomem *reg_base = gpio->regs; 135 136 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); 137 } 138 139 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, 140 u32 val) 141 { 142 struct gpio_chip *gc = &gpio->ports[0].gc; 143 void __iomem *reg_base = gpio->regs; 144 145 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); 146 } 147 148 static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 149 { 150 struct dwapb_gpio_port *port = gpiochip_get_data(gc); 151 struct dwapb_gpio *gpio = port->gpio; 152 153 return irq_find_mapping(gpio->domain, offset); 154 } 155 156 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) 157 { 158 struct dwapb_gpio_port *port; 159 int i; 160 161 for (i = 0; i < gpio->nr_ports; i++) { 162 port = &gpio->ports[i]; 163 if (port->idx == offs / 32) 164 return port; 165 } 166 167 return NULL; 168 } 169 170 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) 171 { 172 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); 173 struct gpio_chip *gc; 174 u32 pol; 175 int val; 176 177 if (!port) 178 return; 179 gc = &port->gc; 180 181 pol = dwapb_read(gpio, GPIO_INT_POLARITY); 182 /* Just read the current value right out of the data register */ 183 val = gc->get(gc, offs % 32); 184 if (val) 185 pol &= ~BIT(offs); 186 else 187 pol |= BIT(offs); 188 189 dwapb_write(gpio, GPIO_INT_POLARITY, pol); 190 } 191 192 static u32 dwapb_do_irq(struct dwapb_gpio *gpio) 193 { 194 u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); 195 u32 ret = irq_status; 196 197 while (irq_status) { 198 int hwirq = fls(irq_status) - 1; 199 int gpio_irq = irq_find_mapping(gpio->domain, hwirq); 200 201 generic_handle_irq(gpio_irq); 202 irq_status &= ~BIT(hwirq); 203 204 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK) 205 == IRQ_TYPE_EDGE_BOTH) 206 dwapb_toggle_trigger(gpio, hwirq); 207 } 208 209 return ret; 210 } 211 212 static void dwapb_irq_handler(struct irq_desc *desc) 213 { 214 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); 215 struct irq_chip *chip = irq_desc_get_chip(desc); 216 217 dwapb_do_irq(gpio); 218 219 if (chip->irq_eoi) 220 chip->irq_eoi(irq_desc_get_irq_data(desc)); 221 } 222 223 static void dwapb_irq_enable(struct irq_data *d) 224 { 225 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 226 struct dwapb_gpio *gpio = igc->private; 227 struct gpio_chip *gc = &gpio->ports[0].gc; 228 unsigned long flags; 229 u32 val; 230 231 spin_lock_irqsave(&gc->bgpio_lock, flags); 232 val = dwapb_read(gpio, GPIO_INTEN); 233 val |= BIT(d->hwirq); 234 dwapb_write(gpio, GPIO_INTEN, val); 235 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 236 } 237 238 static void dwapb_irq_disable(struct irq_data *d) 239 { 240 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 241 struct dwapb_gpio *gpio = igc->private; 242 struct gpio_chip *gc = &gpio->ports[0].gc; 243 unsigned long flags; 244 u32 val; 245 246 spin_lock_irqsave(&gc->bgpio_lock, flags); 247 val = dwapb_read(gpio, GPIO_INTEN); 248 val &= ~BIT(d->hwirq); 249 dwapb_write(gpio, GPIO_INTEN, val); 250 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 251 } 252 253 static int dwapb_irq_reqres(struct irq_data *d) 254 { 255 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 256 struct dwapb_gpio *gpio = igc->private; 257 struct gpio_chip *gc = &gpio->ports[0].gc; 258 259 if (gpiochip_lock_as_irq(gc, irqd_to_hwirq(d))) { 260 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n", 261 irqd_to_hwirq(d)); 262 return -EINVAL; 263 } 264 return 0; 265 } 266 267 static void dwapb_irq_relres(struct irq_data *d) 268 { 269 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 270 struct dwapb_gpio *gpio = igc->private; 271 struct gpio_chip *gc = &gpio->ports[0].gc; 272 273 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d)); 274 } 275 276 static int dwapb_irq_set_type(struct irq_data *d, u32 type) 277 { 278 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 279 struct dwapb_gpio *gpio = igc->private; 280 struct gpio_chip *gc = &gpio->ports[0].gc; 281 int bit = d->hwirq; 282 unsigned long level, polarity, flags; 283 284 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | 285 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 286 return -EINVAL; 287 288 spin_lock_irqsave(&gc->bgpio_lock, flags); 289 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 290 polarity = dwapb_read(gpio, GPIO_INT_POLARITY); 291 292 switch (type) { 293 case IRQ_TYPE_EDGE_BOTH: 294 level |= BIT(bit); 295 dwapb_toggle_trigger(gpio, bit); 296 break; 297 case IRQ_TYPE_EDGE_RISING: 298 level |= BIT(bit); 299 polarity |= BIT(bit); 300 break; 301 case IRQ_TYPE_EDGE_FALLING: 302 level |= BIT(bit); 303 polarity &= ~BIT(bit); 304 break; 305 case IRQ_TYPE_LEVEL_HIGH: 306 level &= ~BIT(bit); 307 polarity |= BIT(bit); 308 break; 309 case IRQ_TYPE_LEVEL_LOW: 310 level &= ~BIT(bit); 311 polarity &= ~BIT(bit); 312 break; 313 } 314 315 irq_setup_alt_chip(d, type); 316 317 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); 318 if (type != IRQ_TYPE_EDGE_BOTH) 319 dwapb_write(gpio, GPIO_INT_POLARITY, polarity); 320 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 321 322 return 0; 323 } 324 325 #ifdef CONFIG_PM_SLEEP 326 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable) 327 { 328 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 329 struct dwapb_gpio *gpio = igc->private; 330 struct dwapb_context *ctx = gpio->ports[0].ctx; 331 332 if (enable) 333 ctx->wake_en |= BIT(d->hwirq); 334 else 335 ctx->wake_en &= ~BIT(d->hwirq); 336 337 return 0; 338 } 339 #endif 340 341 static int dwapb_gpio_set_debounce(struct gpio_chip *gc, 342 unsigned offset, unsigned debounce) 343 { 344 struct dwapb_gpio_port *port = gpiochip_get_data(gc); 345 struct dwapb_gpio *gpio = port->gpio; 346 unsigned long flags, val_deb; 347 unsigned long mask = BIT(offset); 348 349 spin_lock_irqsave(&gc->bgpio_lock, flags); 350 351 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 352 if (debounce) 353 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask); 354 else 355 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask); 356 357 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 358 359 return 0; 360 } 361 362 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, 363 unsigned long config) 364 { 365 u32 debounce; 366 367 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 368 return -ENOTSUPP; 369 370 debounce = pinconf_to_config_argument(config); 371 return dwapb_gpio_set_debounce(gc, offset, debounce); 372 } 373 374 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) 375 { 376 u32 worked; 377 struct dwapb_gpio *gpio = dev_id; 378 379 worked = dwapb_do_irq(gpio); 380 381 return worked ? IRQ_HANDLED : IRQ_NONE; 382 } 383 384 static void dwapb_configure_irqs(struct dwapb_gpio *gpio, 385 struct dwapb_gpio_port *port, 386 struct dwapb_port_property *pp) 387 { 388 struct gpio_chip *gc = &port->gc; 389 struct fwnode_handle *fwnode = pp->fwnode; 390 struct irq_chip_generic *irq_gc = NULL; 391 unsigned int hwirq, ngpio = gc->ngpio; 392 struct irq_chip_type *ct; 393 int err, i; 394 395 gpio->domain = irq_domain_create_linear(fwnode, ngpio, 396 &irq_generic_chip_ops, gpio); 397 if (!gpio->domain) 398 return; 399 400 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2, 401 "gpio-dwapb", handle_level_irq, 402 IRQ_NOREQUEST, 0, 403 IRQ_GC_INIT_NESTED_LOCK); 404 if (err) { 405 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n"); 406 irq_domain_remove(gpio->domain); 407 gpio->domain = NULL; 408 return; 409 } 410 411 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0); 412 if (!irq_gc) { 413 irq_domain_remove(gpio->domain); 414 gpio->domain = NULL; 415 return; 416 } 417 418 irq_gc->reg_base = gpio->regs; 419 irq_gc->private = gpio; 420 421 for (i = 0; i < 2; i++) { 422 ct = &irq_gc->chip_types[i]; 423 ct->chip.irq_ack = irq_gc_ack_set_bit; 424 ct->chip.irq_mask = irq_gc_mask_set_bit; 425 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 426 ct->chip.irq_set_type = dwapb_irq_set_type; 427 ct->chip.irq_enable = dwapb_irq_enable; 428 ct->chip.irq_disable = dwapb_irq_disable; 429 ct->chip.irq_request_resources = dwapb_irq_reqres; 430 ct->chip.irq_release_resources = dwapb_irq_relres; 431 #ifdef CONFIG_PM_SLEEP 432 ct->chip.irq_set_wake = dwapb_irq_set_wake; 433 #endif 434 ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI); 435 ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK); 436 ct->type = IRQ_TYPE_LEVEL_MASK; 437 } 438 439 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; 440 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; 441 irq_gc->chip_types[1].handler = handle_edge_irq; 442 443 if (!pp->irq_shared) { 444 int i; 445 446 for (i = 0; i < pp->ngpio; i++) { 447 if (pp->irq[i] >= 0) 448 irq_set_chained_handler_and_data(pp->irq[i], 449 dwapb_irq_handler, gpio); 450 } 451 } else { 452 /* 453 * Request a shared IRQ since where MFD would have devices 454 * using the same irq pin 455 */ 456 err = devm_request_irq(gpio->dev, pp->irq[0], 457 dwapb_irq_handler_mfd, 458 IRQF_SHARED, "gpio-dwapb-mfd", gpio); 459 if (err) { 460 dev_err(gpio->dev, "error requesting IRQ\n"); 461 irq_domain_remove(gpio->domain); 462 gpio->domain = NULL; 463 return; 464 } 465 } 466 467 for (hwirq = 0 ; hwirq < ngpio ; hwirq++) 468 irq_create_mapping(gpio->domain, hwirq); 469 470 port->gc.to_irq = dwapb_gpio_to_irq; 471 } 472 473 static void dwapb_irq_teardown(struct dwapb_gpio *gpio) 474 { 475 struct dwapb_gpio_port *port = &gpio->ports[0]; 476 struct gpio_chip *gc = &port->gc; 477 unsigned int ngpio = gc->ngpio; 478 irq_hw_number_t hwirq; 479 480 if (!gpio->domain) 481 return; 482 483 for (hwirq = 0 ; hwirq < ngpio ; hwirq++) 484 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq)); 485 486 irq_domain_remove(gpio->domain); 487 gpio->domain = NULL; 488 } 489 490 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, 491 struct dwapb_port_property *pp, 492 unsigned int offs) 493 { 494 struct dwapb_gpio_port *port; 495 void __iomem *dat, *set, *dirout; 496 int err; 497 498 port = &gpio->ports[offs]; 499 port->gpio = gpio; 500 port->idx = pp->idx; 501 502 #ifdef CONFIG_PM_SLEEP 503 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); 504 if (!port->ctx) 505 return -ENOMEM; 506 #endif 507 508 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_STRIDE); 509 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_STRIDE); 510 dirout = gpio->regs + GPIO_SWPORTA_DDR + 511 (pp->idx * GPIO_SWPORT_DDR_STRIDE); 512 513 /* This registers 32 GPIO lines per port */ 514 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, 515 NULL, 0); 516 if (err) { 517 dev_err(gpio->dev, "failed to init gpio chip for port%d\n", 518 port->idx); 519 return err; 520 } 521 522 #ifdef CONFIG_OF_GPIO 523 port->gc.of_node = to_of_node(pp->fwnode); 524 #endif 525 port->gc.ngpio = pp->ngpio; 526 port->gc.base = pp->gpio_base; 527 528 /* Only port A support debounce */ 529 if (pp->idx == 0) 530 port->gc.set_config = dwapb_gpio_set_config; 531 532 if (pp->has_irq) 533 dwapb_configure_irqs(gpio, port, pp); 534 535 err = gpiochip_add_data(&port->gc, port); 536 if (err) 537 dev_err(gpio->dev, "failed to register gpiochip for port%d\n", 538 port->idx); 539 else 540 port->is_registered = true; 541 542 /* Add GPIO-signaled ACPI event support */ 543 if (pp->has_irq) 544 acpi_gpiochip_request_interrupts(&port->gc); 545 546 return err; 547 } 548 549 static void dwapb_gpio_unregister(struct dwapb_gpio *gpio) 550 { 551 unsigned int m; 552 553 for (m = 0; m < gpio->nr_ports; ++m) 554 if (gpio->ports[m].is_registered) 555 gpiochip_remove(&gpio->ports[m].gc); 556 } 557 558 static struct dwapb_platform_data * 559 dwapb_gpio_get_pdata(struct device *dev) 560 { 561 struct fwnode_handle *fwnode; 562 struct dwapb_platform_data *pdata; 563 struct dwapb_port_property *pp; 564 int nports; 565 int i, j; 566 567 nports = device_get_child_node_count(dev); 568 if (nports == 0) 569 return ERR_PTR(-ENODEV); 570 571 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 572 if (!pdata) 573 return ERR_PTR(-ENOMEM); 574 575 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); 576 if (!pdata->properties) 577 return ERR_PTR(-ENOMEM); 578 579 pdata->nports = nports; 580 581 i = 0; 582 device_for_each_child_node(dev, fwnode) { 583 struct device_node *np = NULL; 584 585 pp = &pdata->properties[i++]; 586 pp->fwnode = fwnode; 587 588 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || 589 pp->idx >= DWAPB_MAX_PORTS) { 590 dev_err(dev, 591 "missing/invalid port index for port%d\n", i); 592 fwnode_handle_put(fwnode); 593 return ERR_PTR(-EINVAL); 594 } 595 596 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios", 597 &pp->ngpio)) { 598 dev_info(dev, 599 "failed to get number of gpios for port%d\n", 600 i); 601 pp->ngpio = 32; 602 } 603 604 pp->irq_shared = false; 605 pp->gpio_base = -1; 606 607 /* 608 * Only port A can provide interrupts in all configurations of 609 * the IP. 610 */ 611 if (pp->idx != 0) 612 continue; 613 614 if (dev->of_node && fwnode_property_read_bool(fwnode, 615 "interrupt-controller")) { 616 np = to_of_node(fwnode); 617 } 618 619 for (j = 0; j < pp->ngpio; j++) { 620 pp->irq[j] = -ENXIO; 621 622 if (np) 623 pp->irq[j] = of_irq_get(np, j); 624 else if (has_acpi_companion(dev)) 625 pp->irq[j] = platform_get_irq(to_platform_device(dev), j); 626 627 if (pp->irq[j] >= 0) 628 pp->has_irq = true; 629 } 630 631 if (!pp->has_irq) 632 dev_warn(dev, "no irq for port%d\n", pp->idx); 633 } 634 635 return pdata; 636 } 637 638 static const struct of_device_id dwapb_of_match[] = { 639 { .compatible = "snps,dw-apb-gpio", .data = (void *)0}, 640 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2}, 641 { /* Sentinel */ } 642 }; 643 MODULE_DEVICE_TABLE(of, dwapb_of_match); 644 645 static const struct acpi_device_id dwapb_acpi_match[] = { 646 {"HISI0181", 0}, 647 {"APMC0D07", 0}, 648 {"APMC0D81", GPIO_REG_OFFSET_V2}, 649 { } 650 }; 651 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); 652 653 static int dwapb_gpio_probe(struct platform_device *pdev) 654 { 655 unsigned int i; 656 struct resource *res; 657 struct dwapb_gpio *gpio; 658 int err; 659 struct device *dev = &pdev->dev; 660 struct dwapb_platform_data *pdata = dev_get_platdata(dev); 661 662 if (!pdata) { 663 pdata = dwapb_gpio_get_pdata(dev); 664 if (IS_ERR(pdata)) 665 return PTR_ERR(pdata); 666 } 667 668 if (!pdata->nports) 669 return -ENODEV; 670 671 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 672 if (!gpio) 673 return -ENOMEM; 674 675 gpio->dev = &pdev->dev; 676 gpio->nr_ports = pdata->nports; 677 678 gpio->rst = devm_reset_control_get_optional_shared(dev, NULL); 679 if (IS_ERR(gpio->rst)) 680 return PTR_ERR(gpio->rst); 681 682 reset_control_deassert(gpio->rst); 683 684 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, 685 sizeof(*gpio->ports), GFP_KERNEL); 686 if (!gpio->ports) 687 return -ENOMEM; 688 689 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 690 gpio->regs = devm_ioremap_resource(&pdev->dev, res); 691 if (IS_ERR(gpio->regs)) 692 return PTR_ERR(gpio->regs); 693 694 /* Optional bus clock */ 695 gpio->clk = devm_clk_get(&pdev->dev, "bus"); 696 if (!IS_ERR(gpio->clk)) { 697 err = clk_prepare_enable(gpio->clk); 698 if (err) { 699 dev_info(&pdev->dev, "Cannot enable clock\n"); 700 return err; 701 } 702 } 703 704 gpio->flags = 0; 705 if (dev->of_node) { 706 gpio->flags = (uintptr_t)of_device_get_match_data(dev); 707 } else if (has_acpi_companion(dev)) { 708 const struct acpi_device_id *acpi_id; 709 710 acpi_id = acpi_match_device(dwapb_acpi_match, dev); 711 if (acpi_id) { 712 if (acpi_id->driver_data) 713 gpio->flags = acpi_id->driver_data; 714 } 715 } 716 717 for (i = 0; i < gpio->nr_ports; i++) { 718 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); 719 if (err) 720 goto out_unregister; 721 } 722 platform_set_drvdata(pdev, gpio); 723 724 return 0; 725 726 out_unregister: 727 dwapb_gpio_unregister(gpio); 728 dwapb_irq_teardown(gpio); 729 730 return err; 731 } 732 733 static int dwapb_gpio_remove(struct platform_device *pdev) 734 { 735 struct dwapb_gpio *gpio = platform_get_drvdata(pdev); 736 737 dwapb_gpio_unregister(gpio); 738 dwapb_irq_teardown(gpio); 739 reset_control_assert(gpio->rst); 740 clk_disable_unprepare(gpio->clk); 741 742 return 0; 743 } 744 745 #ifdef CONFIG_PM_SLEEP 746 static int dwapb_gpio_suspend(struct device *dev) 747 { 748 struct platform_device *pdev = to_platform_device(dev); 749 struct dwapb_gpio *gpio = platform_get_drvdata(pdev); 750 struct gpio_chip *gc = &gpio->ports[0].gc; 751 unsigned long flags; 752 int i; 753 754 spin_lock_irqsave(&gc->bgpio_lock, flags); 755 for (i = 0; i < gpio->nr_ports; i++) { 756 unsigned int offset; 757 unsigned int idx = gpio->ports[i].idx; 758 struct dwapb_context *ctx = gpio->ports[i].ctx; 759 760 BUG_ON(!ctx); 761 762 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 763 ctx->dir = dwapb_read(gpio, offset); 764 765 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 766 ctx->data = dwapb_read(gpio, offset); 767 768 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 769 ctx->ext = dwapb_read(gpio, offset); 770 771 /* Only port A can provide interrupts */ 772 if (idx == 0) { 773 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); 774 ctx->int_en = dwapb_read(gpio, GPIO_INTEN); 775 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); 776 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 777 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 778 779 /* Mask out interrupts */ 780 dwapb_write(gpio, GPIO_INTMASK, 781 0xffffffff & ~ctx->wake_en); 782 } 783 } 784 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 785 786 clk_disable_unprepare(gpio->clk); 787 788 return 0; 789 } 790 791 static int dwapb_gpio_resume(struct device *dev) 792 { 793 struct platform_device *pdev = to_platform_device(dev); 794 struct dwapb_gpio *gpio = platform_get_drvdata(pdev); 795 struct gpio_chip *gc = &gpio->ports[0].gc; 796 unsigned long flags; 797 int i; 798 799 if (!IS_ERR(gpio->clk)) 800 clk_prepare_enable(gpio->clk); 801 802 spin_lock_irqsave(&gc->bgpio_lock, flags); 803 for (i = 0; i < gpio->nr_ports; i++) { 804 unsigned int offset; 805 unsigned int idx = gpio->ports[i].idx; 806 struct dwapb_context *ctx = gpio->ports[i].ctx; 807 808 BUG_ON(!ctx); 809 810 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 811 dwapb_write(gpio, offset, ctx->data); 812 813 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 814 dwapb_write(gpio, offset, ctx->dir); 815 816 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 817 dwapb_write(gpio, offset, ctx->ext); 818 819 /* Only port A can provide interrupts */ 820 if (idx == 0) { 821 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); 822 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); 823 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); 824 dwapb_write(gpio, GPIO_INTEN, ctx->int_en); 825 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); 826 827 /* Clear out spurious interrupts */ 828 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); 829 } 830 } 831 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 832 833 return 0; 834 } 835 #endif 836 837 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, 838 dwapb_gpio_resume); 839 840 static struct platform_driver dwapb_gpio_driver = { 841 .driver = { 842 .name = "gpio-dwapb", 843 .pm = &dwapb_gpio_pm_ops, 844 .of_match_table = of_match_ptr(dwapb_of_match), 845 .acpi_match_table = ACPI_PTR(dwapb_acpi_match), 846 }, 847 .probe = dwapb_gpio_probe, 848 .remove = dwapb_gpio_remove, 849 }; 850 851 module_platform_driver(dwapb_gpio_driver); 852 853 MODULE_LICENSE("GPL"); 854 MODULE_AUTHOR("Jamie Iles"); 855 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); 856