1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2011 Jamie Iles 4 * 5 * All enquiries to support@picochip.com 6 */ 7 #include <linux/acpi.h> 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_device.h> 21 #include <linux/of_irq.h> 22 #include <linux/platform_device.h> 23 #include <linux/property.h> 24 #include <linux/reset.h> 25 #include <linux/spinlock.h> 26 #include <linux/platform_data/gpio-dwapb.h> 27 #include <linux/slab.h> 28 29 #include "gpiolib.h" 30 31 #define GPIO_SWPORTA_DR 0x00 32 #define GPIO_SWPORTA_DDR 0x04 33 #define GPIO_SWPORTB_DR 0x0c 34 #define GPIO_SWPORTB_DDR 0x10 35 #define GPIO_SWPORTC_DR 0x18 36 #define GPIO_SWPORTC_DDR 0x1c 37 #define GPIO_SWPORTD_DR 0x24 38 #define GPIO_SWPORTD_DDR 0x28 39 #define GPIO_INTEN 0x30 40 #define GPIO_INTMASK 0x34 41 #define GPIO_INTTYPE_LEVEL 0x38 42 #define GPIO_INT_POLARITY 0x3c 43 #define GPIO_INTSTATUS 0x40 44 #define GPIO_PORTA_DEBOUNCE 0x48 45 #define GPIO_PORTA_EOI 0x4c 46 #define GPIO_EXT_PORTA 0x50 47 #define GPIO_EXT_PORTB 0x54 48 #define GPIO_EXT_PORTC 0x58 49 #define GPIO_EXT_PORTD 0x5c 50 51 #define DWAPB_MAX_PORTS 4 52 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */ 53 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */ 54 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */ 55 56 #define GPIO_REG_OFFSET_V2 1 57 58 #define GPIO_INTMASK_V2 0x44 59 #define GPIO_INTTYPE_LEVEL_V2 0x34 60 #define GPIO_INT_POLARITY_V2 0x38 61 #define GPIO_INTSTATUS_V2 0x3c 62 #define GPIO_PORTA_EOI_V2 0x40 63 64 struct dwapb_gpio; 65 66 #ifdef CONFIG_PM_SLEEP 67 /* Store GPIO context across system-wide suspend/resume transitions */ 68 struct dwapb_context { 69 u32 data; 70 u32 dir; 71 u32 ext; 72 u32 int_en; 73 u32 int_mask; 74 u32 int_type; 75 u32 int_pol; 76 u32 int_deb; 77 u32 wake_en; 78 }; 79 #endif 80 81 struct dwapb_gpio_port { 82 struct gpio_chip gc; 83 bool is_registered; 84 struct dwapb_gpio *gpio; 85 #ifdef CONFIG_PM_SLEEP 86 struct dwapb_context *ctx; 87 #endif 88 unsigned int idx; 89 }; 90 91 struct dwapb_gpio { 92 struct device *dev; 93 void __iomem *regs; 94 struct dwapb_gpio_port *ports; 95 unsigned int nr_ports; 96 struct irq_domain *domain; 97 unsigned int flags; 98 struct reset_control *rst; 99 struct clk *clk; 100 }; 101 102 static inline u32 gpio_reg_v2_convert(unsigned int offset) 103 { 104 switch (offset) { 105 case GPIO_INTMASK: 106 return GPIO_INTMASK_V2; 107 case GPIO_INTTYPE_LEVEL: 108 return GPIO_INTTYPE_LEVEL_V2; 109 case GPIO_INT_POLARITY: 110 return GPIO_INT_POLARITY_V2; 111 case GPIO_INTSTATUS: 112 return GPIO_INTSTATUS_V2; 113 case GPIO_PORTA_EOI: 114 return GPIO_PORTA_EOI_V2; 115 } 116 117 return offset; 118 } 119 120 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) 121 { 122 if (gpio->flags & GPIO_REG_OFFSET_V2) 123 return gpio_reg_v2_convert(offset); 124 125 return offset; 126 } 127 128 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) 129 { 130 struct gpio_chip *gc = &gpio->ports[0].gc; 131 void __iomem *reg_base = gpio->regs; 132 133 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); 134 } 135 136 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, 137 u32 val) 138 { 139 struct gpio_chip *gc = &gpio->ports[0].gc; 140 void __iomem *reg_base = gpio->regs; 141 142 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); 143 } 144 145 static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 146 { 147 struct dwapb_gpio_port *port = gpiochip_get_data(gc); 148 struct dwapb_gpio *gpio = port->gpio; 149 150 return irq_find_mapping(gpio->domain, offset); 151 } 152 153 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) 154 { 155 struct dwapb_gpio_port *port; 156 int i; 157 158 for (i = 0; i < gpio->nr_ports; i++) { 159 port = &gpio->ports[i]; 160 if (port->idx == offs / 32) 161 return port; 162 } 163 164 return NULL; 165 } 166 167 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) 168 { 169 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); 170 struct gpio_chip *gc; 171 u32 pol; 172 int val; 173 174 if (!port) 175 return; 176 gc = &port->gc; 177 178 pol = dwapb_read(gpio, GPIO_INT_POLARITY); 179 /* Just read the current value right out of the data register */ 180 val = gc->get(gc, offs % 32); 181 if (val) 182 pol &= ~BIT(offs); 183 else 184 pol |= BIT(offs); 185 186 dwapb_write(gpio, GPIO_INT_POLARITY, pol); 187 } 188 189 static u32 dwapb_do_irq(struct dwapb_gpio *gpio) 190 { 191 u32 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); 192 u32 ret = irq_status; 193 194 while (irq_status) { 195 int hwirq = fls(irq_status) - 1; 196 int gpio_irq = irq_find_mapping(gpio->domain, hwirq); 197 198 generic_handle_irq(gpio_irq); 199 irq_status &= ~BIT(hwirq); 200 201 if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK) 202 == IRQ_TYPE_EDGE_BOTH) 203 dwapb_toggle_trigger(gpio, hwirq); 204 } 205 206 return ret; 207 } 208 209 static void dwapb_irq_handler(struct irq_desc *desc) 210 { 211 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); 212 struct irq_chip *chip = irq_desc_get_chip(desc); 213 214 dwapb_do_irq(gpio); 215 216 if (chip->irq_eoi) 217 chip->irq_eoi(irq_desc_get_irq_data(desc)); 218 } 219 220 static void dwapb_irq_enable(struct irq_data *d) 221 { 222 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 223 struct dwapb_gpio *gpio = igc->private; 224 struct gpio_chip *gc = &gpio->ports[0].gc; 225 unsigned long flags; 226 u32 val; 227 228 spin_lock_irqsave(&gc->bgpio_lock, flags); 229 val = dwapb_read(gpio, GPIO_INTEN); 230 val |= BIT(d->hwirq); 231 dwapb_write(gpio, GPIO_INTEN, val); 232 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 233 } 234 235 static void dwapb_irq_disable(struct irq_data *d) 236 { 237 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 238 struct dwapb_gpio *gpio = igc->private; 239 struct gpio_chip *gc = &gpio->ports[0].gc; 240 unsigned long flags; 241 u32 val; 242 243 spin_lock_irqsave(&gc->bgpio_lock, flags); 244 val = dwapb_read(gpio, GPIO_INTEN); 245 val &= ~BIT(d->hwirq); 246 dwapb_write(gpio, GPIO_INTEN, val); 247 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 248 } 249 250 static int dwapb_irq_reqres(struct irq_data *d) 251 { 252 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 253 struct dwapb_gpio *gpio = igc->private; 254 struct gpio_chip *gc = &gpio->ports[0].gc; 255 int ret; 256 257 ret = gpiochip_lock_as_irq(gc, irqd_to_hwirq(d)); 258 if (ret) { 259 dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n", 260 irqd_to_hwirq(d)); 261 return ret; 262 } 263 return 0; 264 } 265 266 static void dwapb_irq_relres(struct irq_data *d) 267 { 268 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 269 struct dwapb_gpio *gpio = igc->private; 270 struct gpio_chip *gc = &gpio->ports[0].gc; 271 272 gpiochip_unlock_as_irq(gc, irqd_to_hwirq(d)); 273 } 274 275 static int dwapb_irq_set_type(struct irq_data *d, u32 type) 276 { 277 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 278 struct dwapb_gpio *gpio = igc->private; 279 struct gpio_chip *gc = &gpio->ports[0].gc; 280 int bit = d->hwirq; 281 unsigned long level, polarity, flags; 282 283 if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | 284 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) 285 return -EINVAL; 286 287 spin_lock_irqsave(&gc->bgpio_lock, flags); 288 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 289 polarity = dwapb_read(gpio, GPIO_INT_POLARITY); 290 291 switch (type) { 292 case IRQ_TYPE_EDGE_BOTH: 293 level |= BIT(bit); 294 dwapb_toggle_trigger(gpio, bit); 295 break; 296 case IRQ_TYPE_EDGE_RISING: 297 level |= BIT(bit); 298 polarity |= BIT(bit); 299 break; 300 case IRQ_TYPE_EDGE_FALLING: 301 level |= BIT(bit); 302 polarity &= ~BIT(bit); 303 break; 304 case IRQ_TYPE_LEVEL_HIGH: 305 level &= ~BIT(bit); 306 polarity |= BIT(bit); 307 break; 308 case IRQ_TYPE_LEVEL_LOW: 309 level &= ~BIT(bit); 310 polarity &= ~BIT(bit); 311 break; 312 } 313 314 irq_setup_alt_chip(d, type); 315 316 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); 317 if (type != IRQ_TYPE_EDGE_BOTH) 318 dwapb_write(gpio, GPIO_INT_POLARITY, polarity); 319 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 320 321 return 0; 322 } 323 324 #ifdef CONFIG_PM_SLEEP 325 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable) 326 { 327 struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d); 328 struct dwapb_gpio *gpio = igc->private; 329 struct dwapb_context *ctx = gpio->ports[0].ctx; 330 331 if (enable) 332 ctx->wake_en |= BIT(d->hwirq); 333 else 334 ctx->wake_en &= ~BIT(d->hwirq); 335 336 return 0; 337 } 338 #endif 339 340 static int dwapb_gpio_set_debounce(struct gpio_chip *gc, 341 unsigned offset, unsigned debounce) 342 { 343 struct dwapb_gpio_port *port = gpiochip_get_data(gc); 344 struct dwapb_gpio *gpio = port->gpio; 345 unsigned long flags, val_deb; 346 unsigned long mask = BIT(offset); 347 348 spin_lock_irqsave(&gc->bgpio_lock, flags); 349 350 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 351 if (debounce) 352 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask); 353 else 354 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask); 355 356 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 357 358 return 0; 359 } 360 361 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, 362 unsigned long config) 363 { 364 u32 debounce; 365 366 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 367 return -ENOTSUPP; 368 369 debounce = pinconf_to_config_argument(config); 370 return dwapb_gpio_set_debounce(gc, offset, debounce); 371 } 372 373 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) 374 { 375 u32 worked; 376 struct dwapb_gpio *gpio = dev_id; 377 378 worked = dwapb_do_irq(gpio); 379 380 return worked ? IRQ_HANDLED : IRQ_NONE; 381 } 382 383 static void dwapb_configure_irqs(struct dwapb_gpio *gpio, 384 struct dwapb_gpio_port *port, 385 struct dwapb_port_property *pp) 386 { 387 struct gpio_chip *gc = &port->gc; 388 struct fwnode_handle *fwnode = pp->fwnode; 389 struct irq_chip_generic *irq_gc = NULL; 390 unsigned int hwirq, ngpio = gc->ngpio; 391 struct irq_chip_type *ct; 392 int err, i; 393 394 gpio->domain = irq_domain_create_linear(fwnode, ngpio, 395 &irq_generic_chip_ops, gpio); 396 if (!gpio->domain) 397 return; 398 399 err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2, 400 "gpio-dwapb", handle_level_irq, 401 IRQ_NOREQUEST, 0, 402 IRQ_GC_INIT_NESTED_LOCK); 403 if (err) { 404 dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n"); 405 irq_domain_remove(gpio->domain); 406 gpio->domain = NULL; 407 return; 408 } 409 410 irq_gc = irq_get_domain_generic_chip(gpio->domain, 0); 411 if (!irq_gc) { 412 irq_domain_remove(gpio->domain); 413 gpio->domain = NULL; 414 return; 415 } 416 417 irq_gc->reg_base = gpio->regs; 418 irq_gc->private = gpio; 419 420 for (i = 0; i < 2; i++) { 421 ct = &irq_gc->chip_types[i]; 422 ct->chip.irq_ack = irq_gc_ack_set_bit; 423 ct->chip.irq_mask = irq_gc_mask_set_bit; 424 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 425 ct->chip.irq_set_type = dwapb_irq_set_type; 426 ct->chip.irq_enable = dwapb_irq_enable; 427 ct->chip.irq_disable = dwapb_irq_disable; 428 ct->chip.irq_request_resources = dwapb_irq_reqres; 429 ct->chip.irq_release_resources = dwapb_irq_relres; 430 #ifdef CONFIG_PM_SLEEP 431 ct->chip.irq_set_wake = dwapb_irq_set_wake; 432 #endif 433 ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI); 434 ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK); 435 ct->type = IRQ_TYPE_LEVEL_MASK; 436 } 437 438 irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; 439 irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; 440 irq_gc->chip_types[1].handler = handle_edge_irq; 441 442 if (!pp->irq_shared) { 443 int i; 444 445 for (i = 0; i < pp->ngpio; i++) { 446 if (pp->irq[i] >= 0) 447 irq_set_chained_handler_and_data(pp->irq[i], 448 dwapb_irq_handler, gpio); 449 } 450 } else { 451 /* 452 * Request a shared IRQ since where MFD would have devices 453 * using the same irq pin 454 */ 455 err = devm_request_irq(gpio->dev, pp->irq[0], 456 dwapb_irq_handler_mfd, 457 IRQF_SHARED, "gpio-dwapb-mfd", gpio); 458 if (err) { 459 dev_err(gpio->dev, "error requesting IRQ\n"); 460 irq_domain_remove(gpio->domain); 461 gpio->domain = NULL; 462 return; 463 } 464 } 465 466 for (hwirq = 0 ; hwirq < ngpio ; hwirq++) 467 irq_create_mapping(gpio->domain, hwirq); 468 469 port->gc.to_irq = dwapb_gpio_to_irq; 470 } 471 472 static void dwapb_irq_teardown(struct dwapb_gpio *gpio) 473 { 474 struct dwapb_gpio_port *port = &gpio->ports[0]; 475 struct gpio_chip *gc = &port->gc; 476 unsigned int ngpio = gc->ngpio; 477 irq_hw_number_t hwirq; 478 479 if (!gpio->domain) 480 return; 481 482 for (hwirq = 0 ; hwirq < ngpio ; hwirq++) 483 irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq)); 484 485 irq_domain_remove(gpio->domain); 486 gpio->domain = NULL; 487 } 488 489 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, 490 struct dwapb_port_property *pp, 491 unsigned int offs) 492 { 493 struct dwapb_gpio_port *port; 494 void __iomem *dat, *set, *dirout; 495 int err; 496 497 port = &gpio->ports[offs]; 498 port->gpio = gpio; 499 port->idx = pp->idx; 500 501 #ifdef CONFIG_PM_SLEEP 502 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); 503 if (!port->ctx) 504 return -ENOMEM; 505 #endif 506 507 dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_STRIDE); 508 set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_STRIDE); 509 dirout = gpio->regs + GPIO_SWPORTA_DDR + 510 (pp->idx * GPIO_SWPORT_DDR_STRIDE); 511 512 /* This registers 32 GPIO lines per port */ 513 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, 514 NULL, 0); 515 if (err) { 516 dev_err(gpio->dev, "failed to init gpio chip for port%d\n", 517 port->idx); 518 return err; 519 } 520 521 #ifdef CONFIG_OF_GPIO 522 port->gc.of_node = to_of_node(pp->fwnode); 523 #endif 524 port->gc.ngpio = pp->ngpio; 525 port->gc.base = pp->gpio_base; 526 527 /* Only port A support debounce */ 528 if (pp->idx == 0) 529 port->gc.set_config = dwapb_gpio_set_config; 530 531 if (pp->has_irq) 532 dwapb_configure_irqs(gpio, port, pp); 533 534 err = gpiochip_add_data(&port->gc, port); 535 if (err) 536 dev_err(gpio->dev, "failed to register gpiochip for port%d\n", 537 port->idx); 538 else 539 port->is_registered = true; 540 541 /* Add GPIO-signaled ACPI event support */ 542 if (pp->has_irq) 543 acpi_gpiochip_request_interrupts(&port->gc); 544 545 return err; 546 } 547 548 static void dwapb_gpio_unregister(struct dwapb_gpio *gpio) 549 { 550 unsigned int m; 551 552 for (m = 0; m < gpio->nr_ports; ++m) 553 if (gpio->ports[m].is_registered) 554 gpiochip_remove(&gpio->ports[m].gc); 555 } 556 557 static struct dwapb_platform_data * 558 dwapb_gpio_get_pdata(struct device *dev) 559 { 560 struct fwnode_handle *fwnode; 561 struct dwapb_platform_data *pdata; 562 struct dwapb_port_property *pp; 563 int nports; 564 int i, j; 565 566 nports = device_get_child_node_count(dev); 567 if (nports == 0) 568 return ERR_PTR(-ENODEV); 569 570 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 571 if (!pdata) 572 return ERR_PTR(-ENOMEM); 573 574 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); 575 if (!pdata->properties) 576 return ERR_PTR(-ENOMEM); 577 578 pdata->nports = nports; 579 580 i = 0; 581 device_for_each_child_node(dev, fwnode) { 582 struct device_node *np = NULL; 583 584 pp = &pdata->properties[i++]; 585 pp->fwnode = fwnode; 586 587 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || 588 pp->idx >= DWAPB_MAX_PORTS) { 589 dev_err(dev, 590 "missing/invalid port index for port%d\n", i); 591 fwnode_handle_put(fwnode); 592 return ERR_PTR(-EINVAL); 593 } 594 595 if (fwnode_property_read_u32(fwnode, "snps,nr-gpios", 596 &pp->ngpio)) { 597 dev_info(dev, 598 "failed to get number of gpios for port%d\n", 599 i); 600 pp->ngpio = 32; 601 } 602 603 pp->irq_shared = false; 604 pp->gpio_base = -1; 605 606 /* 607 * Only port A can provide interrupts in all configurations of 608 * the IP. 609 */ 610 if (pp->idx != 0) 611 continue; 612 613 if (dev->of_node && fwnode_property_read_bool(fwnode, 614 "interrupt-controller")) { 615 np = to_of_node(fwnode); 616 } 617 618 for (j = 0; j < pp->ngpio; j++) { 619 pp->irq[j] = -ENXIO; 620 621 if (np) 622 pp->irq[j] = of_irq_get(np, j); 623 else if (has_acpi_companion(dev)) 624 pp->irq[j] = platform_get_irq(to_platform_device(dev), j); 625 626 if (pp->irq[j] >= 0) 627 pp->has_irq = true; 628 } 629 630 if (!pp->has_irq) 631 dev_warn(dev, "no irq for port%d\n", pp->idx); 632 } 633 634 return pdata; 635 } 636 637 static const struct of_device_id dwapb_of_match[] = { 638 { .compatible = "snps,dw-apb-gpio", .data = (void *)0}, 639 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2}, 640 { /* Sentinel */ } 641 }; 642 MODULE_DEVICE_TABLE(of, dwapb_of_match); 643 644 static const struct acpi_device_id dwapb_acpi_match[] = { 645 {"HISI0181", 0}, 646 {"APMC0D07", 0}, 647 {"APMC0D81", GPIO_REG_OFFSET_V2}, 648 { } 649 }; 650 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); 651 652 static int dwapb_gpio_probe(struct platform_device *pdev) 653 { 654 unsigned int i; 655 struct dwapb_gpio *gpio; 656 int err; 657 struct device *dev = &pdev->dev; 658 struct dwapb_platform_data *pdata = dev_get_platdata(dev); 659 660 if (!pdata) { 661 pdata = dwapb_gpio_get_pdata(dev); 662 if (IS_ERR(pdata)) 663 return PTR_ERR(pdata); 664 } 665 666 if (!pdata->nports) 667 return -ENODEV; 668 669 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 670 if (!gpio) 671 return -ENOMEM; 672 673 gpio->dev = &pdev->dev; 674 gpio->nr_ports = pdata->nports; 675 676 gpio->rst = devm_reset_control_get_optional_shared(dev, NULL); 677 if (IS_ERR(gpio->rst)) 678 return PTR_ERR(gpio->rst); 679 680 reset_control_deassert(gpio->rst); 681 682 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, 683 sizeof(*gpio->ports), GFP_KERNEL); 684 if (!gpio->ports) 685 return -ENOMEM; 686 687 gpio->regs = devm_platform_ioremap_resource(pdev, 0); 688 if (IS_ERR(gpio->regs)) 689 return PTR_ERR(gpio->regs); 690 691 /* Optional bus clock */ 692 gpio->clk = devm_clk_get(&pdev->dev, "bus"); 693 if (!IS_ERR(gpio->clk)) { 694 err = clk_prepare_enable(gpio->clk); 695 if (err) { 696 dev_info(&pdev->dev, "Cannot enable clock\n"); 697 return err; 698 } 699 } 700 701 gpio->flags = 0; 702 if (dev->of_node) { 703 gpio->flags = (uintptr_t)of_device_get_match_data(dev); 704 } else if (has_acpi_companion(dev)) { 705 const struct acpi_device_id *acpi_id; 706 707 acpi_id = acpi_match_device(dwapb_acpi_match, dev); 708 if (acpi_id) { 709 if (acpi_id->driver_data) 710 gpio->flags = acpi_id->driver_data; 711 } 712 } 713 714 for (i = 0; i < gpio->nr_ports; i++) { 715 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); 716 if (err) 717 goto out_unregister; 718 } 719 platform_set_drvdata(pdev, gpio); 720 721 return 0; 722 723 out_unregister: 724 dwapb_gpio_unregister(gpio); 725 dwapb_irq_teardown(gpio); 726 clk_disable_unprepare(gpio->clk); 727 728 return err; 729 } 730 731 static int dwapb_gpio_remove(struct platform_device *pdev) 732 { 733 struct dwapb_gpio *gpio = platform_get_drvdata(pdev); 734 735 dwapb_gpio_unregister(gpio); 736 dwapb_irq_teardown(gpio); 737 reset_control_assert(gpio->rst); 738 clk_disable_unprepare(gpio->clk); 739 740 return 0; 741 } 742 743 #ifdef CONFIG_PM_SLEEP 744 static int dwapb_gpio_suspend(struct device *dev) 745 { 746 struct dwapb_gpio *gpio = dev_get_drvdata(dev); 747 struct gpio_chip *gc = &gpio->ports[0].gc; 748 unsigned long flags; 749 int i; 750 751 spin_lock_irqsave(&gc->bgpio_lock, flags); 752 for (i = 0; i < gpio->nr_ports; i++) { 753 unsigned int offset; 754 unsigned int idx = gpio->ports[i].idx; 755 struct dwapb_context *ctx = gpio->ports[i].ctx; 756 757 BUG_ON(!ctx); 758 759 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 760 ctx->dir = dwapb_read(gpio, offset); 761 762 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 763 ctx->data = dwapb_read(gpio, offset); 764 765 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 766 ctx->ext = dwapb_read(gpio, offset); 767 768 /* Only port A can provide interrupts */ 769 if (idx == 0) { 770 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); 771 ctx->int_en = dwapb_read(gpio, GPIO_INTEN); 772 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); 773 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 774 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 775 776 /* Mask out interrupts */ 777 dwapb_write(gpio, GPIO_INTMASK, 778 0xffffffff & ~ctx->wake_en); 779 } 780 } 781 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 782 783 clk_disable_unprepare(gpio->clk); 784 785 return 0; 786 } 787 788 static int dwapb_gpio_resume(struct device *dev) 789 { 790 struct dwapb_gpio *gpio = dev_get_drvdata(dev); 791 struct gpio_chip *gc = &gpio->ports[0].gc; 792 unsigned long flags; 793 int i; 794 795 if (!IS_ERR(gpio->clk)) 796 clk_prepare_enable(gpio->clk); 797 798 spin_lock_irqsave(&gc->bgpio_lock, flags); 799 for (i = 0; i < gpio->nr_ports; i++) { 800 unsigned int offset; 801 unsigned int idx = gpio->ports[i].idx; 802 struct dwapb_context *ctx = gpio->ports[i].ctx; 803 804 BUG_ON(!ctx); 805 806 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 807 dwapb_write(gpio, offset, ctx->data); 808 809 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 810 dwapb_write(gpio, offset, ctx->dir); 811 812 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 813 dwapb_write(gpio, offset, ctx->ext); 814 815 /* Only port A can provide interrupts */ 816 if (idx == 0) { 817 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); 818 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); 819 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); 820 dwapb_write(gpio, GPIO_INTEN, ctx->int_en); 821 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); 822 823 /* Clear out spurious interrupts */ 824 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); 825 } 826 } 827 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 828 829 return 0; 830 } 831 #endif 832 833 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, 834 dwapb_gpio_resume); 835 836 static struct platform_driver dwapb_gpio_driver = { 837 .driver = { 838 .name = "gpio-dwapb", 839 .pm = &dwapb_gpio_pm_ops, 840 .of_match_table = of_match_ptr(dwapb_of_match), 841 .acpi_match_table = ACPI_PTR(dwapb_acpi_match), 842 }, 843 .probe = dwapb_gpio_probe, 844 .remove = dwapb_gpio_remove, 845 }; 846 847 module_platform_driver(dwapb_gpio_driver); 848 849 MODULE_LICENSE("GPL"); 850 MODULE_AUTHOR("Jamie Iles"); 851 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); 852