xref: /openbmc/linux/drivers/gpio/gpio-dwapb.c (revision 3ddc8b84) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2011 Jamie Iles
4  *
5  * All enquiries to support@picochip.com
6  */
7 #include <linux/acpi.h>
8 #include <linux/clk.h>
9 #include <linux/err.h>
10 #include <linux/gpio/driver.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/reset.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 
24 #include "gpiolib.h"
25 #include "gpiolib-acpi.h"
26 
27 #define GPIO_SWPORTA_DR		0x00
28 #define GPIO_SWPORTA_DDR	0x04
29 #define GPIO_SWPORTB_DR		0x0c
30 #define GPIO_SWPORTB_DDR	0x10
31 #define GPIO_SWPORTC_DR		0x18
32 #define GPIO_SWPORTC_DDR	0x1c
33 #define GPIO_SWPORTD_DR		0x24
34 #define GPIO_SWPORTD_DDR	0x28
35 #define GPIO_INTEN		0x30
36 #define GPIO_INTMASK		0x34
37 #define GPIO_INTTYPE_LEVEL	0x38
38 #define GPIO_INT_POLARITY	0x3c
39 #define GPIO_INTSTATUS		0x40
40 #define GPIO_PORTA_DEBOUNCE	0x48
41 #define GPIO_PORTA_EOI		0x4c
42 #define GPIO_EXT_PORTA		0x50
43 #define GPIO_EXT_PORTB		0x54
44 #define GPIO_EXT_PORTC		0x58
45 #define GPIO_EXT_PORTD		0x5c
46 
47 #define DWAPB_DRIVER_NAME	"gpio-dwapb"
48 #define DWAPB_MAX_PORTS		4
49 #define DWAPB_MAX_GPIOS		32
50 
51 #define GPIO_EXT_PORT_STRIDE	0x04 /* register stride 32 bits */
52 #define GPIO_SWPORT_DR_STRIDE	0x0c /* register stride 3*32 bits */
53 #define GPIO_SWPORT_DDR_STRIDE	0x0c /* register stride 3*32 bits */
54 
55 #define GPIO_REG_OFFSET_V1	0
56 #define GPIO_REG_OFFSET_V2	1
57 #define GPIO_REG_OFFSET_MASK	BIT(0)
58 
59 #define GPIO_INTMASK_V2		0x44
60 #define GPIO_INTTYPE_LEVEL_V2	0x34
61 #define GPIO_INT_POLARITY_V2	0x38
62 #define GPIO_INTSTATUS_V2	0x3c
63 #define GPIO_PORTA_EOI_V2	0x40
64 
65 #define DWAPB_NR_CLOCKS		2
66 
67 struct dwapb_gpio;
68 
69 struct dwapb_port_property {
70 	struct fwnode_handle *fwnode;
71 	unsigned int idx;
72 	unsigned int ngpio;
73 	unsigned int gpio_base;
74 	int irq[DWAPB_MAX_GPIOS];
75 };
76 
77 struct dwapb_platform_data {
78 	struct dwapb_port_property *properties;
79 	unsigned int nports;
80 };
81 
82 #ifdef CONFIG_PM_SLEEP
83 /* Store GPIO context across system-wide suspend/resume transitions */
84 struct dwapb_context {
85 	u32 data;
86 	u32 dir;
87 	u32 ext;
88 	u32 int_en;
89 	u32 int_mask;
90 	u32 int_type;
91 	u32 int_pol;
92 	u32 int_deb;
93 	u32 wake_en;
94 };
95 #endif
96 
97 struct dwapb_gpio_port_irqchip {
98 	unsigned int		nr_irqs;
99 	unsigned int		irq[DWAPB_MAX_GPIOS];
100 };
101 
102 struct dwapb_gpio_port {
103 	struct gpio_chip	gc;
104 	struct dwapb_gpio_port_irqchip *pirq;
105 	struct dwapb_gpio	*gpio;
106 #ifdef CONFIG_PM_SLEEP
107 	struct dwapb_context	*ctx;
108 #endif
109 	unsigned int		idx;
110 };
111 #define to_dwapb_gpio(_gc) \
112 	(container_of(_gc, struct dwapb_gpio_port, gc)->gpio)
113 
114 struct dwapb_gpio {
115 	struct	device		*dev;
116 	void __iomem		*regs;
117 	struct dwapb_gpio_port	*ports;
118 	unsigned int		nr_ports;
119 	unsigned int		flags;
120 	struct reset_control	*rst;
121 	struct clk_bulk_data	clks[DWAPB_NR_CLOCKS];
122 };
123 
124 static inline u32 gpio_reg_v2_convert(unsigned int offset)
125 {
126 	switch (offset) {
127 	case GPIO_INTMASK:
128 		return GPIO_INTMASK_V2;
129 	case GPIO_INTTYPE_LEVEL:
130 		return GPIO_INTTYPE_LEVEL_V2;
131 	case GPIO_INT_POLARITY:
132 		return GPIO_INT_POLARITY_V2;
133 	case GPIO_INTSTATUS:
134 		return GPIO_INTSTATUS_V2;
135 	case GPIO_PORTA_EOI:
136 		return GPIO_PORTA_EOI_V2;
137 	}
138 
139 	return offset;
140 }
141 
142 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset)
143 {
144 	if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2)
145 		return gpio_reg_v2_convert(offset);
146 
147 	return offset;
148 }
149 
150 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
151 {
152 	struct gpio_chip *gc	= &gpio->ports[0].gc;
153 	void __iomem *reg_base	= gpio->regs;
154 
155 	return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset));
156 }
157 
158 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
159 			       u32 val)
160 {
161 	struct gpio_chip *gc	= &gpio->ports[0].gc;
162 	void __iomem *reg_base	= gpio->regs;
163 
164 	gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val);
165 }
166 
167 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs)
168 {
169 	struct dwapb_gpio_port *port;
170 	int i;
171 
172 	for (i = 0; i < gpio->nr_ports; i++) {
173 		port = &gpio->ports[i];
174 		if (port->idx == offs / DWAPB_MAX_GPIOS)
175 			return port;
176 	}
177 
178 	return NULL;
179 }
180 
181 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
182 {
183 	struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs);
184 	struct gpio_chip *gc;
185 	u32 pol;
186 	int val;
187 
188 	if (!port)
189 		return;
190 	gc = &port->gc;
191 
192 	pol = dwapb_read(gpio, GPIO_INT_POLARITY);
193 	/* Just read the current value right out of the data register */
194 	val = gc->get(gc, offs % DWAPB_MAX_GPIOS);
195 	if (val)
196 		pol &= ~BIT(offs);
197 	else
198 		pol |= BIT(offs);
199 
200 	dwapb_write(gpio, GPIO_INT_POLARITY, pol);
201 }
202 
203 static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
204 {
205 	struct gpio_chip *gc = &gpio->ports[0].gc;
206 	unsigned long irq_status;
207 	irq_hw_number_t hwirq;
208 
209 	irq_status = dwapb_read(gpio, GPIO_INTSTATUS);
210 	for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) {
211 		int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq);
212 		u32 irq_type = irq_get_trigger_type(gpio_irq);
213 
214 		generic_handle_irq(gpio_irq);
215 
216 		if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
217 			dwapb_toggle_trigger(gpio, hwirq);
218 	}
219 
220 	return irq_status;
221 }
222 
223 static void dwapb_irq_handler(struct irq_desc *desc)
224 {
225 	struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc);
226 	struct irq_chip *chip = irq_desc_get_chip(desc);
227 
228 	chained_irq_enter(chip, desc);
229 	dwapb_do_irq(gpio);
230 	chained_irq_exit(chip, desc);
231 }
232 
233 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
234 {
235 	return IRQ_RETVAL(dwapb_do_irq(dev_id));
236 }
237 
238 static void dwapb_irq_ack(struct irq_data *d)
239 {
240 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
241 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
242 	u32 val = BIT(irqd_to_hwirq(d));
243 	unsigned long flags;
244 
245 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
246 	dwapb_write(gpio, GPIO_PORTA_EOI, val);
247 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
248 }
249 
250 static void dwapb_irq_mask(struct irq_data *d)
251 {
252 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
253 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
254 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
255 	unsigned long flags;
256 	u32 val;
257 
258 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
259 	val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
260 	dwapb_write(gpio, GPIO_INTMASK, val);
261 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
262 
263 	gpiochip_disable_irq(gc, hwirq);
264 }
265 
266 static void dwapb_irq_unmask(struct irq_data *d)
267 {
268 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
269 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
270 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
271 	unsigned long flags;
272 	u32 val;
273 
274 	gpiochip_enable_irq(gc, hwirq);
275 
276 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
277 	val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
278 	dwapb_write(gpio, GPIO_INTMASK, val);
279 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
280 }
281 
282 static void dwapb_irq_enable(struct irq_data *d)
283 {
284 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
285 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
286 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
287 	unsigned long flags;
288 	u32 val;
289 
290 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
291 	val = dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq);
292 	dwapb_write(gpio, GPIO_INTEN, val);
293 	val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq);
294 	dwapb_write(gpio, GPIO_INTMASK, val);
295 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
296 }
297 
298 static void dwapb_irq_disable(struct irq_data *d)
299 {
300 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
301 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
302 	irq_hw_number_t hwirq = irqd_to_hwirq(d);
303 	unsigned long flags;
304 	u32 val;
305 
306 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
307 	val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq);
308 	dwapb_write(gpio, GPIO_INTMASK, val);
309 	val = dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq);
310 	dwapb_write(gpio, GPIO_INTEN, val);
311 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
312 }
313 
314 static int dwapb_irq_set_type(struct irq_data *d, u32 type)
315 {
316 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
317 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
318 	irq_hw_number_t bit = irqd_to_hwirq(d);
319 	unsigned long level, polarity, flags;
320 
321 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
322 	level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
323 	polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
324 
325 	switch (type) {
326 	case IRQ_TYPE_EDGE_BOTH:
327 		level |= BIT(bit);
328 		dwapb_toggle_trigger(gpio, bit);
329 		break;
330 	case IRQ_TYPE_EDGE_RISING:
331 		level |= BIT(bit);
332 		polarity |= BIT(bit);
333 		break;
334 	case IRQ_TYPE_EDGE_FALLING:
335 		level |= BIT(bit);
336 		polarity &= ~BIT(bit);
337 		break;
338 	case IRQ_TYPE_LEVEL_HIGH:
339 		level &= ~BIT(bit);
340 		polarity |= BIT(bit);
341 		break;
342 	case IRQ_TYPE_LEVEL_LOW:
343 		level &= ~BIT(bit);
344 		polarity &= ~BIT(bit);
345 		break;
346 	}
347 
348 	if (type & IRQ_TYPE_LEVEL_MASK)
349 		irq_set_handler_locked(d, handle_level_irq);
350 	else if (type & IRQ_TYPE_EDGE_BOTH)
351 		irq_set_handler_locked(d, handle_edge_irq);
352 
353 	dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
354 	if (type != IRQ_TYPE_EDGE_BOTH)
355 		dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
356 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
357 
358 	return 0;
359 }
360 
361 #ifdef CONFIG_PM_SLEEP
362 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
363 {
364 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
365 	struct dwapb_gpio *gpio = to_dwapb_gpio(gc);
366 	struct dwapb_context *ctx = gpio->ports[0].ctx;
367 	irq_hw_number_t bit = irqd_to_hwirq(d);
368 
369 	if (enable)
370 		ctx->wake_en |= BIT(bit);
371 	else
372 		ctx->wake_en &= ~BIT(bit);
373 
374 	return 0;
375 }
376 #else
377 #define dwapb_irq_set_wake	NULL
378 #endif
379 
380 static const struct irq_chip dwapb_irq_chip = {
381 	.name		= DWAPB_DRIVER_NAME,
382 	.irq_ack	= dwapb_irq_ack,
383 	.irq_mask	= dwapb_irq_mask,
384 	.irq_unmask	= dwapb_irq_unmask,
385 	.irq_set_type	= dwapb_irq_set_type,
386 	.irq_enable	= dwapb_irq_enable,
387 	.irq_disable	= dwapb_irq_disable,
388 	.irq_set_wake	= dwapb_irq_set_wake,
389 	.flags		= IRQCHIP_IMMUTABLE,
390 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
391 };
392 
393 static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
394 				   unsigned offset, unsigned debounce)
395 {
396 	struct dwapb_gpio_port *port = gpiochip_get_data(gc);
397 	struct dwapb_gpio *gpio = port->gpio;
398 	unsigned long flags, val_deb;
399 	unsigned long mask = BIT(offset);
400 
401 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
402 
403 	val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
404 	if (debounce)
405 		val_deb |= mask;
406 	else
407 		val_deb &= ~mask;
408 	dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb);
409 
410 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
411 
412 	return 0;
413 }
414 
415 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset,
416 				 unsigned long config)
417 {
418 	u32 debounce;
419 
420 	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
421 		return -ENOTSUPP;
422 
423 	debounce = pinconf_to_config_argument(config);
424 	return dwapb_gpio_set_debounce(gc, offset, debounce);
425 }
426 
427 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq,
428 			      struct dwapb_port_property *pp)
429 {
430 	int i;
431 
432 	/* Group all available IRQs into an array of parental IRQs. */
433 	for (i = 0; i < pp->ngpio; ++i) {
434 		if (!pp->irq[i])
435 			continue;
436 
437 		pirq->irq[pirq->nr_irqs++] = pp->irq[i];
438 	}
439 
440 	return pirq->nr_irqs ? 0 : -ENOENT;
441 }
442 
443 static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
444 				 struct dwapb_gpio_port *port,
445 				 struct dwapb_port_property *pp)
446 {
447 	struct dwapb_gpio_port_irqchip *pirq;
448 	struct gpio_chip *gc = &port->gc;
449 	struct gpio_irq_chip *girq;
450 	int err;
451 
452 	pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL);
453 	if (!pirq)
454 		return;
455 
456 	if (dwapb_convert_irqs(pirq, pp)) {
457 		dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx);
458 		goto err_kfree_pirq;
459 	}
460 
461 	girq = &gc->irq;
462 	girq->handler = handle_bad_irq;
463 	girq->default_type = IRQ_TYPE_NONE;
464 
465 	port->pirq = pirq;
466 
467 	/*
468 	 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO
469 	 * IRQ lane shared between several devices. In that case the parental
470 	 * IRQ has to be handled in the shared way so to be properly delivered
471 	 * to all the connected devices.
472 	 */
473 	if (has_acpi_companion(gpio->dev)) {
474 		girq->num_parents = 0;
475 		girq->parents = NULL;
476 		girq->parent_handler = NULL;
477 
478 		err = devm_request_irq(gpio->dev, pp->irq[0],
479 				       dwapb_irq_handler_mfd,
480 				       IRQF_SHARED, DWAPB_DRIVER_NAME, gpio);
481 		if (err) {
482 			dev_err(gpio->dev, "error requesting IRQ\n");
483 			goto err_kfree_pirq;
484 		}
485 	} else {
486 		girq->num_parents = pirq->nr_irqs;
487 		girq->parents = pirq->irq;
488 		girq->parent_handler_data = gpio;
489 		girq->parent_handler = dwapb_irq_handler;
490 	}
491 
492 	gpio_irq_chip_set_chip(girq, &dwapb_irq_chip);
493 
494 	return;
495 
496 err_kfree_pirq:
497 	devm_kfree(gpio->dev, pirq);
498 }
499 
500 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
501 			       struct dwapb_port_property *pp,
502 			       unsigned int offs)
503 {
504 	struct dwapb_gpio_port *port;
505 	void __iomem *dat, *set, *dirout;
506 	int err;
507 
508 	port = &gpio->ports[offs];
509 	port->gpio = gpio;
510 	port->idx = pp->idx;
511 
512 #ifdef CONFIG_PM_SLEEP
513 	port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
514 	if (!port->ctx)
515 		return -ENOMEM;
516 #endif
517 
518 	dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE;
519 	set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE;
520 	dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE;
521 
522 	/* This registers 32 GPIO lines per port */
523 	err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout,
524 			 NULL, 0);
525 	if (err) {
526 		dev_err(gpio->dev, "failed to init gpio chip for port%d\n",
527 			port->idx);
528 		return err;
529 	}
530 
531 	port->gc.fwnode = pp->fwnode;
532 	port->gc.ngpio = pp->ngpio;
533 	port->gc.base = pp->gpio_base;
534 
535 	/* Only port A support debounce */
536 	if (pp->idx == 0)
537 		port->gc.set_config = dwapb_gpio_set_config;
538 
539 	/* Only port A can provide interrupts in all configurations of the IP */
540 	if (pp->idx == 0)
541 		dwapb_configure_irqs(gpio, port, pp);
542 
543 	err = devm_gpiochip_add_data(gpio->dev, &port->gc, port);
544 	if (err) {
545 		dev_err(gpio->dev, "failed to register gpiochip for port%d\n",
546 			port->idx);
547 		return err;
548 	}
549 
550 	return 0;
551 }
552 
553 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode,
554 			  struct dwapb_port_property *pp)
555 {
556 	int irq, j;
557 
558 	for (j = 0; j < pp->ngpio; j++) {
559 		if (has_acpi_companion(dev))
560 			irq = platform_get_irq_optional(to_platform_device(dev), j);
561 		else
562 			irq = fwnode_irq_get(fwnode, j);
563 		if (irq > 0)
564 			pp->irq[j] = irq;
565 	}
566 }
567 
568 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev)
569 {
570 	struct fwnode_handle *fwnode;
571 	struct dwapb_platform_data *pdata;
572 	struct dwapb_port_property *pp;
573 	int nports;
574 	int i;
575 
576 	nports = device_get_child_node_count(dev);
577 	if (nports == 0)
578 		return ERR_PTR(-ENODEV);
579 
580 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
581 	if (!pdata)
582 		return ERR_PTR(-ENOMEM);
583 
584 	pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL);
585 	if (!pdata->properties)
586 		return ERR_PTR(-ENOMEM);
587 
588 	pdata->nports = nports;
589 
590 	i = 0;
591 	device_for_each_child_node(dev, fwnode)  {
592 		pp = &pdata->properties[i++];
593 		pp->fwnode = fwnode;
594 
595 		if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) ||
596 		    pp->idx >= DWAPB_MAX_PORTS) {
597 			dev_err(dev,
598 				"missing/invalid port index for port%d\n", i);
599 			fwnode_handle_put(fwnode);
600 			return ERR_PTR(-EINVAL);
601 		}
602 
603 		if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) &&
604 		    fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) {
605 			dev_info(dev,
606 				 "failed to get number of gpios for port%d\n",
607 				 i);
608 			pp->ngpio = DWAPB_MAX_GPIOS;
609 		}
610 
611 		pp->gpio_base	= -1;
612 
613 		/* For internal use only, new platforms mustn't exercise this */
614 		if (is_software_node(fwnode))
615 			fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base);
616 
617 		/*
618 		 * Only port A can provide interrupts in all configurations of
619 		 * the IP.
620 		 */
621 		if (pp->idx == 0)
622 			dwapb_get_irq(dev, fwnode, pp);
623 	}
624 
625 	return pdata;
626 }
627 
628 static void dwapb_assert_reset(void *data)
629 {
630 	struct dwapb_gpio *gpio = data;
631 
632 	reset_control_assert(gpio->rst);
633 }
634 
635 static int dwapb_get_reset(struct dwapb_gpio *gpio)
636 {
637 	int err;
638 
639 	gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL);
640 	if (IS_ERR(gpio->rst))
641 		return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst),
642 				     "Cannot get reset descriptor\n");
643 
644 	err = reset_control_deassert(gpio->rst);
645 	if (err) {
646 		dev_err(gpio->dev, "Cannot deassert reset lane\n");
647 		return err;
648 	}
649 
650 	return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio);
651 }
652 
653 static void dwapb_disable_clks(void *data)
654 {
655 	struct dwapb_gpio *gpio = data;
656 
657 	clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
658 }
659 
660 static int dwapb_get_clks(struct dwapb_gpio *gpio)
661 {
662 	int err;
663 
664 	/* Optional bus and debounce clocks */
665 	gpio->clks[0].id = "bus";
666 	gpio->clks[1].id = "db";
667 	err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS,
668 					 gpio->clks);
669 	if (err)
670 		return dev_err_probe(gpio->dev, err,
671 				     "Cannot get APB/Debounce clocks\n");
672 
673 	err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
674 	if (err) {
675 		dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n");
676 		return err;
677 	}
678 
679 	return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio);
680 }
681 
682 static const struct of_device_id dwapb_of_match[] = {
683 	{ .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1},
684 	{ .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2},
685 	{ /* Sentinel */ }
686 };
687 MODULE_DEVICE_TABLE(of, dwapb_of_match);
688 
689 static const struct acpi_device_id dwapb_acpi_match[] = {
690 	{"HISI0181", GPIO_REG_OFFSET_V1},
691 	{"APMC0D07", GPIO_REG_OFFSET_V1},
692 	{"APMC0D81", GPIO_REG_OFFSET_V2},
693 	{ }
694 };
695 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match);
696 
697 static int dwapb_gpio_probe(struct platform_device *pdev)
698 {
699 	unsigned int i;
700 	struct dwapb_gpio *gpio;
701 	int err;
702 	struct dwapb_platform_data *pdata;
703 	struct device *dev = &pdev->dev;
704 
705 	pdata = dwapb_gpio_get_pdata(dev);
706 	if (IS_ERR(pdata))
707 		return PTR_ERR(pdata);
708 
709 	gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
710 	if (!gpio)
711 		return -ENOMEM;
712 
713 	gpio->dev = &pdev->dev;
714 	gpio->nr_ports = pdata->nports;
715 
716 	err = dwapb_get_reset(gpio);
717 	if (err)
718 		return err;
719 
720 	gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
721 				   sizeof(*gpio->ports), GFP_KERNEL);
722 	if (!gpio->ports)
723 		return -ENOMEM;
724 
725 	gpio->regs = devm_platform_ioremap_resource(pdev, 0);
726 	if (IS_ERR(gpio->regs))
727 		return PTR_ERR(gpio->regs);
728 
729 	err = dwapb_get_clks(gpio);
730 	if (err)
731 		return err;
732 
733 	gpio->flags = (uintptr_t)device_get_match_data(dev);
734 
735 	for (i = 0; i < gpio->nr_ports; i++) {
736 		err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
737 		if (err)
738 			return err;
739 	}
740 
741 	platform_set_drvdata(pdev, gpio);
742 
743 	return 0;
744 }
745 
746 #ifdef CONFIG_PM_SLEEP
747 static int dwapb_gpio_suspend(struct device *dev)
748 {
749 	struct dwapb_gpio *gpio = dev_get_drvdata(dev);
750 	struct gpio_chip *gc	= &gpio->ports[0].gc;
751 	unsigned long flags;
752 	int i;
753 
754 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
755 	for (i = 0; i < gpio->nr_ports; i++) {
756 		unsigned int offset;
757 		unsigned int idx = gpio->ports[i].idx;
758 		struct dwapb_context *ctx = gpio->ports[i].ctx;
759 
760 		offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
761 		ctx->dir = dwapb_read(gpio, offset);
762 
763 		offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
764 		ctx->data = dwapb_read(gpio, offset);
765 
766 		offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
767 		ctx->ext = dwapb_read(gpio, offset);
768 
769 		/* Only port A can provide interrupts */
770 		if (idx == 0) {
771 			ctx->int_mask	= dwapb_read(gpio, GPIO_INTMASK);
772 			ctx->int_en	= dwapb_read(gpio, GPIO_INTEN);
773 			ctx->int_pol	= dwapb_read(gpio, GPIO_INT_POLARITY);
774 			ctx->int_type	= dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
775 			ctx->int_deb	= dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
776 
777 			/* Mask out interrupts */
778 			dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en);
779 		}
780 	}
781 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
782 
783 	clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks);
784 
785 	return 0;
786 }
787 
788 static int dwapb_gpio_resume(struct device *dev)
789 {
790 	struct dwapb_gpio *gpio = dev_get_drvdata(dev);
791 	struct gpio_chip *gc	= &gpio->ports[0].gc;
792 	unsigned long flags;
793 	int i, err;
794 
795 	err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks);
796 	if (err) {
797 		dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n");
798 		return err;
799 	}
800 
801 	raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
802 	for (i = 0; i < gpio->nr_ports; i++) {
803 		unsigned int offset;
804 		unsigned int idx = gpio->ports[i].idx;
805 		struct dwapb_context *ctx = gpio->ports[i].ctx;
806 
807 		offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE;
808 		dwapb_write(gpio, offset, ctx->data);
809 
810 		offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE;
811 		dwapb_write(gpio, offset, ctx->dir);
812 
813 		offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE;
814 		dwapb_write(gpio, offset, ctx->ext);
815 
816 		/* Only port A can provide interrupts */
817 		if (idx == 0) {
818 			dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
819 			dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
820 			dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
821 			dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
822 			dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
823 
824 			/* Clear out spurious interrupts */
825 			dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
826 		}
827 	}
828 	raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
829 
830 	return 0;
831 }
832 #endif
833 
834 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
835 			 dwapb_gpio_resume);
836 
837 static struct platform_driver dwapb_gpio_driver = {
838 	.driver		= {
839 		.name	= DWAPB_DRIVER_NAME,
840 		.pm	= &dwapb_gpio_pm_ops,
841 		.of_match_table = dwapb_of_match,
842 		.acpi_match_table = dwapb_acpi_match,
843 	},
844 	.probe		= dwapb_gpio_probe,
845 };
846 
847 module_platform_driver(dwapb_gpio_driver);
848 
849 MODULE_LICENSE("GPL");
850 MODULE_AUTHOR("Jamie Iles");
851 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
852 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME);
853