1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2011 Jamie Iles 4 * 5 * All enquiries to support@picochip.com 6 */ 7 #include <linux/acpi.h> 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/irq.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 #include <linux/spinlock.h> 23 24 #include "gpiolib.h" 25 #include "gpiolib-acpi.h" 26 27 #define GPIO_SWPORTA_DR 0x00 28 #define GPIO_SWPORTA_DDR 0x04 29 #define GPIO_SWPORTB_DR 0x0c 30 #define GPIO_SWPORTB_DDR 0x10 31 #define GPIO_SWPORTC_DR 0x18 32 #define GPIO_SWPORTC_DDR 0x1c 33 #define GPIO_SWPORTD_DR 0x24 34 #define GPIO_SWPORTD_DDR 0x28 35 #define GPIO_INTEN 0x30 36 #define GPIO_INTMASK 0x34 37 #define GPIO_INTTYPE_LEVEL 0x38 38 #define GPIO_INT_POLARITY 0x3c 39 #define GPIO_INTSTATUS 0x40 40 #define GPIO_PORTA_DEBOUNCE 0x48 41 #define GPIO_PORTA_EOI 0x4c 42 #define GPIO_EXT_PORTA 0x50 43 #define GPIO_EXT_PORTB 0x54 44 #define GPIO_EXT_PORTC 0x58 45 #define GPIO_EXT_PORTD 0x5c 46 47 #define DWAPB_DRIVER_NAME "gpio-dwapb" 48 #define DWAPB_MAX_PORTS 4 49 #define DWAPB_MAX_GPIOS 32 50 51 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */ 52 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */ 53 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */ 54 55 #define GPIO_REG_OFFSET_V1 0 56 #define GPIO_REG_OFFSET_V2 1 57 #define GPIO_REG_OFFSET_MASK BIT(0) 58 59 #define GPIO_INTMASK_V2 0x44 60 #define GPIO_INTTYPE_LEVEL_V2 0x34 61 #define GPIO_INT_POLARITY_V2 0x38 62 #define GPIO_INTSTATUS_V2 0x3c 63 #define GPIO_PORTA_EOI_V2 0x40 64 65 #define DWAPB_NR_CLOCKS 2 66 67 struct dwapb_gpio; 68 69 struct dwapb_port_property { 70 struct fwnode_handle *fwnode; 71 unsigned int idx; 72 unsigned int ngpio; 73 unsigned int gpio_base; 74 int irq[DWAPB_MAX_GPIOS]; 75 }; 76 77 struct dwapb_platform_data { 78 struct dwapb_port_property *properties; 79 unsigned int nports; 80 }; 81 82 #ifdef CONFIG_PM_SLEEP 83 /* Store GPIO context across system-wide suspend/resume transitions */ 84 struct dwapb_context { 85 u32 data; 86 u32 dir; 87 u32 ext; 88 u32 int_en; 89 u32 int_mask; 90 u32 int_type; 91 u32 int_pol; 92 u32 int_deb; 93 u32 wake_en; 94 }; 95 #endif 96 97 struct dwapb_gpio_port_irqchip { 98 unsigned int nr_irqs; 99 unsigned int irq[DWAPB_MAX_GPIOS]; 100 }; 101 102 struct dwapb_gpio_port { 103 struct gpio_chip gc; 104 struct dwapb_gpio_port_irqchip *pirq; 105 struct dwapb_gpio *gpio; 106 #ifdef CONFIG_PM_SLEEP 107 struct dwapb_context *ctx; 108 #endif 109 unsigned int idx; 110 }; 111 #define to_dwapb_gpio(_gc) \ 112 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio) 113 114 struct dwapb_gpio { 115 struct device *dev; 116 void __iomem *regs; 117 struct dwapb_gpio_port *ports; 118 unsigned int nr_ports; 119 unsigned int flags; 120 struct reset_control *rst; 121 struct clk_bulk_data clks[DWAPB_NR_CLOCKS]; 122 }; 123 124 static inline u32 gpio_reg_v2_convert(unsigned int offset) 125 { 126 switch (offset) { 127 case GPIO_INTMASK: 128 return GPIO_INTMASK_V2; 129 case GPIO_INTTYPE_LEVEL: 130 return GPIO_INTTYPE_LEVEL_V2; 131 case GPIO_INT_POLARITY: 132 return GPIO_INT_POLARITY_V2; 133 case GPIO_INTSTATUS: 134 return GPIO_INTSTATUS_V2; 135 case GPIO_PORTA_EOI: 136 return GPIO_PORTA_EOI_V2; 137 } 138 139 return offset; 140 } 141 142 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) 143 { 144 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2) 145 return gpio_reg_v2_convert(offset); 146 147 return offset; 148 } 149 150 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) 151 { 152 struct gpio_chip *gc = &gpio->ports[0].gc; 153 void __iomem *reg_base = gpio->regs; 154 155 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); 156 } 157 158 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, 159 u32 val) 160 { 161 struct gpio_chip *gc = &gpio->ports[0].gc; 162 void __iomem *reg_base = gpio->regs; 163 164 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); 165 } 166 167 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) 168 { 169 struct dwapb_gpio_port *port; 170 int i; 171 172 for (i = 0; i < gpio->nr_ports; i++) { 173 port = &gpio->ports[i]; 174 if (port->idx == offs / DWAPB_MAX_GPIOS) 175 return port; 176 } 177 178 return NULL; 179 } 180 181 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) 182 { 183 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); 184 struct gpio_chip *gc; 185 u32 pol; 186 int val; 187 188 if (!port) 189 return; 190 gc = &port->gc; 191 192 pol = dwapb_read(gpio, GPIO_INT_POLARITY); 193 /* Just read the current value right out of the data register */ 194 val = gc->get(gc, offs % DWAPB_MAX_GPIOS); 195 if (val) 196 pol &= ~BIT(offs); 197 else 198 pol |= BIT(offs); 199 200 dwapb_write(gpio, GPIO_INT_POLARITY, pol); 201 } 202 203 static u32 dwapb_do_irq(struct dwapb_gpio *gpio) 204 { 205 struct gpio_chip *gc = &gpio->ports[0].gc; 206 unsigned long irq_status; 207 irq_hw_number_t hwirq; 208 209 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); 210 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) { 211 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq); 212 u32 irq_type = irq_get_trigger_type(gpio_irq); 213 214 generic_handle_irq(gpio_irq); 215 216 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 217 dwapb_toggle_trigger(gpio, hwirq); 218 } 219 220 return irq_status; 221 } 222 223 static void dwapb_irq_handler(struct irq_desc *desc) 224 { 225 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); 226 struct irq_chip *chip = irq_desc_get_chip(desc); 227 228 chained_irq_enter(chip, desc); 229 dwapb_do_irq(gpio); 230 chained_irq_exit(chip, desc); 231 } 232 233 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) 234 { 235 return IRQ_RETVAL(dwapb_do_irq(dev_id)); 236 } 237 238 static void dwapb_irq_ack(struct irq_data *d) 239 { 240 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 241 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 242 u32 val = BIT(irqd_to_hwirq(d)); 243 unsigned long flags; 244 245 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 246 dwapb_write(gpio, GPIO_PORTA_EOI, val); 247 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 248 } 249 250 static void dwapb_irq_mask(struct irq_data *d) 251 { 252 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 253 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 254 irq_hw_number_t hwirq = irqd_to_hwirq(d); 255 unsigned long flags; 256 u32 val; 257 258 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 259 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); 260 dwapb_write(gpio, GPIO_INTMASK, val); 261 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 262 263 gpiochip_disable_irq(gc, hwirq); 264 } 265 266 static void dwapb_irq_unmask(struct irq_data *d) 267 { 268 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 269 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 270 irq_hw_number_t hwirq = irqd_to_hwirq(d); 271 unsigned long flags; 272 u32 val; 273 274 gpiochip_enable_irq(gc, hwirq); 275 276 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 277 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); 278 dwapb_write(gpio, GPIO_INTMASK, val); 279 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 280 } 281 282 static void dwapb_irq_enable(struct irq_data *d) 283 { 284 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 285 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 286 unsigned long flags; 287 u32 val; 288 289 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 290 val = dwapb_read(gpio, GPIO_INTEN); 291 val |= BIT(irqd_to_hwirq(d)); 292 dwapb_write(gpio, GPIO_INTEN, val); 293 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 294 } 295 296 static void dwapb_irq_disable(struct irq_data *d) 297 { 298 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 299 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 300 unsigned long flags; 301 u32 val; 302 303 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 304 val = dwapb_read(gpio, GPIO_INTEN); 305 val &= ~BIT(irqd_to_hwirq(d)); 306 dwapb_write(gpio, GPIO_INTEN, val); 307 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 308 } 309 310 static int dwapb_irq_set_type(struct irq_data *d, u32 type) 311 { 312 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 313 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 314 irq_hw_number_t bit = irqd_to_hwirq(d); 315 unsigned long level, polarity, flags; 316 317 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 318 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 319 polarity = dwapb_read(gpio, GPIO_INT_POLARITY); 320 321 switch (type) { 322 case IRQ_TYPE_EDGE_BOTH: 323 level |= BIT(bit); 324 dwapb_toggle_trigger(gpio, bit); 325 break; 326 case IRQ_TYPE_EDGE_RISING: 327 level |= BIT(bit); 328 polarity |= BIT(bit); 329 break; 330 case IRQ_TYPE_EDGE_FALLING: 331 level |= BIT(bit); 332 polarity &= ~BIT(bit); 333 break; 334 case IRQ_TYPE_LEVEL_HIGH: 335 level &= ~BIT(bit); 336 polarity |= BIT(bit); 337 break; 338 case IRQ_TYPE_LEVEL_LOW: 339 level &= ~BIT(bit); 340 polarity &= ~BIT(bit); 341 break; 342 } 343 344 if (type & IRQ_TYPE_LEVEL_MASK) 345 irq_set_handler_locked(d, handle_level_irq); 346 else if (type & IRQ_TYPE_EDGE_BOTH) 347 irq_set_handler_locked(d, handle_edge_irq); 348 349 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); 350 if (type != IRQ_TYPE_EDGE_BOTH) 351 dwapb_write(gpio, GPIO_INT_POLARITY, polarity); 352 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 353 354 return 0; 355 } 356 357 #ifdef CONFIG_PM_SLEEP 358 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable) 359 { 360 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 361 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 362 struct dwapb_context *ctx = gpio->ports[0].ctx; 363 irq_hw_number_t bit = irqd_to_hwirq(d); 364 365 if (enable) 366 ctx->wake_en |= BIT(bit); 367 else 368 ctx->wake_en &= ~BIT(bit); 369 370 return 0; 371 } 372 #else 373 #define dwapb_irq_set_wake NULL 374 #endif 375 376 static const struct irq_chip dwapb_irq_chip = { 377 .name = DWAPB_DRIVER_NAME, 378 .irq_ack = dwapb_irq_ack, 379 .irq_mask = dwapb_irq_mask, 380 .irq_unmask = dwapb_irq_unmask, 381 .irq_set_type = dwapb_irq_set_type, 382 .irq_enable = dwapb_irq_enable, 383 .irq_disable = dwapb_irq_disable, 384 .irq_set_wake = dwapb_irq_set_wake, 385 .flags = IRQCHIP_IMMUTABLE, 386 GPIOCHIP_IRQ_RESOURCE_HELPERS, 387 }; 388 389 static int dwapb_gpio_set_debounce(struct gpio_chip *gc, 390 unsigned offset, unsigned debounce) 391 { 392 struct dwapb_gpio_port *port = gpiochip_get_data(gc); 393 struct dwapb_gpio *gpio = port->gpio; 394 unsigned long flags, val_deb; 395 unsigned long mask = BIT(offset); 396 397 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 398 399 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 400 if (debounce) 401 val_deb |= mask; 402 else 403 val_deb &= ~mask; 404 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); 405 406 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 407 408 return 0; 409 } 410 411 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, 412 unsigned long config) 413 { 414 u32 debounce; 415 416 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 417 return -ENOTSUPP; 418 419 debounce = pinconf_to_config_argument(config); 420 return dwapb_gpio_set_debounce(gc, offset, debounce); 421 } 422 423 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq, 424 struct dwapb_port_property *pp) 425 { 426 int i; 427 428 /* Group all available IRQs into an array of parental IRQs. */ 429 for (i = 0; i < pp->ngpio; ++i) { 430 if (!pp->irq[i]) 431 continue; 432 433 pirq->irq[pirq->nr_irqs++] = pp->irq[i]; 434 } 435 436 return pirq->nr_irqs ? 0 : -ENOENT; 437 } 438 439 static void dwapb_configure_irqs(struct dwapb_gpio *gpio, 440 struct dwapb_gpio_port *port, 441 struct dwapb_port_property *pp) 442 { 443 struct dwapb_gpio_port_irqchip *pirq; 444 struct gpio_chip *gc = &port->gc; 445 struct gpio_irq_chip *girq; 446 int err; 447 448 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL); 449 if (!pirq) 450 return; 451 452 if (dwapb_convert_irqs(pirq, pp)) { 453 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx); 454 goto err_kfree_pirq; 455 } 456 457 girq = &gc->irq; 458 girq->handler = handle_bad_irq; 459 girq->default_type = IRQ_TYPE_NONE; 460 461 port->pirq = pirq; 462 463 /* 464 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO 465 * IRQ lane shared between several devices. In that case the parental 466 * IRQ has to be handled in the shared way so to be properly delivered 467 * to all the connected devices. 468 */ 469 if (has_acpi_companion(gpio->dev)) { 470 girq->num_parents = 0; 471 girq->parents = NULL; 472 girq->parent_handler = NULL; 473 474 err = devm_request_irq(gpio->dev, pp->irq[0], 475 dwapb_irq_handler_mfd, 476 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio); 477 if (err) { 478 dev_err(gpio->dev, "error requesting IRQ\n"); 479 goto err_kfree_pirq; 480 } 481 } else { 482 girq->num_parents = pirq->nr_irqs; 483 girq->parents = pirq->irq; 484 girq->parent_handler_data = gpio; 485 girq->parent_handler = dwapb_irq_handler; 486 } 487 488 gpio_irq_chip_set_chip(girq, &dwapb_irq_chip); 489 490 return; 491 492 err_kfree_pirq: 493 devm_kfree(gpio->dev, pirq); 494 } 495 496 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, 497 struct dwapb_port_property *pp, 498 unsigned int offs) 499 { 500 struct dwapb_gpio_port *port; 501 void __iomem *dat, *set, *dirout; 502 int err; 503 504 port = &gpio->ports[offs]; 505 port->gpio = gpio; 506 port->idx = pp->idx; 507 508 #ifdef CONFIG_PM_SLEEP 509 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); 510 if (!port->ctx) 511 return -ENOMEM; 512 #endif 513 514 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE; 515 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; 516 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE; 517 518 /* This registers 32 GPIO lines per port */ 519 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, 520 NULL, 0); 521 if (err) { 522 dev_err(gpio->dev, "failed to init gpio chip for port%d\n", 523 port->idx); 524 return err; 525 } 526 527 port->gc.fwnode = pp->fwnode; 528 port->gc.ngpio = pp->ngpio; 529 port->gc.base = pp->gpio_base; 530 531 /* Only port A support debounce */ 532 if (pp->idx == 0) 533 port->gc.set_config = dwapb_gpio_set_config; 534 535 /* Only port A can provide interrupts in all configurations of the IP */ 536 if (pp->idx == 0) 537 dwapb_configure_irqs(gpio, port, pp); 538 539 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port); 540 if (err) { 541 dev_err(gpio->dev, "failed to register gpiochip for port%d\n", 542 port->idx); 543 return err; 544 } 545 546 return 0; 547 } 548 549 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode, 550 struct dwapb_port_property *pp) 551 { 552 int irq, j; 553 554 for (j = 0; j < pp->ngpio; j++) { 555 if (has_acpi_companion(dev)) 556 irq = platform_get_irq_optional(to_platform_device(dev), j); 557 else 558 irq = fwnode_irq_get(fwnode, j); 559 if (irq > 0) 560 pp->irq[j] = irq; 561 } 562 } 563 564 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev) 565 { 566 struct fwnode_handle *fwnode; 567 struct dwapb_platform_data *pdata; 568 struct dwapb_port_property *pp; 569 int nports; 570 int i; 571 572 nports = device_get_child_node_count(dev); 573 if (nports == 0) 574 return ERR_PTR(-ENODEV); 575 576 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 577 if (!pdata) 578 return ERR_PTR(-ENOMEM); 579 580 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); 581 if (!pdata->properties) 582 return ERR_PTR(-ENOMEM); 583 584 pdata->nports = nports; 585 586 i = 0; 587 device_for_each_child_node(dev, fwnode) { 588 pp = &pdata->properties[i++]; 589 pp->fwnode = fwnode; 590 591 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || 592 pp->idx >= DWAPB_MAX_PORTS) { 593 dev_err(dev, 594 "missing/invalid port index for port%d\n", i); 595 fwnode_handle_put(fwnode); 596 return ERR_PTR(-EINVAL); 597 } 598 599 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) && 600 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) { 601 dev_info(dev, 602 "failed to get number of gpios for port%d\n", 603 i); 604 pp->ngpio = DWAPB_MAX_GPIOS; 605 } 606 607 pp->gpio_base = -1; 608 609 /* For internal use only, new platforms mustn't exercise this */ 610 if (is_software_node(fwnode)) 611 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base); 612 613 /* 614 * Only port A can provide interrupts in all configurations of 615 * the IP. 616 */ 617 if (pp->idx == 0) 618 dwapb_get_irq(dev, fwnode, pp); 619 } 620 621 return pdata; 622 } 623 624 static void dwapb_assert_reset(void *data) 625 { 626 struct dwapb_gpio *gpio = data; 627 628 reset_control_assert(gpio->rst); 629 } 630 631 static int dwapb_get_reset(struct dwapb_gpio *gpio) 632 { 633 int err; 634 635 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL); 636 if (IS_ERR(gpio->rst)) 637 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst), 638 "Cannot get reset descriptor\n"); 639 640 err = reset_control_deassert(gpio->rst); 641 if (err) { 642 dev_err(gpio->dev, "Cannot deassert reset lane\n"); 643 return err; 644 } 645 646 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio); 647 } 648 649 static void dwapb_disable_clks(void *data) 650 { 651 struct dwapb_gpio *gpio = data; 652 653 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); 654 } 655 656 static int dwapb_get_clks(struct dwapb_gpio *gpio) 657 { 658 int err; 659 660 /* Optional bus and debounce clocks */ 661 gpio->clks[0].id = "bus"; 662 gpio->clks[1].id = "db"; 663 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS, 664 gpio->clks); 665 if (err) 666 return dev_err_probe(gpio->dev, err, 667 "Cannot get APB/Debounce clocks\n"); 668 669 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); 670 if (err) { 671 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n"); 672 return err; 673 } 674 675 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio); 676 } 677 678 static const struct of_device_id dwapb_of_match[] = { 679 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1}, 680 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2}, 681 { /* Sentinel */ } 682 }; 683 MODULE_DEVICE_TABLE(of, dwapb_of_match); 684 685 static const struct acpi_device_id dwapb_acpi_match[] = { 686 {"HISI0181", GPIO_REG_OFFSET_V1}, 687 {"APMC0D07", GPIO_REG_OFFSET_V1}, 688 {"APMC0D81", GPIO_REG_OFFSET_V2}, 689 { } 690 }; 691 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); 692 693 static int dwapb_gpio_probe(struct platform_device *pdev) 694 { 695 unsigned int i; 696 struct dwapb_gpio *gpio; 697 int err; 698 struct dwapb_platform_data *pdata; 699 struct device *dev = &pdev->dev; 700 701 pdata = dwapb_gpio_get_pdata(dev); 702 if (IS_ERR(pdata)) 703 return PTR_ERR(pdata); 704 705 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 706 if (!gpio) 707 return -ENOMEM; 708 709 gpio->dev = &pdev->dev; 710 gpio->nr_ports = pdata->nports; 711 712 err = dwapb_get_reset(gpio); 713 if (err) 714 return err; 715 716 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, 717 sizeof(*gpio->ports), GFP_KERNEL); 718 if (!gpio->ports) 719 return -ENOMEM; 720 721 gpio->regs = devm_platform_ioremap_resource(pdev, 0); 722 if (IS_ERR(gpio->regs)) 723 return PTR_ERR(gpio->regs); 724 725 err = dwapb_get_clks(gpio); 726 if (err) 727 return err; 728 729 gpio->flags = (uintptr_t)device_get_match_data(dev); 730 731 for (i = 0; i < gpio->nr_ports; i++) { 732 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); 733 if (err) 734 return err; 735 } 736 737 platform_set_drvdata(pdev, gpio); 738 739 return 0; 740 } 741 742 #ifdef CONFIG_PM_SLEEP 743 static int dwapb_gpio_suspend(struct device *dev) 744 { 745 struct dwapb_gpio *gpio = dev_get_drvdata(dev); 746 struct gpio_chip *gc = &gpio->ports[0].gc; 747 unsigned long flags; 748 int i; 749 750 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 751 for (i = 0; i < gpio->nr_ports; i++) { 752 unsigned int offset; 753 unsigned int idx = gpio->ports[i].idx; 754 struct dwapb_context *ctx = gpio->ports[i].ctx; 755 756 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 757 ctx->dir = dwapb_read(gpio, offset); 758 759 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 760 ctx->data = dwapb_read(gpio, offset); 761 762 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 763 ctx->ext = dwapb_read(gpio, offset); 764 765 /* Only port A can provide interrupts */ 766 if (idx == 0) { 767 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); 768 ctx->int_en = dwapb_read(gpio, GPIO_INTEN); 769 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); 770 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 771 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 772 773 /* Mask out interrupts */ 774 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); 775 } 776 } 777 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 778 779 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); 780 781 return 0; 782 } 783 784 static int dwapb_gpio_resume(struct device *dev) 785 { 786 struct dwapb_gpio *gpio = dev_get_drvdata(dev); 787 struct gpio_chip *gc = &gpio->ports[0].gc; 788 unsigned long flags; 789 int i, err; 790 791 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); 792 if (err) { 793 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n"); 794 return err; 795 } 796 797 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 798 for (i = 0; i < gpio->nr_ports; i++) { 799 unsigned int offset; 800 unsigned int idx = gpio->ports[i].idx; 801 struct dwapb_context *ctx = gpio->ports[i].ctx; 802 803 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 804 dwapb_write(gpio, offset, ctx->data); 805 806 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 807 dwapb_write(gpio, offset, ctx->dir); 808 809 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 810 dwapb_write(gpio, offset, ctx->ext); 811 812 /* Only port A can provide interrupts */ 813 if (idx == 0) { 814 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); 815 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); 816 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); 817 dwapb_write(gpio, GPIO_INTEN, ctx->int_en); 818 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); 819 820 /* Clear out spurious interrupts */ 821 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); 822 } 823 } 824 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 825 826 return 0; 827 } 828 #endif 829 830 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, 831 dwapb_gpio_resume); 832 833 static struct platform_driver dwapb_gpio_driver = { 834 .driver = { 835 .name = DWAPB_DRIVER_NAME, 836 .pm = &dwapb_gpio_pm_ops, 837 .of_match_table = dwapb_of_match, 838 .acpi_match_table = dwapb_acpi_match, 839 }, 840 .probe = dwapb_gpio_probe, 841 }; 842 843 module_platform_driver(dwapb_gpio_driver); 844 845 MODULE_LICENSE("GPL"); 846 MODULE_AUTHOR("Jamie Iles"); 847 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); 848 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME); 849