1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2011 Jamie Iles 4 * 5 * All enquiries to support@picochip.com 6 */ 7 #include <linux/acpi.h> 8 #include <linux/clk.h> 9 #include <linux/err.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/ioport.h> 15 #include <linux/irq.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 #include <linux/spinlock.h> 23 24 #include "gpiolib.h" 25 #include "gpiolib-acpi.h" 26 27 #define GPIO_SWPORTA_DR 0x00 28 #define GPIO_SWPORTA_DDR 0x04 29 #define GPIO_SWPORTB_DR 0x0c 30 #define GPIO_SWPORTB_DDR 0x10 31 #define GPIO_SWPORTC_DR 0x18 32 #define GPIO_SWPORTC_DDR 0x1c 33 #define GPIO_SWPORTD_DR 0x24 34 #define GPIO_SWPORTD_DDR 0x28 35 #define GPIO_INTEN 0x30 36 #define GPIO_INTMASK 0x34 37 #define GPIO_INTTYPE_LEVEL 0x38 38 #define GPIO_INT_POLARITY 0x3c 39 #define GPIO_INTSTATUS 0x40 40 #define GPIO_PORTA_DEBOUNCE 0x48 41 #define GPIO_PORTA_EOI 0x4c 42 #define GPIO_EXT_PORTA 0x50 43 #define GPIO_EXT_PORTB 0x54 44 #define GPIO_EXT_PORTC 0x58 45 #define GPIO_EXT_PORTD 0x5c 46 47 #define DWAPB_DRIVER_NAME "gpio-dwapb" 48 #define DWAPB_MAX_PORTS 4 49 #define DWAPB_MAX_GPIOS 32 50 51 #define GPIO_EXT_PORT_STRIDE 0x04 /* register stride 32 bits */ 52 #define GPIO_SWPORT_DR_STRIDE 0x0c /* register stride 3*32 bits */ 53 #define GPIO_SWPORT_DDR_STRIDE 0x0c /* register stride 3*32 bits */ 54 55 #define GPIO_REG_OFFSET_V1 0 56 #define GPIO_REG_OFFSET_V2 1 57 #define GPIO_REG_OFFSET_MASK BIT(0) 58 59 #define GPIO_INTMASK_V2 0x44 60 #define GPIO_INTTYPE_LEVEL_V2 0x34 61 #define GPIO_INT_POLARITY_V2 0x38 62 #define GPIO_INTSTATUS_V2 0x3c 63 #define GPIO_PORTA_EOI_V2 0x40 64 65 #define DWAPB_NR_CLOCKS 2 66 67 struct dwapb_gpio; 68 69 struct dwapb_port_property { 70 struct fwnode_handle *fwnode; 71 unsigned int idx; 72 unsigned int ngpio; 73 unsigned int gpio_base; 74 int irq[DWAPB_MAX_GPIOS]; 75 }; 76 77 struct dwapb_platform_data { 78 struct dwapb_port_property *properties; 79 unsigned int nports; 80 }; 81 82 #ifdef CONFIG_PM_SLEEP 83 /* Store GPIO context across system-wide suspend/resume transitions */ 84 struct dwapb_context { 85 u32 data; 86 u32 dir; 87 u32 ext; 88 u32 int_en; 89 u32 int_mask; 90 u32 int_type; 91 u32 int_pol; 92 u32 int_deb; 93 u32 wake_en; 94 }; 95 #endif 96 97 struct dwapb_gpio_port_irqchip { 98 struct irq_chip irqchip; 99 unsigned int nr_irqs; 100 unsigned int irq[DWAPB_MAX_GPIOS]; 101 }; 102 103 struct dwapb_gpio_port { 104 struct gpio_chip gc; 105 struct dwapb_gpio_port_irqchip *pirq; 106 struct dwapb_gpio *gpio; 107 #ifdef CONFIG_PM_SLEEP 108 struct dwapb_context *ctx; 109 #endif 110 unsigned int idx; 111 }; 112 #define to_dwapb_gpio(_gc) \ 113 (container_of(_gc, struct dwapb_gpio_port, gc)->gpio) 114 115 struct dwapb_gpio { 116 struct device *dev; 117 void __iomem *regs; 118 struct dwapb_gpio_port *ports; 119 unsigned int nr_ports; 120 unsigned int flags; 121 struct reset_control *rst; 122 struct clk_bulk_data clks[DWAPB_NR_CLOCKS]; 123 }; 124 125 static inline u32 gpio_reg_v2_convert(unsigned int offset) 126 { 127 switch (offset) { 128 case GPIO_INTMASK: 129 return GPIO_INTMASK_V2; 130 case GPIO_INTTYPE_LEVEL: 131 return GPIO_INTTYPE_LEVEL_V2; 132 case GPIO_INT_POLARITY: 133 return GPIO_INT_POLARITY_V2; 134 case GPIO_INTSTATUS: 135 return GPIO_INTSTATUS_V2; 136 case GPIO_PORTA_EOI: 137 return GPIO_PORTA_EOI_V2; 138 } 139 140 return offset; 141 } 142 143 static inline u32 gpio_reg_convert(struct dwapb_gpio *gpio, unsigned int offset) 144 { 145 if ((gpio->flags & GPIO_REG_OFFSET_MASK) == GPIO_REG_OFFSET_V2) 146 return gpio_reg_v2_convert(offset); 147 148 return offset; 149 } 150 151 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) 152 { 153 struct gpio_chip *gc = &gpio->ports[0].gc; 154 void __iomem *reg_base = gpio->regs; 155 156 return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); 157 } 158 159 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset, 160 u32 val) 161 { 162 struct gpio_chip *gc = &gpio->ports[0].gc; 163 void __iomem *reg_base = gpio->regs; 164 165 gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); 166 } 167 168 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio, unsigned int offs) 169 { 170 struct dwapb_gpio_port *port; 171 int i; 172 173 for (i = 0; i < gpio->nr_ports; i++) { 174 port = &gpio->ports[i]; 175 if (port->idx == offs / DWAPB_MAX_GPIOS) 176 return port; 177 } 178 179 return NULL; 180 } 181 182 static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs) 183 { 184 struct dwapb_gpio_port *port = dwapb_offs_to_port(gpio, offs); 185 struct gpio_chip *gc; 186 u32 pol; 187 int val; 188 189 if (!port) 190 return; 191 gc = &port->gc; 192 193 pol = dwapb_read(gpio, GPIO_INT_POLARITY); 194 /* Just read the current value right out of the data register */ 195 val = gc->get(gc, offs % DWAPB_MAX_GPIOS); 196 if (val) 197 pol &= ~BIT(offs); 198 else 199 pol |= BIT(offs); 200 201 dwapb_write(gpio, GPIO_INT_POLARITY, pol); 202 } 203 204 static u32 dwapb_do_irq(struct dwapb_gpio *gpio) 205 { 206 struct gpio_chip *gc = &gpio->ports[0].gc; 207 unsigned long irq_status; 208 irq_hw_number_t hwirq; 209 210 irq_status = dwapb_read(gpio, GPIO_INTSTATUS); 211 for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) { 212 int gpio_irq = irq_find_mapping(gc->irq.domain, hwirq); 213 u32 irq_type = irq_get_trigger_type(gpio_irq); 214 215 generic_handle_irq(gpio_irq); 216 217 if ((irq_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 218 dwapb_toggle_trigger(gpio, hwirq); 219 } 220 221 return irq_status; 222 } 223 224 static void dwapb_irq_handler(struct irq_desc *desc) 225 { 226 struct dwapb_gpio *gpio = irq_desc_get_handler_data(desc); 227 struct irq_chip *chip = irq_desc_get_chip(desc); 228 229 chained_irq_enter(chip, desc); 230 dwapb_do_irq(gpio); 231 chained_irq_exit(chip, desc); 232 } 233 234 static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id) 235 { 236 return IRQ_RETVAL(dwapb_do_irq(dev_id)); 237 } 238 239 static void dwapb_irq_ack(struct irq_data *d) 240 { 241 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 242 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 243 u32 val = BIT(irqd_to_hwirq(d)); 244 unsigned long flags; 245 246 spin_lock_irqsave(&gc->bgpio_lock, flags); 247 dwapb_write(gpio, GPIO_PORTA_EOI, val); 248 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 249 } 250 251 static void dwapb_irq_mask(struct irq_data *d) 252 { 253 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 254 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 255 unsigned long flags; 256 u32 val; 257 258 spin_lock_irqsave(&gc->bgpio_lock, flags); 259 val = dwapb_read(gpio, GPIO_INTMASK) | BIT(irqd_to_hwirq(d)); 260 dwapb_write(gpio, GPIO_INTMASK, val); 261 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 262 } 263 264 static void dwapb_irq_unmask(struct irq_data *d) 265 { 266 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 267 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 268 unsigned long flags; 269 u32 val; 270 271 spin_lock_irqsave(&gc->bgpio_lock, flags); 272 val = dwapb_read(gpio, GPIO_INTMASK) & ~BIT(irqd_to_hwirq(d)); 273 dwapb_write(gpio, GPIO_INTMASK, val); 274 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 275 } 276 277 static void dwapb_irq_enable(struct irq_data *d) 278 { 279 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 280 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 281 unsigned long flags; 282 u32 val; 283 284 spin_lock_irqsave(&gc->bgpio_lock, flags); 285 val = dwapb_read(gpio, GPIO_INTEN); 286 val |= BIT(irqd_to_hwirq(d)); 287 dwapb_write(gpio, GPIO_INTEN, val); 288 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 289 } 290 291 static void dwapb_irq_disable(struct irq_data *d) 292 { 293 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 294 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 295 unsigned long flags; 296 u32 val; 297 298 spin_lock_irqsave(&gc->bgpio_lock, flags); 299 val = dwapb_read(gpio, GPIO_INTEN); 300 val &= ~BIT(irqd_to_hwirq(d)); 301 dwapb_write(gpio, GPIO_INTEN, val); 302 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 303 } 304 305 static int dwapb_irq_set_type(struct irq_data *d, u32 type) 306 { 307 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 308 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 309 irq_hw_number_t bit = irqd_to_hwirq(d); 310 unsigned long level, polarity, flags; 311 312 spin_lock_irqsave(&gc->bgpio_lock, flags); 313 level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 314 polarity = dwapb_read(gpio, GPIO_INT_POLARITY); 315 316 switch (type) { 317 case IRQ_TYPE_EDGE_BOTH: 318 level |= BIT(bit); 319 dwapb_toggle_trigger(gpio, bit); 320 break; 321 case IRQ_TYPE_EDGE_RISING: 322 level |= BIT(bit); 323 polarity |= BIT(bit); 324 break; 325 case IRQ_TYPE_EDGE_FALLING: 326 level |= BIT(bit); 327 polarity &= ~BIT(bit); 328 break; 329 case IRQ_TYPE_LEVEL_HIGH: 330 level &= ~BIT(bit); 331 polarity |= BIT(bit); 332 break; 333 case IRQ_TYPE_LEVEL_LOW: 334 level &= ~BIT(bit); 335 polarity &= ~BIT(bit); 336 break; 337 } 338 339 if (type & IRQ_TYPE_LEVEL_MASK) 340 irq_set_handler_locked(d, handle_level_irq); 341 else if (type & IRQ_TYPE_EDGE_BOTH) 342 irq_set_handler_locked(d, handle_edge_irq); 343 344 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); 345 if (type != IRQ_TYPE_EDGE_BOTH) 346 dwapb_write(gpio, GPIO_INT_POLARITY, polarity); 347 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 348 349 return 0; 350 } 351 352 #ifdef CONFIG_PM_SLEEP 353 static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable) 354 { 355 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 356 struct dwapb_gpio *gpio = to_dwapb_gpio(gc); 357 struct dwapb_context *ctx = gpio->ports[0].ctx; 358 irq_hw_number_t bit = irqd_to_hwirq(d); 359 360 if (enable) 361 ctx->wake_en |= BIT(bit); 362 else 363 ctx->wake_en &= ~BIT(bit); 364 365 return 0; 366 } 367 #endif 368 369 static int dwapb_gpio_set_debounce(struct gpio_chip *gc, 370 unsigned offset, unsigned debounce) 371 { 372 struct dwapb_gpio_port *port = gpiochip_get_data(gc); 373 struct dwapb_gpio *gpio = port->gpio; 374 unsigned long flags, val_deb; 375 unsigned long mask = BIT(offset); 376 377 spin_lock_irqsave(&gc->bgpio_lock, flags); 378 379 val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 380 if (debounce) 381 val_deb |= mask; 382 else 383 val_deb &= ~mask; 384 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); 385 386 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 387 388 return 0; 389 } 390 391 static int dwapb_gpio_set_config(struct gpio_chip *gc, unsigned offset, 392 unsigned long config) 393 { 394 u32 debounce; 395 396 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 397 return -ENOTSUPP; 398 399 debounce = pinconf_to_config_argument(config); 400 return dwapb_gpio_set_debounce(gc, offset, debounce); 401 } 402 403 static int dwapb_convert_irqs(struct dwapb_gpio_port_irqchip *pirq, 404 struct dwapb_port_property *pp) 405 { 406 int i; 407 408 /* Group all available IRQs into an array of parental IRQs. */ 409 for (i = 0; i < pp->ngpio; ++i) { 410 if (!pp->irq[i]) 411 continue; 412 413 pirq->irq[pirq->nr_irqs++] = pp->irq[i]; 414 } 415 416 return pirq->nr_irqs ? 0 : -ENOENT; 417 } 418 419 static void dwapb_configure_irqs(struct dwapb_gpio *gpio, 420 struct dwapb_gpio_port *port, 421 struct dwapb_port_property *pp) 422 { 423 struct dwapb_gpio_port_irqchip *pirq; 424 struct gpio_chip *gc = &port->gc; 425 struct gpio_irq_chip *girq; 426 int err; 427 428 pirq = devm_kzalloc(gpio->dev, sizeof(*pirq), GFP_KERNEL); 429 if (!pirq) 430 return; 431 432 if (dwapb_convert_irqs(pirq, pp)) { 433 dev_warn(gpio->dev, "no IRQ for port%d\n", pp->idx); 434 goto err_kfree_pirq; 435 } 436 437 girq = &gc->irq; 438 girq->handler = handle_bad_irq; 439 girq->default_type = IRQ_TYPE_NONE; 440 441 port->pirq = pirq; 442 pirq->irqchip.name = DWAPB_DRIVER_NAME; 443 pirq->irqchip.irq_ack = dwapb_irq_ack; 444 pirq->irqchip.irq_mask = dwapb_irq_mask; 445 pirq->irqchip.irq_unmask = dwapb_irq_unmask; 446 pirq->irqchip.irq_set_type = dwapb_irq_set_type; 447 pirq->irqchip.irq_enable = dwapb_irq_enable; 448 pirq->irqchip.irq_disable = dwapb_irq_disable; 449 #ifdef CONFIG_PM_SLEEP 450 pirq->irqchip.irq_set_wake = dwapb_irq_set_wake; 451 #endif 452 453 /* 454 * Intel ACPI-based platforms mostly have the DesignWare APB GPIO 455 * IRQ lane shared between several devices. In that case the parental 456 * IRQ has to be handled in the shared way so to be properly delivered 457 * to all the connected devices. 458 */ 459 if (has_acpi_companion(gpio->dev)) { 460 girq->num_parents = 0; 461 girq->parents = NULL; 462 girq->parent_handler = NULL; 463 464 err = devm_request_irq(gpio->dev, pp->irq[0], 465 dwapb_irq_handler_mfd, 466 IRQF_SHARED, DWAPB_DRIVER_NAME, gpio); 467 if (err) { 468 dev_err(gpio->dev, "error requesting IRQ\n"); 469 goto err_kfree_pirq; 470 } 471 } else { 472 girq->num_parents = pirq->nr_irqs; 473 girq->parents = pirq->irq; 474 girq->parent_handler_data = gpio; 475 girq->parent_handler = dwapb_irq_handler; 476 } 477 478 girq->chip = &pirq->irqchip; 479 480 return; 481 482 err_kfree_pirq: 483 devm_kfree(gpio->dev, pirq); 484 } 485 486 static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, 487 struct dwapb_port_property *pp, 488 unsigned int offs) 489 { 490 struct dwapb_gpio_port *port; 491 void __iomem *dat, *set, *dirout; 492 int err; 493 494 port = &gpio->ports[offs]; 495 port->gpio = gpio; 496 port->idx = pp->idx; 497 498 #ifdef CONFIG_PM_SLEEP 499 port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL); 500 if (!port->ctx) 501 return -ENOMEM; 502 #endif 503 504 dat = gpio->regs + GPIO_EXT_PORTA + pp->idx * GPIO_EXT_PORT_STRIDE; 505 set = gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; 506 dirout = gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRIDE; 507 508 /* This registers 32 GPIO lines per port */ 509 err = bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, 510 NULL, 0); 511 if (err) { 512 dev_err(gpio->dev, "failed to init gpio chip for port%d\n", 513 port->idx); 514 return err; 515 } 516 517 port->gc.fwnode = pp->fwnode; 518 port->gc.ngpio = pp->ngpio; 519 port->gc.base = pp->gpio_base; 520 521 /* Only port A support debounce */ 522 if (pp->idx == 0) 523 port->gc.set_config = dwapb_gpio_set_config; 524 525 /* Only port A can provide interrupts in all configurations of the IP */ 526 if (pp->idx == 0) 527 dwapb_configure_irqs(gpio, port, pp); 528 529 err = devm_gpiochip_add_data(gpio->dev, &port->gc, port); 530 if (err) { 531 dev_err(gpio->dev, "failed to register gpiochip for port%d\n", 532 port->idx); 533 return err; 534 } 535 536 return 0; 537 } 538 539 static void dwapb_get_irq(struct device *dev, struct fwnode_handle *fwnode, 540 struct dwapb_port_property *pp) 541 { 542 int irq, j; 543 544 for (j = 0; j < pp->ngpio; j++) { 545 if (has_acpi_companion(dev)) 546 irq = platform_get_irq_optional(to_platform_device(dev), j); 547 else 548 irq = fwnode_irq_get(fwnode, j); 549 if (irq > 0) 550 pp->irq[j] = irq; 551 } 552 } 553 554 static struct dwapb_platform_data *dwapb_gpio_get_pdata(struct device *dev) 555 { 556 struct fwnode_handle *fwnode; 557 struct dwapb_platform_data *pdata; 558 struct dwapb_port_property *pp; 559 int nports; 560 int i; 561 562 nports = device_get_child_node_count(dev); 563 if (nports == 0) 564 return ERR_PTR(-ENODEV); 565 566 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 567 if (!pdata) 568 return ERR_PTR(-ENOMEM); 569 570 pdata->properties = devm_kcalloc(dev, nports, sizeof(*pp), GFP_KERNEL); 571 if (!pdata->properties) 572 return ERR_PTR(-ENOMEM); 573 574 pdata->nports = nports; 575 576 i = 0; 577 device_for_each_child_node(dev, fwnode) { 578 pp = &pdata->properties[i++]; 579 pp->fwnode = fwnode; 580 581 if (fwnode_property_read_u32(fwnode, "reg", &pp->idx) || 582 pp->idx >= DWAPB_MAX_PORTS) { 583 dev_err(dev, 584 "missing/invalid port index for port%d\n", i); 585 fwnode_handle_put(fwnode); 586 return ERR_PTR(-EINVAL); 587 } 588 589 if (fwnode_property_read_u32(fwnode, "ngpios", &pp->ngpio) && 590 fwnode_property_read_u32(fwnode, "snps,nr-gpios", &pp->ngpio)) { 591 dev_info(dev, 592 "failed to get number of gpios for port%d\n", 593 i); 594 pp->ngpio = DWAPB_MAX_GPIOS; 595 } 596 597 pp->gpio_base = -1; 598 599 /* For internal use only, new platforms mustn't exercise this */ 600 if (is_software_node(fwnode)) 601 fwnode_property_read_u32(fwnode, "gpio-base", &pp->gpio_base); 602 603 /* 604 * Only port A can provide interrupts in all configurations of 605 * the IP. 606 */ 607 if (pp->idx == 0) 608 dwapb_get_irq(dev, fwnode, pp); 609 } 610 611 return pdata; 612 } 613 614 static void dwapb_assert_reset(void *data) 615 { 616 struct dwapb_gpio *gpio = data; 617 618 reset_control_assert(gpio->rst); 619 } 620 621 static int dwapb_get_reset(struct dwapb_gpio *gpio) 622 { 623 int err; 624 625 gpio->rst = devm_reset_control_get_optional_shared(gpio->dev, NULL); 626 if (IS_ERR(gpio->rst)) 627 return dev_err_probe(gpio->dev, PTR_ERR(gpio->rst), 628 "Cannot get reset descriptor\n"); 629 630 err = reset_control_deassert(gpio->rst); 631 if (err) { 632 dev_err(gpio->dev, "Cannot deassert reset lane\n"); 633 return err; 634 } 635 636 return devm_add_action_or_reset(gpio->dev, dwapb_assert_reset, gpio); 637 } 638 639 static void dwapb_disable_clks(void *data) 640 { 641 struct dwapb_gpio *gpio = data; 642 643 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); 644 } 645 646 static int dwapb_get_clks(struct dwapb_gpio *gpio) 647 { 648 int err; 649 650 /* Optional bus and debounce clocks */ 651 gpio->clks[0].id = "bus"; 652 gpio->clks[1].id = "db"; 653 err = devm_clk_bulk_get_optional(gpio->dev, DWAPB_NR_CLOCKS, 654 gpio->clks); 655 if (err) { 656 dev_err(gpio->dev, "Cannot get APB/Debounce clocks\n"); 657 return err; 658 } 659 660 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); 661 if (err) { 662 dev_err(gpio->dev, "Cannot enable APB/Debounce clocks\n"); 663 return err; 664 } 665 666 return devm_add_action_or_reset(gpio->dev, dwapb_disable_clks, gpio); 667 } 668 669 static const struct of_device_id dwapb_of_match[] = { 670 { .compatible = "snps,dw-apb-gpio", .data = (void *)GPIO_REG_OFFSET_V1}, 671 { .compatible = "apm,xgene-gpio-v2", .data = (void *)GPIO_REG_OFFSET_V2}, 672 { /* Sentinel */ } 673 }; 674 MODULE_DEVICE_TABLE(of, dwapb_of_match); 675 676 static const struct acpi_device_id dwapb_acpi_match[] = { 677 {"HISI0181", GPIO_REG_OFFSET_V1}, 678 {"APMC0D07", GPIO_REG_OFFSET_V1}, 679 {"APMC0D81", GPIO_REG_OFFSET_V2}, 680 { } 681 }; 682 MODULE_DEVICE_TABLE(acpi, dwapb_acpi_match); 683 684 static int dwapb_gpio_probe(struct platform_device *pdev) 685 { 686 unsigned int i; 687 struct dwapb_gpio *gpio; 688 int err; 689 struct dwapb_platform_data *pdata; 690 struct device *dev = &pdev->dev; 691 692 pdata = dwapb_gpio_get_pdata(dev); 693 if (IS_ERR(pdata)) 694 return PTR_ERR(pdata); 695 696 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 697 if (!gpio) 698 return -ENOMEM; 699 700 gpio->dev = &pdev->dev; 701 gpio->nr_ports = pdata->nports; 702 703 err = dwapb_get_reset(gpio); 704 if (err) 705 return err; 706 707 gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports, 708 sizeof(*gpio->ports), GFP_KERNEL); 709 if (!gpio->ports) 710 return -ENOMEM; 711 712 gpio->regs = devm_platform_ioremap_resource(pdev, 0); 713 if (IS_ERR(gpio->regs)) 714 return PTR_ERR(gpio->regs); 715 716 err = dwapb_get_clks(gpio); 717 if (err) 718 return err; 719 720 gpio->flags = (uintptr_t)device_get_match_data(dev); 721 722 for (i = 0; i < gpio->nr_ports; i++) { 723 err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i); 724 if (err) 725 return err; 726 } 727 728 platform_set_drvdata(pdev, gpio); 729 730 return 0; 731 } 732 733 #ifdef CONFIG_PM_SLEEP 734 static int dwapb_gpio_suspend(struct device *dev) 735 { 736 struct dwapb_gpio *gpio = dev_get_drvdata(dev); 737 struct gpio_chip *gc = &gpio->ports[0].gc; 738 unsigned long flags; 739 int i; 740 741 spin_lock_irqsave(&gc->bgpio_lock, flags); 742 for (i = 0; i < gpio->nr_ports; i++) { 743 unsigned int offset; 744 unsigned int idx = gpio->ports[i].idx; 745 struct dwapb_context *ctx = gpio->ports[i].ctx; 746 747 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 748 ctx->dir = dwapb_read(gpio, offset); 749 750 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 751 ctx->data = dwapb_read(gpio, offset); 752 753 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 754 ctx->ext = dwapb_read(gpio, offset); 755 756 /* Only port A can provide interrupts */ 757 if (idx == 0) { 758 ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK); 759 ctx->int_en = dwapb_read(gpio, GPIO_INTEN); 760 ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY); 761 ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL); 762 ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); 763 764 /* Mask out interrupts */ 765 dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); 766 } 767 } 768 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 769 770 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); 771 772 return 0; 773 } 774 775 static int dwapb_gpio_resume(struct device *dev) 776 { 777 struct dwapb_gpio *gpio = dev_get_drvdata(dev); 778 struct gpio_chip *gc = &gpio->ports[0].gc; 779 unsigned long flags; 780 int i, err; 781 782 err = clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); 783 if (err) { 784 dev_err(gpio->dev, "Cannot reenable APB/Debounce clocks\n"); 785 return err; 786 } 787 788 spin_lock_irqsave(&gc->bgpio_lock, flags); 789 for (i = 0; i < gpio->nr_ports; i++) { 790 unsigned int offset; 791 unsigned int idx = gpio->ports[i].idx; 792 struct dwapb_context *ctx = gpio->ports[i].ctx; 793 794 offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; 795 dwapb_write(gpio, offset, ctx->data); 796 797 offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; 798 dwapb_write(gpio, offset, ctx->dir); 799 800 offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; 801 dwapb_write(gpio, offset, ctx->ext); 802 803 /* Only port A can provide interrupts */ 804 if (idx == 0) { 805 dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type); 806 dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol); 807 dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb); 808 dwapb_write(gpio, GPIO_INTEN, ctx->int_en); 809 dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask); 810 811 /* Clear out spurious interrupts */ 812 dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); 813 } 814 } 815 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 816 817 return 0; 818 } 819 #endif 820 821 static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend, 822 dwapb_gpio_resume); 823 824 static struct platform_driver dwapb_gpio_driver = { 825 .driver = { 826 .name = DWAPB_DRIVER_NAME, 827 .pm = &dwapb_gpio_pm_ops, 828 .of_match_table = dwapb_of_match, 829 .acpi_match_table = dwapb_acpi_match, 830 }, 831 .probe = dwapb_gpio_probe, 832 }; 833 834 module_platform_driver(dwapb_gpio_driver); 835 836 MODULE_LICENSE("GPL"); 837 MODULE_AUTHOR("Jamie Iles"); 838 MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver"); 839 MODULE_ALIAS("platform:" DWAPB_DRIVER_NAME); 840