1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the Diolan DLN-2 USB-GPIO adapter 4 * 5 * Copyright (c) 2014 Intel Corporation 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/slab.h> 11 #include <linux/types.h> 12 #include <linux/irqdomain.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/platform_device.h> 17 #include <linux/mfd/dln2.h> 18 19 #define DLN2_GPIO_ID 0x01 20 21 #define DLN2_GPIO_GET_PIN_COUNT DLN2_CMD(0x01, DLN2_GPIO_ID) 22 #define DLN2_GPIO_SET_DEBOUNCE DLN2_CMD(0x04, DLN2_GPIO_ID) 23 #define DLN2_GPIO_GET_DEBOUNCE DLN2_CMD(0x05, DLN2_GPIO_ID) 24 #define DLN2_GPIO_PORT_GET_VAL DLN2_CMD(0x06, DLN2_GPIO_ID) 25 #define DLN2_GPIO_PIN_GET_VAL DLN2_CMD(0x0B, DLN2_GPIO_ID) 26 #define DLN2_GPIO_PIN_SET_OUT_VAL DLN2_CMD(0x0C, DLN2_GPIO_ID) 27 #define DLN2_GPIO_PIN_GET_OUT_VAL DLN2_CMD(0x0D, DLN2_GPIO_ID) 28 #define DLN2_GPIO_CONDITION_MET_EV DLN2_CMD(0x0F, DLN2_GPIO_ID) 29 #define DLN2_GPIO_PIN_ENABLE DLN2_CMD(0x10, DLN2_GPIO_ID) 30 #define DLN2_GPIO_PIN_DISABLE DLN2_CMD(0x11, DLN2_GPIO_ID) 31 #define DLN2_GPIO_PIN_SET_DIRECTION DLN2_CMD(0x13, DLN2_GPIO_ID) 32 #define DLN2_GPIO_PIN_GET_DIRECTION DLN2_CMD(0x14, DLN2_GPIO_ID) 33 #define DLN2_GPIO_PIN_SET_EVENT_CFG DLN2_CMD(0x1E, DLN2_GPIO_ID) 34 #define DLN2_GPIO_PIN_GET_EVENT_CFG DLN2_CMD(0x1F, DLN2_GPIO_ID) 35 36 #define DLN2_GPIO_EVENT_NONE 0 37 #define DLN2_GPIO_EVENT_CHANGE 1 38 #define DLN2_GPIO_EVENT_LVL_HIGH 2 39 #define DLN2_GPIO_EVENT_LVL_LOW 3 40 #define DLN2_GPIO_EVENT_CHANGE_RISING 0x11 41 #define DLN2_GPIO_EVENT_CHANGE_FALLING 0x21 42 #define DLN2_GPIO_EVENT_MASK 0x0F 43 44 #define DLN2_GPIO_MAX_PINS 32 45 46 struct dln2_gpio { 47 struct platform_device *pdev; 48 struct gpio_chip gpio; 49 struct irq_chip irqchip; 50 51 /* 52 * Cache pin direction to save us one transfer, since the hardware has 53 * separate commands to read the in and out values. 54 */ 55 DECLARE_BITMAP(output_enabled, DLN2_GPIO_MAX_PINS); 56 57 /* active IRQs - not synced to hardware */ 58 DECLARE_BITMAP(unmasked_irqs, DLN2_GPIO_MAX_PINS); 59 /* active IRQS - synced to hardware */ 60 DECLARE_BITMAP(enabled_irqs, DLN2_GPIO_MAX_PINS); 61 int irq_type[DLN2_GPIO_MAX_PINS]; 62 struct mutex irq_lock; 63 }; 64 65 struct dln2_gpio_pin { 66 __le16 pin; 67 }; 68 69 struct dln2_gpio_pin_val { 70 __le16 pin __packed; 71 u8 value; 72 }; 73 74 static int dln2_gpio_get_pin_count(struct platform_device *pdev) 75 { 76 int ret; 77 __le16 count; 78 int len = sizeof(count); 79 80 ret = dln2_transfer_rx(pdev, DLN2_GPIO_GET_PIN_COUNT, &count, &len); 81 if (ret < 0) 82 return ret; 83 if (len < sizeof(count)) 84 return -EPROTO; 85 86 return le16_to_cpu(count); 87 } 88 89 static int dln2_gpio_pin_cmd(struct dln2_gpio *dln2, int cmd, unsigned pin) 90 { 91 struct dln2_gpio_pin req = { 92 .pin = cpu_to_le16(pin), 93 }; 94 95 return dln2_transfer_tx(dln2->pdev, cmd, &req, sizeof(req)); 96 } 97 98 static int dln2_gpio_pin_val(struct dln2_gpio *dln2, int cmd, unsigned int pin) 99 { 100 int ret; 101 struct dln2_gpio_pin req = { 102 .pin = cpu_to_le16(pin), 103 }; 104 struct dln2_gpio_pin_val rsp; 105 int len = sizeof(rsp); 106 107 ret = dln2_transfer(dln2->pdev, cmd, &req, sizeof(req), &rsp, &len); 108 if (ret < 0) 109 return ret; 110 if (len < sizeof(rsp) || req.pin != rsp.pin) 111 return -EPROTO; 112 113 return rsp.value; 114 } 115 116 static int dln2_gpio_pin_get_in_val(struct dln2_gpio *dln2, unsigned int pin) 117 { 118 int ret; 119 120 ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_VAL, pin); 121 if (ret < 0) 122 return ret; 123 return !!ret; 124 } 125 126 static int dln2_gpio_pin_get_out_val(struct dln2_gpio *dln2, unsigned int pin) 127 { 128 int ret; 129 130 ret = dln2_gpio_pin_val(dln2, DLN2_GPIO_PIN_GET_OUT_VAL, pin); 131 if (ret < 0) 132 return ret; 133 return !!ret; 134 } 135 136 static int dln2_gpio_pin_set_out_val(struct dln2_gpio *dln2, 137 unsigned int pin, int value) 138 { 139 struct dln2_gpio_pin_val req = { 140 .pin = cpu_to_le16(pin), 141 .value = value, 142 }; 143 144 return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_OUT_VAL, &req, 145 sizeof(req)); 146 } 147 148 #define DLN2_GPIO_DIRECTION_IN 0 149 #define DLN2_GPIO_DIRECTION_OUT 1 150 151 static int dln2_gpio_request(struct gpio_chip *chip, unsigned offset) 152 { 153 struct dln2_gpio *dln2 = gpiochip_get_data(chip); 154 struct dln2_gpio_pin req = { 155 .pin = cpu_to_le16(offset), 156 }; 157 struct dln2_gpio_pin_val rsp; 158 int len = sizeof(rsp); 159 int ret; 160 161 ret = dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_ENABLE, offset); 162 if (ret < 0) 163 return ret; 164 165 /* cache the pin direction */ 166 ret = dln2_transfer(dln2->pdev, DLN2_GPIO_PIN_GET_DIRECTION, 167 &req, sizeof(req), &rsp, &len); 168 if (ret < 0) 169 return ret; 170 if (len < sizeof(rsp) || req.pin != rsp.pin) { 171 ret = -EPROTO; 172 goto out_disable; 173 } 174 175 switch (rsp.value) { 176 case DLN2_GPIO_DIRECTION_IN: 177 clear_bit(offset, dln2->output_enabled); 178 return 0; 179 case DLN2_GPIO_DIRECTION_OUT: 180 set_bit(offset, dln2->output_enabled); 181 return 0; 182 default: 183 ret = -EPROTO; 184 goto out_disable; 185 } 186 187 out_disable: 188 dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset); 189 return ret; 190 } 191 192 static void dln2_gpio_free(struct gpio_chip *chip, unsigned offset) 193 { 194 struct dln2_gpio *dln2 = gpiochip_get_data(chip); 195 196 dln2_gpio_pin_cmd(dln2, DLN2_GPIO_PIN_DISABLE, offset); 197 } 198 199 static int dln2_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 200 { 201 struct dln2_gpio *dln2 = gpiochip_get_data(chip); 202 203 if (test_bit(offset, dln2->output_enabled)) 204 return GPIO_LINE_DIRECTION_OUT; 205 206 return GPIO_LINE_DIRECTION_IN; 207 } 208 209 static int dln2_gpio_get(struct gpio_chip *chip, unsigned int offset) 210 { 211 struct dln2_gpio *dln2 = gpiochip_get_data(chip); 212 int dir; 213 214 dir = dln2_gpio_get_direction(chip, offset); 215 if (dir < 0) 216 return dir; 217 218 if (dir == GPIO_LINE_DIRECTION_IN) 219 return dln2_gpio_pin_get_in_val(dln2, offset); 220 221 return dln2_gpio_pin_get_out_val(dln2, offset); 222 } 223 224 static void dln2_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 225 { 226 struct dln2_gpio *dln2 = gpiochip_get_data(chip); 227 228 dln2_gpio_pin_set_out_val(dln2, offset, value); 229 } 230 231 static int dln2_gpio_set_direction(struct gpio_chip *chip, unsigned offset, 232 unsigned dir) 233 { 234 struct dln2_gpio *dln2 = gpiochip_get_data(chip); 235 struct dln2_gpio_pin_val req = { 236 .pin = cpu_to_le16(offset), 237 .value = dir, 238 }; 239 int ret; 240 241 ret = dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_DIRECTION, 242 &req, sizeof(req)); 243 if (ret < 0) 244 return ret; 245 246 if (dir == DLN2_GPIO_DIRECTION_OUT) 247 set_bit(offset, dln2->output_enabled); 248 else 249 clear_bit(offset, dln2->output_enabled); 250 251 return ret; 252 } 253 254 static int dln2_gpio_direction_input(struct gpio_chip *chip, unsigned offset) 255 { 256 return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_IN); 257 } 258 259 static int dln2_gpio_direction_output(struct gpio_chip *chip, unsigned offset, 260 int value) 261 { 262 struct dln2_gpio *dln2 = gpiochip_get_data(chip); 263 int ret; 264 265 ret = dln2_gpio_pin_set_out_val(dln2, offset, value); 266 if (ret < 0) 267 return ret; 268 269 return dln2_gpio_set_direction(chip, offset, DLN2_GPIO_DIRECTION_OUT); 270 } 271 272 static int dln2_gpio_set_config(struct gpio_chip *chip, unsigned offset, 273 unsigned long config) 274 { 275 struct dln2_gpio *dln2 = gpiochip_get_data(chip); 276 __le32 duration; 277 278 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 279 return -ENOTSUPP; 280 281 duration = cpu_to_le32(pinconf_to_config_argument(config)); 282 return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_SET_DEBOUNCE, 283 &duration, sizeof(duration)); 284 } 285 286 static int dln2_gpio_set_event_cfg(struct dln2_gpio *dln2, unsigned pin, 287 unsigned type, unsigned period) 288 { 289 struct { 290 __le16 pin; 291 u8 type; 292 __le16 period; 293 } __packed req = { 294 .pin = cpu_to_le16(pin), 295 .type = type, 296 .period = cpu_to_le16(period), 297 }; 298 299 return dln2_transfer_tx(dln2->pdev, DLN2_GPIO_PIN_SET_EVENT_CFG, 300 &req, sizeof(req)); 301 } 302 303 static void dln2_irq_unmask(struct irq_data *irqd) 304 { 305 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 306 struct dln2_gpio *dln2 = gpiochip_get_data(gc); 307 int pin = irqd_to_hwirq(irqd); 308 309 set_bit(pin, dln2->unmasked_irqs); 310 } 311 312 static void dln2_irq_mask(struct irq_data *irqd) 313 { 314 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 315 struct dln2_gpio *dln2 = gpiochip_get_data(gc); 316 int pin = irqd_to_hwirq(irqd); 317 318 clear_bit(pin, dln2->unmasked_irqs); 319 } 320 321 static int dln2_irq_set_type(struct irq_data *irqd, unsigned type) 322 { 323 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 324 struct dln2_gpio *dln2 = gpiochip_get_data(gc); 325 int pin = irqd_to_hwirq(irqd); 326 327 switch (type) { 328 case IRQ_TYPE_LEVEL_HIGH: 329 dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_HIGH; 330 break; 331 case IRQ_TYPE_LEVEL_LOW: 332 dln2->irq_type[pin] = DLN2_GPIO_EVENT_LVL_LOW; 333 break; 334 case IRQ_TYPE_EDGE_BOTH: 335 dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE; 336 break; 337 case IRQ_TYPE_EDGE_RISING: 338 dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_RISING; 339 break; 340 case IRQ_TYPE_EDGE_FALLING: 341 dln2->irq_type[pin] = DLN2_GPIO_EVENT_CHANGE_FALLING; 342 break; 343 default: 344 return -EINVAL; 345 } 346 347 return 0; 348 } 349 350 static void dln2_irq_bus_lock(struct irq_data *irqd) 351 { 352 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 353 struct dln2_gpio *dln2 = gpiochip_get_data(gc); 354 355 mutex_lock(&dln2->irq_lock); 356 } 357 358 static void dln2_irq_bus_unlock(struct irq_data *irqd) 359 { 360 struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd); 361 struct dln2_gpio *dln2 = gpiochip_get_data(gc); 362 int pin = irqd_to_hwirq(irqd); 363 int enabled, unmasked; 364 unsigned type; 365 int ret; 366 367 enabled = test_bit(pin, dln2->enabled_irqs); 368 unmasked = test_bit(pin, dln2->unmasked_irqs); 369 370 if (enabled != unmasked) { 371 if (unmasked) { 372 type = dln2->irq_type[pin] & DLN2_GPIO_EVENT_MASK; 373 set_bit(pin, dln2->enabled_irqs); 374 } else { 375 type = DLN2_GPIO_EVENT_NONE; 376 clear_bit(pin, dln2->enabled_irqs); 377 } 378 379 ret = dln2_gpio_set_event_cfg(dln2, pin, type, 0); 380 if (ret) 381 dev_err(dln2->gpio.parent, "failed to set event\n"); 382 } 383 384 mutex_unlock(&dln2->irq_lock); 385 } 386 387 static void dln2_gpio_event(struct platform_device *pdev, u16 echo, 388 const void *data, int len) 389 { 390 int pin, ret; 391 392 const struct { 393 __le16 count; 394 __u8 type; 395 __le16 pin; 396 __u8 value; 397 } __packed *event = data; 398 struct dln2_gpio *dln2 = platform_get_drvdata(pdev); 399 400 if (len < sizeof(*event)) { 401 dev_err(dln2->gpio.parent, "short event message\n"); 402 return; 403 } 404 405 pin = le16_to_cpu(event->pin); 406 if (pin >= dln2->gpio.ngpio) { 407 dev_err(dln2->gpio.parent, "out of bounds pin %d\n", pin); 408 return; 409 } 410 411 switch (dln2->irq_type[pin]) { 412 case DLN2_GPIO_EVENT_CHANGE_RISING: 413 if (!event->value) 414 return; 415 break; 416 case DLN2_GPIO_EVENT_CHANGE_FALLING: 417 if (event->value) 418 return; 419 break; 420 } 421 422 ret = generic_handle_domain_irq(dln2->gpio.irq.domain, pin); 423 if (unlikely(ret)) 424 dev_err(dln2->gpio.parent, "pin %d not mapped to IRQ\n", pin); 425 } 426 427 static int dln2_gpio_probe(struct platform_device *pdev) 428 { 429 struct dln2_gpio *dln2; 430 struct device *dev = &pdev->dev; 431 struct gpio_irq_chip *girq; 432 int pins; 433 int ret; 434 435 pins = dln2_gpio_get_pin_count(pdev); 436 if (pins < 0) { 437 dev_err(dev, "failed to get pin count: %d\n", pins); 438 return pins; 439 } 440 if (pins > DLN2_GPIO_MAX_PINS) { 441 pins = DLN2_GPIO_MAX_PINS; 442 dev_warn(dev, "clamping pins to %d\n", DLN2_GPIO_MAX_PINS); 443 } 444 445 dln2 = devm_kzalloc(&pdev->dev, sizeof(*dln2), GFP_KERNEL); 446 if (!dln2) 447 return -ENOMEM; 448 449 mutex_init(&dln2->irq_lock); 450 451 dln2->pdev = pdev; 452 453 dln2->gpio.label = "dln2"; 454 dln2->gpio.parent = dev; 455 dln2->gpio.owner = THIS_MODULE; 456 dln2->gpio.base = -1; 457 dln2->gpio.ngpio = pins; 458 dln2->gpio.can_sleep = true; 459 dln2->gpio.set = dln2_gpio_set; 460 dln2->gpio.get = dln2_gpio_get; 461 dln2->gpio.request = dln2_gpio_request; 462 dln2->gpio.free = dln2_gpio_free; 463 dln2->gpio.get_direction = dln2_gpio_get_direction; 464 dln2->gpio.direction_input = dln2_gpio_direction_input; 465 dln2->gpio.direction_output = dln2_gpio_direction_output; 466 dln2->gpio.set_config = dln2_gpio_set_config; 467 468 dln2->irqchip.name = "dln2-irq", 469 dln2->irqchip.irq_mask = dln2_irq_mask, 470 dln2->irqchip.irq_unmask = dln2_irq_unmask, 471 dln2->irqchip.irq_set_type = dln2_irq_set_type, 472 dln2->irqchip.irq_bus_lock = dln2_irq_bus_lock, 473 dln2->irqchip.irq_bus_sync_unlock = dln2_irq_bus_unlock, 474 475 girq = &dln2->gpio.irq; 476 girq->chip = &dln2->irqchip; 477 /* The event comes from the outside so no parent handler */ 478 girq->parent_handler = NULL; 479 girq->num_parents = 0; 480 girq->parents = NULL; 481 girq->default_type = IRQ_TYPE_NONE; 482 girq->handler = handle_simple_irq; 483 484 platform_set_drvdata(pdev, dln2); 485 486 ret = devm_gpiochip_add_data(dev, &dln2->gpio, dln2); 487 if (ret < 0) { 488 dev_err(dev, "failed to add gpio chip: %d\n", ret); 489 return ret; 490 } 491 492 ret = dln2_register_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV, 493 dln2_gpio_event); 494 if (ret) { 495 dev_err(dev, "failed to register event cb: %d\n", ret); 496 return ret; 497 } 498 499 return 0; 500 } 501 502 static int dln2_gpio_remove(struct platform_device *pdev) 503 { 504 dln2_unregister_event_cb(pdev, DLN2_GPIO_CONDITION_MET_EV); 505 506 return 0; 507 } 508 509 static struct platform_driver dln2_gpio_driver = { 510 .driver.name = "dln2-gpio", 511 .probe = dln2_gpio_probe, 512 .remove = dln2_gpio_remove, 513 }; 514 515 module_platform_driver(dln2_gpio_driver); 516 517 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com"); 518 MODULE_DESCRIPTION("Driver for the Diolan DLN2 GPIO interface"); 519 MODULE_LICENSE("GPL v2"); 520 MODULE_ALIAS("platform:dln2-gpio"); 521