1 /* 2 * TI DaVinci GPIO Support 3 * 4 * Copyright (c) 2006-2007 David Brownell 5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 */ 12 #include <linux/gpio.h> 13 #include <linux/errno.h> 14 #include <linux/kernel.h> 15 #include <linux/clk.h> 16 #include <linux/err.h> 17 #include <linux/io.h> 18 19 #include <asm/mach/irq.h> 20 21 struct davinci_gpio_regs { 22 u32 dir; 23 u32 out_data; 24 u32 set_data; 25 u32 clr_data; 26 u32 in_data; 27 u32 set_rising; 28 u32 clr_rising; 29 u32 set_falling; 30 u32 clr_falling; 31 u32 intstat; 32 }; 33 34 #define chip2controller(chip) \ 35 container_of(chip, struct davinci_gpio_controller, chip) 36 37 static struct davinci_gpio_controller chips[DIV_ROUND_UP(DAVINCI_N_GPIO, 32)]; 38 static void __iomem *gpio_base; 39 40 static struct davinci_gpio_regs __iomem __init *gpio2regs(unsigned gpio) 41 { 42 void __iomem *ptr; 43 44 if (gpio < 32 * 1) 45 ptr = gpio_base + 0x10; 46 else if (gpio < 32 * 2) 47 ptr = gpio_base + 0x38; 48 else if (gpio < 32 * 3) 49 ptr = gpio_base + 0x60; 50 else if (gpio < 32 * 4) 51 ptr = gpio_base + 0x88; 52 else if (gpio < 32 * 5) 53 ptr = gpio_base + 0xb0; 54 else 55 ptr = NULL; 56 return ptr; 57 } 58 59 static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) 60 { 61 struct davinci_gpio_regs __iomem *g; 62 63 g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq); 64 65 return g; 66 } 67 68 static int __init davinci_gpio_irq_setup(void); 69 70 /*--------------------------------------------------------------------------*/ 71 72 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ 73 static inline int __davinci_direction(struct gpio_chip *chip, 74 unsigned offset, bool out, int value) 75 { 76 struct davinci_gpio_controller *d = chip2controller(chip); 77 struct davinci_gpio_regs __iomem *g = d->regs; 78 unsigned long flags; 79 u32 temp; 80 u32 mask = 1 << offset; 81 82 spin_lock_irqsave(&d->lock, flags); 83 temp = __raw_readl(&g->dir); 84 if (out) { 85 temp &= ~mask; 86 __raw_writel(mask, value ? &g->set_data : &g->clr_data); 87 } else { 88 temp |= mask; 89 } 90 __raw_writel(temp, &g->dir); 91 spin_unlock_irqrestore(&d->lock, flags); 92 93 return 0; 94 } 95 96 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) 97 { 98 return __davinci_direction(chip, offset, false, 0); 99 } 100 101 static int 102 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) 103 { 104 return __davinci_direction(chip, offset, true, value); 105 } 106 107 /* 108 * Read the pin's value (works even if it's set up as output); 109 * returns zero/nonzero. 110 * 111 * Note that changes are synched to the GPIO clock, so reading values back 112 * right after you've set them may give old values. 113 */ 114 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) 115 { 116 struct davinci_gpio_controller *d = chip2controller(chip); 117 struct davinci_gpio_regs __iomem *g = d->regs; 118 119 return (1 << offset) & __raw_readl(&g->in_data); 120 } 121 122 /* 123 * Assuming the pin is muxed as a gpio output, set its output value. 124 */ 125 static void 126 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 127 { 128 struct davinci_gpio_controller *d = chip2controller(chip); 129 struct davinci_gpio_regs __iomem *g = d->regs; 130 131 __raw_writel((1 << offset), value ? &g->set_data : &g->clr_data); 132 } 133 134 static int __init davinci_gpio_setup(void) 135 { 136 int i, base; 137 unsigned ngpio; 138 struct davinci_soc_info *soc_info = &davinci_soc_info; 139 struct davinci_gpio_regs *regs; 140 141 if (soc_info->gpio_type != GPIO_TYPE_DAVINCI) 142 return 0; 143 144 /* 145 * The gpio banks conceptually expose a segmented bitmap, 146 * and "ngpio" is one more than the largest zero-based 147 * bit index that's valid. 148 */ 149 ngpio = soc_info->gpio_num; 150 if (ngpio == 0) { 151 pr_err("GPIO setup: how many GPIOs?\n"); 152 return -EINVAL; 153 } 154 155 if (WARN_ON(DAVINCI_N_GPIO < ngpio)) 156 ngpio = DAVINCI_N_GPIO; 157 158 gpio_base = ioremap(soc_info->gpio_base, SZ_4K); 159 if (WARN_ON(!gpio_base)) 160 return -ENOMEM; 161 162 for (i = 0, base = 0; base < ngpio; i++, base += 32) { 163 chips[i].chip.label = "DaVinci"; 164 165 chips[i].chip.direction_input = davinci_direction_in; 166 chips[i].chip.get = davinci_gpio_get; 167 chips[i].chip.direction_output = davinci_direction_out; 168 chips[i].chip.set = davinci_gpio_set; 169 170 chips[i].chip.base = base; 171 chips[i].chip.ngpio = ngpio - base; 172 if (chips[i].chip.ngpio > 32) 173 chips[i].chip.ngpio = 32; 174 175 spin_lock_init(&chips[i].lock); 176 177 regs = gpio2regs(base); 178 chips[i].regs = regs; 179 chips[i].set_data = ®s->set_data; 180 chips[i].clr_data = ®s->clr_data; 181 chips[i].in_data = ®s->in_data; 182 183 gpiochip_add(&chips[i].chip); 184 } 185 186 soc_info->gpio_ctlrs = chips; 187 soc_info->gpio_ctlrs_num = DIV_ROUND_UP(ngpio, 32); 188 189 davinci_gpio_irq_setup(); 190 return 0; 191 } 192 pure_initcall(davinci_gpio_setup); 193 194 /*--------------------------------------------------------------------------*/ 195 /* 196 * We expect irqs will normally be set up as input pins, but they can also be 197 * used as output pins ... which is convenient for testing. 198 * 199 * NOTE: The first few GPIOs also have direct INTC hookups in addition 200 * to their GPIOBNK0 irq, with a bit less overhead. 201 * 202 * All those INTC hookups (direct, plus several IRQ banks) can also 203 * serve as EDMA event triggers. 204 */ 205 206 static void gpio_irq_disable(struct irq_data *d) 207 { 208 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 209 u32 mask = (u32) irq_data_get_irq_handler_data(d); 210 211 __raw_writel(mask, &g->clr_falling); 212 __raw_writel(mask, &g->clr_rising); 213 } 214 215 static void gpio_irq_enable(struct irq_data *d) 216 { 217 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 218 u32 mask = (u32) irq_data_get_irq_handler_data(d); 219 unsigned status = irqd_get_trigger_type(d); 220 221 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 222 if (!status) 223 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 224 225 if (status & IRQ_TYPE_EDGE_FALLING) 226 __raw_writel(mask, &g->set_falling); 227 if (status & IRQ_TYPE_EDGE_RISING) 228 __raw_writel(mask, &g->set_rising); 229 } 230 231 static int gpio_irq_type(struct irq_data *d, unsigned trigger) 232 { 233 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 234 return -EINVAL; 235 236 return 0; 237 } 238 239 static struct irq_chip gpio_irqchip = { 240 .name = "GPIO", 241 .irq_enable = gpio_irq_enable, 242 .irq_disable = gpio_irq_disable, 243 .irq_set_type = gpio_irq_type, 244 .flags = IRQCHIP_SET_TYPE_MASKED, 245 }; 246 247 static void 248 gpio_irq_handler(unsigned irq, struct irq_desc *desc) 249 { 250 struct davinci_gpio_regs __iomem *g; 251 u32 mask = 0xffff; 252 struct davinci_gpio_controller *d; 253 254 d = (struct davinci_gpio_controller *)irq_desc_get_handler_data(desc); 255 g = (struct davinci_gpio_regs __iomem *)d->regs; 256 257 /* we only care about one bank */ 258 if (irq & 1) 259 mask <<= 16; 260 261 /* temporarily mask (level sensitive) parent IRQ */ 262 desc->irq_data.chip->irq_mask(&desc->irq_data); 263 desc->irq_data.chip->irq_ack(&desc->irq_data); 264 while (1) { 265 u32 status; 266 int n; 267 int res; 268 269 /* ack any irqs */ 270 status = __raw_readl(&g->intstat) & mask; 271 if (!status) 272 break; 273 __raw_writel(status, &g->intstat); 274 275 /* now demux them to the right lowlevel handler */ 276 n = d->irq_base; 277 if (irq & 1) { 278 n += 16; 279 status >>= 16; 280 } 281 282 while (status) { 283 res = ffs(status); 284 n += res; 285 generic_handle_irq(n - 1); 286 status >>= res; 287 } 288 } 289 desc->irq_data.chip->irq_unmask(&desc->irq_data); 290 /* now it may re-trigger */ 291 } 292 293 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) 294 { 295 struct davinci_gpio_controller *d = chip2controller(chip); 296 297 if (d->irq_base >= 0) 298 return d->irq_base + offset; 299 else 300 return -ENODEV; 301 } 302 303 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) 304 { 305 struct davinci_soc_info *soc_info = &davinci_soc_info; 306 307 /* NOTE: we assume for now that only irqs in the first gpio_chip 308 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). 309 */ 310 if (offset < soc_info->gpio_unbanked) 311 return soc_info->gpio_irq + offset; 312 else 313 return -ENODEV; 314 } 315 316 static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) 317 { 318 struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); 319 u32 mask = (u32) irq_data_get_irq_handler_data(d); 320 321 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 322 return -EINVAL; 323 324 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_FALLING) 325 ? &g->set_falling : &g->clr_falling); 326 __raw_writel(mask, (trigger & IRQ_TYPE_EDGE_RISING) 327 ? &g->set_rising : &g->clr_rising); 328 329 return 0; 330 } 331 332 /* 333 * NOTE: for suspend/resume, probably best to make a platform_device with 334 * suspend_late/resume_resume calls hooking into results of the set_wake() 335 * calls ... so if no gpios are wakeup events the clock can be disabled, 336 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 337 * (dm6446) can be set appropriately for GPIOV33 pins. 338 */ 339 340 static int __init davinci_gpio_irq_setup(void) 341 { 342 unsigned gpio, irq, bank; 343 struct clk *clk; 344 u32 binten = 0; 345 unsigned ngpio, bank_irq; 346 struct davinci_soc_info *soc_info = &davinci_soc_info; 347 struct davinci_gpio_regs __iomem *g; 348 349 ngpio = soc_info->gpio_num; 350 351 bank_irq = soc_info->gpio_irq; 352 if (bank_irq == 0) { 353 printk(KERN_ERR "Don't know first GPIO bank IRQ.\n"); 354 return -EINVAL; 355 } 356 357 clk = clk_get(NULL, "gpio"); 358 if (IS_ERR(clk)) { 359 printk(KERN_ERR "Error %ld getting gpio clock?\n", 360 PTR_ERR(clk)); 361 return PTR_ERR(clk); 362 } 363 clk_enable(clk); 364 365 /* Arrange gpio_to_irq() support, handling either direct IRQs or 366 * banked IRQs. Having GPIOs in the first GPIO bank use direct 367 * IRQs, while the others use banked IRQs, would need some setup 368 * tweaks to recognize hardware which can do that. 369 */ 370 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 32) { 371 chips[bank].chip.to_irq = gpio_to_irq_banked; 372 chips[bank].irq_base = soc_info->gpio_unbanked 373 ? -EINVAL 374 : (soc_info->intc_irq_num + gpio); 375 } 376 377 /* 378 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO 379 * controller only handling trigger modes. We currently assume no 380 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. 381 */ 382 if (soc_info->gpio_unbanked) { 383 static struct irq_chip gpio_irqchip_unbanked; 384 385 /* pass "bank 0" GPIO IRQs to AINTC */ 386 chips[0].chip.to_irq = gpio_to_irq_unbanked; 387 binten = BIT(0); 388 389 /* AINTC handles mask/unmask; GPIO handles triggering */ 390 irq = bank_irq; 391 gpio_irqchip_unbanked = *irq_get_chip(irq); 392 gpio_irqchip_unbanked.name = "GPIO-AINTC"; 393 gpio_irqchip_unbanked.irq_set_type = gpio_irq_type_unbanked; 394 395 /* default trigger: both edges */ 396 g = gpio2regs(0); 397 __raw_writel(~0, &g->set_falling); 398 __raw_writel(~0, &g->set_rising); 399 400 /* set the direct IRQs up to use that irqchip */ 401 for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { 402 irq_set_chip(irq, &gpio_irqchip_unbanked); 403 irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); 404 irq_set_chip_data(irq, (__force void *)g); 405 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); 406 } 407 408 goto done; 409 } 410 411 /* 412 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we 413 * then chain through our own handler. 414 */ 415 for (gpio = 0, irq = gpio_to_irq(0), bank = 0; 416 gpio < ngpio; 417 bank++, bank_irq++) { 418 unsigned i; 419 420 /* disabled by default, enabled only as needed */ 421 g = gpio2regs(gpio); 422 __raw_writel(~0, &g->clr_falling); 423 __raw_writel(~0, &g->clr_rising); 424 425 /* set up all irqs in this bank */ 426 irq_set_chained_handler(bank_irq, gpio_irq_handler); 427 428 /* 429 * Each chip handles 32 gpios, and each irq bank consists of 16 430 * gpio irqs. Pass the irq bank's corresponding controller to 431 * the chained irq handler. 432 */ 433 irq_set_handler_data(bank_irq, &chips[gpio / 32]); 434 435 for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { 436 irq_set_chip(irq, &gpio_irqchip); 437 irq_set_chip_data(irq, (__force void *)g); 438 irq_set_handler_data(irq, (void *)__gpio_mask(gpio)); 439 irq_set_handler(irq, handle_simple_irq); 440 set_irq_flags(irq, IRQF_VALID); 441 } 442 443 binten |= BIT(bank); 444 } 445 446 done: 447 /* BINTEN -- per-bank interrupt enable. genirq would also let these 448 * bits be set/cleared dynamically. 449 */ 450 __raw_writel(binten, gpio_base + 0x08); 451 452 printk(KERN_INFO "DaVinci: %d gpio irqs\n", irq - gpio_to_irq(0)); 453 454 return 0; 455 } 456