1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * TI DaVinci GPIO Support 4 * 5 * Copyright (c) 2006-2007 David Brownell 6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com> 7 */ 8 9 #include <linux/gpio/driver.h> 10 #include <linux/errno.h> 11 #include <linux/kernel.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/platform_device.h> 22 #include <linux/platform_data/gpio-davinci.h> 23 #include <linux/irqchip/chained_irq.h> 24 #include <linux/spinlock.h> 25 #include <linux/pm_runtime.h> 26 27 #include <asm-generic/gpio.h> 28 29 #define MAX_REGS_BANKS 5 30 #define MAX_INT_PER_BANK 32 31 32 struct davinci_gpio_regs { 33 u32 dir; 34 u32 out_data; 35 u32 set_data; 36 u32 clr_data; 37 u32 in_data; 38 u32 set_rising; 39 u32 clr_rising; 40 u32 set_falling; 41 u32 clr_falling; 42 u32 intstat; 43 }; 44 45 typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq); 46 47 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */ 48 49 static void __iomem *gpio_base; 50 static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0}; 51 52 struct davinci_gpio_irq_data { 53 void __iomem *regs; 54 struct davinci_gpio_controller *chip; 55 int bank_num; 56 }; 57 58 struct davinci_gpio_controller { 59 struct gpio_chip chip; 60 struct irq_domain *irq_domain; 61 /* Serialize access to GPIO registers */ 62 spinlock_t lock; 63 void __iomem *regs[MAX_REGS_BANKS]; 64 int gpio_unbanked; 65 int irqs[MAX_INT_PER_BANK]; 66 struct davinci_gpio_regs context[MAX_REGS_BANKS]; 67 u32 binten_context; 68 }; 69 70 static inline u32 __gpio_mask(unsigned gpio) 71 { 72 return 1 << (gpio % 32); 73 } 74 75 static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d) 76 { 77 struct davinci_gpio_regs __iomem *g; 78 79 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d); 80 81 return g; 82 } 83 84 static int davinci_gpio_irq_setup(struct platform_device *pdev); 85 86 /*--------------------------------------------------------------------------*/ 87 88 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */ 89 static inline int __davinci_direction(struct gpio_chip *chip, 90 unsigned offset, bool out, int value) 91 { 92 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 93 struct davinci_gpio_regs __iomem *g; 94 unsigned long flags; 95 u32 temp; 96 int bank = offset / 32; 97 u32 mask = __gpio_mask(offset); 98 99 g = d->regs[bank]; 100 spin_lock_irqsave(&d->lock, flags); 101 temp = readl_relaxed(&g->dir); 102 if (out) { 103 temp &= ~mask; 104 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); 105 } else { 106 temp |= mask; 107 } 108 writel_relaxed(temp, &g->dir); 109 spin_unlock_irqrestore(&d->lock, flags); 110 111 return 0; 112 } 113 114 static int davinci_direction_in(struct gpio_chip *chip, unsigned offset) 115 { 116 return __davinci_direction(chip, offset, false, 0); 117 } 118 119 static int 120 davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value) 121 { 122 return __davinci_direction(chip, offset, true, value); 123 } 124 125 /* 126 * Read the pin's value (works even if it's set up as output); 127 * returns zero/nonzero. 128 * 129 * Note that changes are synched to the GPIO clock, so reading values back 130 * right after you've set them may give old values. 131 */ 132 static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset) 133 { 134 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 135 struct davinci_gpio_regs __iomem *g; 136 int bank = offset / 32; 137 138 g = d->regs[bank]; 139 140 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data)); 141 } 142 143 /* 144 * Assuming the pin is muxed as a gpio output, set its output value. 145 */ 146 static void 147 davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 148 { 149 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 150 struct davinci_gpio_regs __iomem *g; 151 int bank = offset / 32; 152 153 g = d->regs[bank]; 154 155 writel_relaxed(__gpio_mask(offset), 156 value ? &g->set_data : &g->clr_data); 157 } 158 159 static struct davinci_gpio_platform_data * 160 davinci_gpio_get_pdata(struct platform_device *pdev) 161 { 162 struct device_node *dn = pdev->dev.of_node; 163 struct davinci_gpio_platform_data *pdata; 164 int ret; 165 u32 val; 166 167 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) 168 return dev_get_platdata(&pdev->dev); 169 170 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 171 if (!pdata) 172 return NULL; 173 174 ret = of_property_read_u32(dn, "ti,ngpio", &val); 175 if (ret) 176 goto of_err; 177 178 pdata->ngpio = val; 179 180 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val); 181 if (ret) 182 goto of_err; 183 184 pdata->gpio_unbanked = val; 185 186 return pdata; 187 188 of_err: 189 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret); 190 return NULL; 191 } 192 193 static int davinci_gpio_probe(struct platform_device *pdev) 194 { 195 int bank, i, ret = 0; 196 unsigned int ngpio, nbank, nirq; 197 struct davinci_gpio_controller *chips; 198 struct davinci_gpio_platform_data *pdata; 199 struct device *dev = &pdev->dev; 200 201 pdata = davinci_gpio_get_pdata(pdev); 202 if (!pdata) { 203 dev_err(dev, "No platform data found\n"); 204 return -EINVAL; 205 } 206 207 dev->platform_data = pdata; 208 209 /* 210 * The gpio banks conceptually expose a segmented bitmap, 211 * and "ngpio" is one more than the largest zero-based 212 * bit index that's valid. 213 */ 214 ngpio = pdata->ngpio; 215 if (ngpio == 0) { 216 dev_err(dev, "How many GPIOs?\n"); 217 return -EINVAL; 218 } 219 220 if (WARN_ON(ARCH_NR_GPIOS < ngpio)) 221 ngpio = ARCH_NR_GPIOS; 222 223 /* 224 * If there are unbanked interrupts then the number of 225 * interrupts is equal to number of gpios else all are banked so 226 * number of interrupts is equal to number of banks(each with 16 gpios) 227 */ 228 if (pdata->gpio_unbanked) 229 nirq = pdata->gpio_unbanked; 230 else 231 nirq = DIV_ROUND_UP(ngpio, 16); 232 233 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL); 234 if (!chips) 235 return -ENOMEM; 236 237 gpio_base = devm_platform_ioremap_resource(pdev, 0); 238 if (IS_ERR(gpio_base)) 239 return PTR_ERR(gpio_base); 240 241 for (i = 0; i < nirq; i++) { 242 chips->irqs[i] = platform_get_irq(pdev, i); 243 if (chips->irqs[i] < 0) 244 return dev_err_probe(dev, chips->irqs[i], "IRQ not populated\n"); 245 } 246 247 chips->chip.label = dev_name(dev); 248 249 chips->chip.direction_input = davinci_direction_in; 250 chips->chip.get = davinci_gpio_get; 251 chips->chip.direction_output = davinci_direction_out; 252 chips->chip.set = davinci_gpio_set; 253 254 chips->chip.ngpio = ngpio; 255 chips->chip.base = pdata->no_auto_base ? pdata->base : -1; 256 257 #ifdef CONFIG_OF_GPIO 258 chips->chip.of_gpio_n_cells = 2; 259 chips->chip.parent = dev; 260 chips->chip.request = gpiochip_generic_request; 261 chips->chip.free = gpiochip_generic_free; 262 #endif 263 spin_lock_init(&chips->lock); 264 265 nbank = DIV_ROUND_UP(ngpio, 32); 266 for (bank = 0; bank < nbank; bank++) 267 chips->regs[bank] = gpio_base + offset_array[bank]; 268 269 ret = devm_gpiochip_add_data(dev, &chips->chip, chips); 270 if (ret) 271 return ret; 272 273 platform_set_drvdata(pdev, chips); 274 ret = davinci_gpio_irq_setup(pdev); 275 if (ret) 276 return ret; 277 278 return 0; 279 } 280 281 /*--------------------------------------------------------------------------*/ 282 /* 283 * We expect irqs will normally be set up as input pins, but they can also be 284 * used as output pins ... which is convenient for testing. 285 * 286 * NOTE: The first few GPIOs also have direct INTC hookups in addition 287 * to their GPIOBNK0 irq, with a bit less overhead. 288 * 289 * All those INTC hookups (direct, plus several IRQ banks) can also 290 * serve as EDMA event triggers. 291 */ 292 293 static void gpio_irq_disable(struct irq_data *d) 294 { 295 struct davinci_gpio_regs __iomem *g = irq2regs(d); 296 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); 297 298 writel_relaxed(mask, &g->clr_falling); 299 writel_relaxed(mask, &g->clr_rising); 300 } 301 302 static void gpio_irq_enable(struct irq_data *d) 303 { 304 struct davinci_gpio_regs __iomem *g = irq2regs(d); 305 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d); 306 unsigned status = irqd_get_trigger_type(d); 307 308 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 309 if (!status) 310 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; 311 312 if (status & IRQ_TYPE_EDGE_FALLING) 313 writel_relaxed(mask, &g->set_falling); 314 if (status & IRQ_TYPE_EDGE_RISING) 315 writel_relaxed(mask, &g->set_rising); 316 } 317 318 static int gpio_irq_type(struct irq_data *d, unsigned trigger) 319 { 320 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 321 return -EINVAL; 322 323 return 0; 324 } 325 326 static struct irq_chip gpio_irqchip = { 327 .name = "GPIO", 328 .irq_enable = gpio_irq_enable, 329 .irq_disable = gpio_irq_disable, 330 .irq_set_type = gpio_irq_type, 331 .flags = IRQCHIP_SET_TYPE_MASKED, 332 }; 333 334 static void gpio_irq_handler(struct irq_desc *desc) 335 { 336 struct davinci_gpio_regs __iomem *g; 337 u32 mask = 0xffff; 338 int bank_num; 339 struct davinci_gpio_controller *d; 340 struct davinci_gpio_irq_data *irqdata; 341 342 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc); 343 bank_num = irqdata->bank_num; 344 g = irqdata->regs; 345 d = irqdata->chip; 346 347 /* we only care about one bank */ 348 if ((bank_num % 2) == 1) 349 mask <<= 16; 350 351 /* temporarily mask (level sensitive) parent IRQ */ 352 chained_irq_enter(irq_desc_get_chip(desc), desc); 353 while (1) { 354 u32 status; 355 int bit; 356 irq_hw_number_t hw_irq; 357 358 /* ack any irqs */ 359 status = readl_relaxed(&g->intstat) & mask; 360 if (!status) 361 break; 362 writel_relaxed(status, &g->intstat); 363 364 /* now demux them to the right lowlevel handler */ 365 366 while (status) { 367 bit = __ffs(status); 368 status &= ~BIT(bit); 369 /* Max number of gpios per controller is 144 so 370 * hw_irq will be in [0..143] 371 */ 372 hw_irq = (bank_num / 2) * 32 + bit; 373 374 generic_handle_domain_irq(d->irq_domain, hw_irq); 375 } 376 } 377 chained_irq_exit(irq_desc_get_chip(desc), desc); 378 /* now it may re-trigger */ 379 } 380 381 static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset) 382 { 383 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 384 385 if (d->irq_domain) 386 return irq_create_mapping(d->irq_domain, offset); 387 else 388 return -ENXIO; 389 } 390 391 static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) 392 { 393 struct davinci_gpio_controller *d = gpiochip_get_data(chip); 394 395 /* 396 * NOTE: we assume for now that only irqs in the first gpio_chip 397 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs). 398 */ 399 if (offset < d->gpio_unbanked) 400 return d->irqs[offset]; 401 else 402 return -ENODEV; 403 } 404 405 static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger) 406 { 407 struct davinci_gpio_controller *d; 408 struct davinci_gpio_regs __iomem *g; 409 u32 mask, i; 410 411 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data); 412 g = (struct davinci_gpio_regs __iomem *)d->regs[0]; 413 for (i = 0; i < MAX_INT_PER_BANK; i++) 414 if (data->irq == d->irqs[i]) 415 break; 416 417 if (i == MAX_INT_PER_BANK) 418 return -EINVAL; 419 420 mask = __gpio_mask(i); 421 422 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 423 return -EINVAL; 424 425 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING) 426 ? &g->set_falling : &g->clr_falling); 427 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING) 428 ? &g->set_rising : &g->clr_rising); 429 430 return 0; 431 } 432 433 static int 434 davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq, 435 irq_hw_number_t hw) 436 { 437 struct davinci_gpio_controller *chips = 438 (struct davinci_gpio_controller *)d->host_data; 439 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32]; 440 441 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq, 442 "davinci_gpio"); 443 irq_set_irq_type(irq, IRQ_TYPE_NONE); 444 irq_set_chip_data(irq, (__force void *)g); 445 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw)); 446 447 return 0; 448 } 449 450 static const struct irq_domain_ops davinci_gpio_irq_ops = { 451 .map = davinci_gpio_irq_map, 452 .xlate = irq_domain_xlate_onetwocell, 453 }; 454 455 static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq) 456 { 457 static struct irq_chip_type gpio_unbanked; 458 459 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq)); 460 461 return &gpio_unbanked.chip; 462 }; 463 464 static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq) 465 { 466 static struct irq_chip gpio_unbanked; 467 468 gpio_unbanked = *irq_get_chip(irq); 469 return &gpio_unbanked; 470 }; 471 472 static const struct of_device_id davinci_gpio_ids[]; 473 474 /* 475 * NOTE: for suspend/resume, probably best to make a platform_device with 476 * suspend_late/resume_resume calls hooking into results of the set_wake() 477 * calls ... so if no gpios are wakeup events the clock can be disabled, 478 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0 479 * (dm6446) can be set appropriately for GPIOV33 pins. 480 */ 481 482 static int davinci_gpio_irq_setup(struct platform_device *pdev) 483 { 484 unsigned gpio, bank; 485 int irq; 486 int ret; 487 struct clk *clk; 488 u32 binten = 0; 489 unsigned ngpio; 490 struct device *dev = &pdev->dev; 491 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev); 492 struct davinci_gpio_platform_data *pdata = dev->platform_data; 493 struct davinci_gpio_regs __iomem *g; 494 struct irq_domain *irq_domain = NULL; 495 const struct of_device_id *match; 496 struct irq_chip *irq_chip; 497 struct davinci_gpio_irq_data *irqdata; 498 gpio_get_irq_chip_cb_t gpio_get_irq_chip; 499 500 /* 501 * Use davinci_gpio_get_irq_chip by default to handle non DT cases 502 */ 503 gpio_get_irq_chip = davinci_gpio_get_irq_chip; 504 match = of_match_device(of_match_ptr(davinci_gpio_ids), 505 dev); 506 if (match) 507 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data; 508 509 ngpio = pdata->ngpio; 510 511 clk = devm_clk_get(dev, "gpio"); 512 if (IS_ERR(clk)) { 513 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk)); 514 return PTR_ERR(clk); 515 } 516 517 ret = clk_prepare_enable(clk); 518 if (ret) 519 return ret; 520 521 if (!pdata->gpio_unbanked) { 522 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0); 523 if (irq < 0) { 524 dev_err(dev, "Couldn't allocate IRQ numbers\n"); 525 clk_disable_unprepare(clk); 526 return irq; 527 } 528 529 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0, 530 &davinci_gpio_irq_ops, 531 chips); 532 if (!irq_domain) { 533 dev_err(dev, "Couldn't register an IRQ domain\n"); 534 clk_disable_unprepare(clk); 535 return -ENODEV; 536 } 537 } 538 539 /* 540 * Arrange gpio_to_irq() support, handling either direct IRQs or 541 * banked IRQs. Having GPIOs in the first GPIO bank use direct 542 * IRQs, while the others use banked IRQs, would need some setup 543 * tweaks to recognize hardware which can do that. 544 */ 545 chips->chip.to_irq = gpio_to_irq_banked; 546 chips->irq_domain = irq_domain; 547 548 /* 549 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO 550 * controller only handling trigger modes. We currently assume no 551 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs. 552 */ 553 if (pdata->gpio_unbanked) { 554 /* pass "bank 0" GPIO IRQs to AINTC */ 555 chips->chip.to_irq = gpio_to_irq_unbanked; 556 chips->gpio_unbanked = pdata->gpio_unbanked; 557 binten = GENMASK(pdata->gpio_unbanked / 16, 0); 558 559 /* AINTC handles mask/unmask; GPIO handles triggering */ 560 irq = chips->irqs[0]; 561 irq_chip = gpio_get_irq_chip(irq); 562 irq_chip->name = "GPIO-AINTC"; 563 irq_chip->irq_set_type = gpio_irq_type_unbanked; 564 565 /* default trigger: both edges */ 566 g = chips->regs[0]; 567 writel_relaxed(~0, &g->set_falling); 568 writel_relaxed(~0, &g->set_rising); 569 570 /* set the direct IRQs up to use that irqchip */ 571 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) { 572 irq_set_chip(chips->irqs[gpio], irq_chip); 573 irq_set_handler_data(chips->irqs[gpio], chips); 574 irq_set_status_flags(chips->irqs[gpio], 575 IRQ_TYPE_EDGE_BOTH); 576 } 577 578 goto done; 579 } 580 581 /* 582 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we 583 * then chain through our own handler. 584 */ 585 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) { 586 /* disabled by default, enabled only as needed 587 * There are register sets for 32 GPIOs. 2 banks of 16 588 * GPIOs are covered by each set of registers hence divide by 2 589 */ 590 g = chips->regs[bank / 2]; 591 writel_relaxed(~0, &g->clr_falling); 592 writel_relaxed(~0, &g->clr_rising); 593 594 /* 595 * Each chip handles 32 gpios, and each irq bank consists of 16 596 * gpio irqs. Pass the irq bank's corresponding controller to 597 * the chained irq handler. 598 */ 599 irqdata = devm_kzalloc(&pdev->dev, 600 sizeof(struct 601 davinci_gpio_irq_data), 602 GFP_KERNEL); 603 if (!irqdata) { 604 clk_disable_unprepare(clk); 605 return -ENOMEM; 606 } 607 608 irqdata->regs = g; 609 irqdata->bank_num = bank; 610 irqdata->chip = chips; 611 612 irq_set_chained_handler_and_data(chips->irqs[bank], 613 gpio_irq_handler, irqdata); 614 615 binten |= BIT(bank); 616 } 617 618 done: 619 /* 620 * BINTEN -- per-bank interrupt enable. genirq would also let these 621 * bits be set/cleared dynamically. 622 */ 623 writel_relaxed(binten, gpio_base + BINTEN); 624 625 return 0; 626 } 627 628 static void davinci_gpio_save_context(struct davinci_gpio_controller *chips, 629 u32 nbank) 630 { 631 struct davinci_gpio_regs __iomem *g; 632 struct davinci_gpio_regs *context; 633 u32 bank; 634 void __iomem *base; 635 636 base = chips->regs[0] - offset_array[0]; 637 chips->binten_context = readl_relaxed(base + BINTEN); 638 639 for (bank = 0; bank < nbank; bank++) { 640 g = chips->regs[bank]; 641 context = &chips->context[bank]; 642 context->dir = readl_relaxed(&g->dir); 643 context->set_data = readl_relaxed(&g->set_data); 644 context->set_rising = readl_relaxed(&g->set_rising); 645 context->set_falling = readl_relaxed(&g->set_falling); 646 } 647 648 /* Clear Bank interrupt enable bit */ 649 writel_relaxed(0, base + BINTEN); 650 651 /* Clear all interrupt status registers */ 652 writel_relaxed(GENMASK(31, 0), &g->intstat); 653 } 654 655 static void davinci_gpio_restore_context(struct davinci_gpio_controller *chips, 656 u32 nbank) 657 { 658 struct davinci_gpio_regs __iomem *g; 659 struct davinci_gpio_regs *context; 660 u32 bank; 661 void __iomem *base; 662 663 base = chips->regs[0] - offset_array[0]; 664 665 if (readl_relaxed(base + BINTEN) != chips->binten_context) 666 writel_relaxed(chips->binten_context, base + BINTEN); 667 668 for (bank = 0; bank < nbank; bank++) { 669 g = chips->regs[bank]; 670 context = &chips->context[bank]; 671 if (readl_relaxed(&g->dir) != context->dir) 672 writel_relaxed(context->dir, &g->dir); 673 if (readl_relaxed(&g->set_data) != context->set_data) 674 writel_relaxed(context->set_data, &g->set_data); 675 if (readl_relaxed(&g->set_rising) != context->set_rising) 676 writel_relaxed(context->set_rising, &g->set_rising); 677 if (readl_relaxed(&g->set_falling) != context->set_falling) 678 writel_relaxed(context->set_falling, &g->set_falling); 679 } 680 } 681 682 static int davinci_gpio_suspend(struct device *dev) 683 { 684 struct davinci_gpio_controller *chips = dev_get_drvdata(dev); 685 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev); 686 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32); 687 688 davinci_gpio_save_context(chips, nbank); 689 690 return 0; 691 } 692 693 static int davinci_gpio_resume(struct device *dev) 694 { 695 struct davinci_gpio_controller *chips = dev_get_drvdata(dev); 696 struct davinci_gpio_platform_data *pdata = dev_get_platdata(dev); 697 u32 nbank = DIV_ROUND_UP(pdata->ngpio, 32); 698 699 davinci_gpio_restore_context(chips, nbank); 700 701 return 0; 702 } 703 704 DEFINE_SIMPLE_DEV_PM_OPS(davinci_gpio_dev_pm_ops, davinci_gpio_suspend, 705 davinci_gpio_resume); 706 707 static const struct of_device_id davinci_gpio_ids[] = { 708 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip}, 709 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip}, 710 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip}, 711 { /* sentinel */ }, 712 }; 713 MODULE_DEVICE_TABLE(of, davinci_gpio_ids); 714 715 static struct platform_driver davinci_gpio_driver = { 716 .probe = davinci_gpio_probe, 717 .driver = { 718 .name = "davinci_gpio", 719 .pm = pm_sleep_ptr(&davinci_gpio_dev_pm_ops), 720 .of_match_table = of_match_ptr(davinci_gpio_ids), 721 }, 722 }; 723 724 /** 725 * GPIO driver registration needs to be done before machine_init functions 726 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall. 727 */ 728 static int __init davinci_gpio_drv_reg(void) 729 { 730 return platform_driver_register(&davinci_gpio_driver); 731 } 732 postcore_initcall(davinci_gpio_drv_reg); 733