1 /* 2 * Copyright (C) 2015 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/bitops.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/module.h> 19 #include <linux/irqdomain.h> 20 #include <linux/irqchip/chained_irq.h> 21 #include <linux/interrupt.h> 22 #include <linux/reboot.h> 23 24 #define GIO_BANK_SIZE 0x20 25 #define GIO_ODEN(bank) (((bank) * GIO_BANK_SIZE) + 0x00) 26 #define GIO_DATA(bank) (((bank) * GIO_BANK_SIZE) + 0x04) 27 #define GIO_IODIR(bank) (((bank) * GIO_BANK_SIZE) + 0x08) 28 #define GIO_EC(bank) (((bank) * GIO_BANK_SIZE) + 0x0c) 29 #define GIO_EI(bank) (((bank) * GIO_BANK_SIZE) + 0x10) 30 #define GIO_MASK(bank) (((bank) * GIO_BANK_SIZE) + 0x14) 31 #define GIO_LEVEL(bank) (((bank) * GIO_BANK_SIZE) + 0x18) 32 #define GIO_STAT(bank) (((bank) * GIO_BANK_SIZE) + 0x1c) 33 34 struct brcmstb_gpio_bank { 35 struct list_head node; 36 int id; 37 struct gpio_chip gc; 38 struct brcmstb_gpio_priv *parent_priv; 39 u32 width; 40 struct irq_chip irq_chip; 41 }; 42 43 struct brcmstb_gpio_priv { 44 struct list_head bank_list; 45 void __iomem *reg_base; 46 struct platform_device *pdev; 47 int parent_irq; 48 int gpio_base; 49 bool can_wake; 50 int parent_wake_irq; 51 struct notifier_block reboot_notifier; 52 }; 53 54 #define MAX_GPIO_PER_BANK 32 55 #define GPIO_BANK(gpio) ((gpio) >> 5) 56 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */ 57 #define GPIO_BIT(gpio) ((gpio) & (MAX_GPIO_PER_BANK - 1)) 58 59 static inline struct brcmstb_gpio_priv * 60 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc) 61 { 62 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 63 return bank->parent_priv; 64 } 65 66 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank, 67 unsigned int offset, bool enable) 68 { 69 struct gpio_chip *gc = &bank->gc; 70 struct brcmstb_gpio_priv *priv = bank->parent_priv; 71 u32 mask = gc->pin2mask(gc, offset); 72 u32 imask; 73 unsigned long flags; 74 75 spin_lock_irqsave(&gc->bgpio_lock, flags); 76 imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id)); 77 if (enable) 78 imask |= mask; 79 else 80 imask &= ~mask; 81 gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask); 82 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 83 } 84 85 /* -------------------- IRQ chip functions -------------------- */ 86 87 static void brcmstb_gpio_irq_mask(struct irq_data *d) 88 { 89 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 90 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 91 92 brcmstb_gpio_set_imask(bank, d->hwirq, false); 93 } 94 95 static void brcmstb_gpio_irq_unmask(struct irq_data *d) 96 { 97 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 98 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 99 100 brcmstb_gpio_set_imask(bank, d->hwirq, true); 101 } 102 103 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type) 104 { 105 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 106 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 107 struct brcmstb_gpio_priv *priv = bank->parent_priv; 108 u32 mask = BIT(d->hwirq); 109 u32 edge_insensitive, iedge_insensitive; 110 u32 edge_config, iedge_config; 111 u32 level, ilevel; 112 unsigned long flags; 113 114 switch (type) { 115 case IRQ_TYPE_LEVEL_LOW: 116 level = 0; 117 edge_config = 0; 118 edge_insensitive = 0; 119 break; 120 case IRQ_TYPE_LEVEL_HIGH: 121 level = mask; 122 edge_config = 0; 123 edge_insensitive = 0; 124 break; 125 case IRQ_TYPE_EDGE_FALLING: 126 level = 0; 127 edge_config = 0; 128 edge_insensitive = 0; 129 break; 130 case IRQ_TYPE_EDGE_RISING: 131 level = 0; 132 edge_config = mask; 133 edge_insensitive = 0; 134 break; 135 case IRQ_TYPE_EDGE_BOTH: 136 level = 0; 137 edge_config = 0; /* don't care, but want known value */ 138 edge_insensitive = mask; 139 break; 140 default: 141 return -EINVAL; 142 } 143 144 spin_lock_irqsave(&bank->gc.bgpio_lock, flags); 145 146 iedge_config = bank->gc.read_reg(priv->reg_base + 147 GIO_EC(bank->id)) & ~mask; 148 iedge_insensitive = bank->gc.read_reg(priv->reg_base + 149 GIO_EI(bank->id)) & ~mask; 150 ilevel = bank->gc.read_reg(priv->reg_base + 151 GIO_LEVEL(bank->id)) & ~mask; 152 153 bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id), 154 iedge_config | edge_config); 155 bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id), 156 iedge_insensitive | edge_insensitive); 157 bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id), 158 ilevel | level); 159 160 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); 161 return 0; 162 } 163 164 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv, 165 unsigned int enable) 166 { 167 int ret = 0; 168 169 /* 170 * Only enable wake IRQ once for however many hwirqs can wake 171 * since they all use the same wake IRQ. Mask will be set 172 * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag. 173 */ 174 if (enable) 175 ret = enable_irq_wake(priv->parent_wake_irq); 176 else 177 ret = disable_irq_wake(priv->parent_wake_irq); 178 if (ret) 179 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n", 180 enable ? "enable" : "disable"); 181 return ret; 182 } 183 184 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable) 185 { 186 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 187 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); 188 189 return brcmstb_gpio_priv_set_wake(priv, enable); 190 } 191 192 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data) 193 { 194 struct brcmstb_gpio_priv *priv = data; 195 196 if (!priv || irq != priv->parent_wake_irq) 197 return IRQ_NONE; 198 pm_wakeup_event(&priv->pdev->dev, 0); 199 return IRQ_HANDLED; 200 } 201 202 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank) 203 { 204 struct brcmstb_gpio_priv *priv = bank->parent_priv; 205 struct irq_domain *irq_domain = bank->gc.irqdomain; 206 void __iomem *reg_base = priv->reg_base; 207 unsigned long status; 208 unsigned long flags; 209 210 spin_lock_irqsave(&bank->gc.bgpio_lock, flags); 211 while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) & 212 bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) { 213 int bit; 214 215 for_each_set_bit(bit, &status, 32) { 216 u32 stat = bank->gc.read_reg(reg_base + 217 GIO_STAT(bank->id)); 218 if (bit >= bank->width) 219 dev_warn(&priv->pdev->dev, 220 "IRQ for invalid GPIO (bank=%d, offset=%d)\n", 221 bank->id, bit); 222 bank->gc.write_reg(reg_base + GIO_STAT(bank->id), 223 stat | BIT(bit)); 224 generic_handle_irq(irq_find_mapping(irq_domain, bit)); 225 } 226 } 227 spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags); 228 } 229 230 /* Each UPG GIO block has one IRQ for all banks */ 231 static void brcmstb_gpio_irq_handler(struct irq_desc *desc) 232 { 233 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 234 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); 235 struct irq_chip *chip = irq_desc_get_chip(desc); 236 struct brcmstb_gpio_bank *bank; 237 238 /* Interrupts weren't properly cleared during probe */ 239 BUG_ON(!priv || !chip); 240 241 chained_irq_enter(chip, desc); 242 list_for_each_entry(bank, &priv->bank_list, node) 243 brcmstb_gpio_irq_bank_handler(bank); 244 chained_irq_exit(chip, desc); 245 } 246 247 static int brcmstb_gpio_reboot(struct notifier_block *nb, 248 unsigned long action, void *data) 249 { 250 struct brcmstb_gpio_priv *priv = 251 container_of(nb, struct brcmstb_gpio_priv, reboot_notifier); 252 253 /* Enable GPIO for S5 cold boot */ 254 if (action == SYS_POWER_OFF) 255 brcmstb_gpio_priv_set_wake(priv, 1); 256 257 return NOTIFY_DONE; 258 } 259 260 /* Make sure that the number of banks matches up between properties */ 261 static int brcmstb_gpio_sanity_check_banks(struct device *dev, 262 struct device_node *np, struct resource *res) 263 { 264 int res_num_banks = resource_size(res) / GIO_BANK_SIZE; 265 int num_banks = 266 of_property_count_u32_elems(np, "brcm,gpio-bank-widths"); 267 268 if (res_num_banks != num_banks) { 269 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n", 270 res_num_banks, num_banks); 271 return -EINVAL; 272 } else { 273 return 0; 274 } 275 } 276 277 static int brcmstb_gpio_remove(struct platform_device *pdev) 278 { 279 struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev); 280 struct brcmstb_gpio_bank *bank; 281 int ret = 0; 282 283 if (!priv) { 284 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__); 285 return -EFAULT; 286 } 287 288 /* 289 * You can lose return values below, but we report all errors, and it's 290 * more important to actually perform all of the steps. 291 */ 292 list_for_each_entry(bank, &priv->bank_list, node) 293 gpiochip_remove(&bank->gc); 294 295 if (priv->reboot_notifier.notifier_call) { 296 ret = unregister_reboot_notifier(&priv->reboot_notifier); 297 if (ret) 298 dev_err(&pdev->dev, 299 "failed to unregister reboot notifier\n"); 300 } 301 return ret; 302 } 303 304 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc, 305 const struct of_phandle_args *gpiospec, u32 *flags) 306 { 307 struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc); 308 struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc); 309 int offset; 310 311 if (gc->of_gpio_n_cells != 2) { 312 WARN_ON(1); 313 return -EINVAL; 314 } 315 316 if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells)) 317 return -EINVAL; 318 319 offset = gpiospec->args[0] - (gc->base - priv->gpio_base); 320 if (offset >= gc->ngpio || offset < 0) 321 return -EINVAL; 322 323 if (unlikely(offset >= bank->width)) { 324 dev_warn_ratelimited(&priv->pdev->dev, 325 "Received request for invalid GPIO offset %d\n", 326 gpiospec->args[0]); 327 } 328 329 if (flags) 330 *flags = gpiospec->args[1]; 331 332 return offset; 333 } 334 335 /* Before calling, must have bank->parent_irq set and gpiochip registered */ 336 static int brcmstb_gpio_irq_setup(struct platform_device *pdev, 337 struct brcmstb_gpio_bank *bank) 338 { 339 struct brcmstb_gpio_priv *priv = bank->parent_priv; 340 struct device *dev = &pdev->dev; 341 struct device_node *np = dev->of_node; 342 int err; 343 344 bank->irq_chip.name = dev_name(dev); 345 bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask; 346 bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask; 347 bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type; 348 349 /* Ensures that all non-wakeup IRQs are disabled at suspend */ 350 bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND; 351 352 if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake && 353 of_property_read_bool(np, "wakeup-source")) { 354 priv->parent_wake_irq = platform_get_irq(pdev, 1); 355 if (priv->parent_wake_irq < 0) { 356 dev_warn(dev, 357 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep"); 358 } else { 359 /* 360 * Set wakeup capability before requesting wakeup 361 * interrupt, so we can process boot-time "wakeups" 362 * (e.g., from S5 cold boot) 363 */ 364 device_set_wakeup_capable(dev, true); 365 device_wakeup_enable(dev); 366 err = devm_request_irq(dev, priv->parent_wake_irq, 367 brcmstb_gpio_wake_irq_handler, 0, 368 "brcmstb-gpio-wake", priv); 369 370 if (err < 0) { 371 dev_err(dev, "Couldn't request wake IRQ"); 372 return err; 373 } 374 375 priv->reboot_notifier.notifier_call = 376 brcmstb_gpio_reboot; 377 register_reboot_notifier(&priv->reboot_notifier); 378 priv->can_wake = true; 379 } 380 } 381 382 if (priv->can_wake) 383 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake; 384 385 err = gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0, 386 handle_simple_irq, IRQ_TYPE_NONE); 387 if (err) 388 return err; 389 gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip, 390 priv->parent_irq, brcmstb_gpio_irq_handler); 391 392 return 0; 393 } 394 395 static int brcmstb_gpio_probe(struct platform_device *pdev) 396 { 397 struct device *dev = &pdev->dev; 398 struct device_node *np = dev->of_node; 399 void __iomem *reg_base; 400 struct brcmstb_gpio_priv *priv; 401 struct resource *res; 402 struct property *prop; 403 const __be32 *p; 404 u32 bank_width; 405 int num_banks = 0; 406 int err; 407 static int gpio_base; 408 unsigned long flags = 0; 409 410 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 411 if (!priv) 412 return -ENOMEM; 413 platform_set_drvdata(pdev, priv); 414 INIT_LIST_HEAD(&priv->bank_list); 415 416 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 417 reg_base = devm_ioremap_resource(dev, res); 418 if (IS_ERR(reg_base)) 419 return PTR_ERR(reg_base); 420 421 priv->gpio_base = gpio_base; 422 priv->reg_base = reg_base; 423 priv->pdev = pdev; 424 425 if (of_property_read_bool(np, "interrupt-controller")) { 426 priv->parent_irq = platform_get_irq(pdev, 0); 427 if (priv->parent_irq <= 0) { 428 dev_err(dev, "Couldn't get IRQ"); 429 return -ENOENT; 430 } 431 } else { 432 priv->parent_irq = -ENOENT; 433 } 434 435 if (brcmstb_gpio_sanity_check_banks(dev, np, res)) 436 return -EINVAL; 437 438 /* 439 * MIPS endianness is configured by boot strap, which also reverses all 440 * bus endianness (i.e., big-endian CPU + big endian bus ==> native 441 * endian I/O). 442 * 443 * Other architectures (e.g., ARM) either do not support big endian, or 444 * else leave I/O in little endian mode. 445 */ 446 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN) 447 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; 448 #endif 449 450 of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p, 451 bank_width) { 452 struct brcmstb_gpio_bank *bank; 453 struct gpio_chip *gc; 454 455 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); 456 if (!bank) { 457 err = -ENOMEM; 458 goto fail; 459 } 460 461 bank->parent_priv = priv; 462 bank->id = num_banks; 463 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) { 464 dev_err(dev, "Invalid bank width %d\n", bank_width); 465 err = -EINVAL; 466 goto fail; 467 } else { 468 bank->width = bank_width; 469 } 470 471 /* 472 * Regs are 4 bytes wide, have data reg, no set/clear regs, 473 * and direction bits have 0 = output and 1 = input 474 */ 475 gc = &bank->gc; 476 err = bgpio_init(gc, dev, 4, 477 reg_base + GIO_DATA(bank->id), 478 NULL, NULL, NULL, 479 reg_base + GIO_IODIR(bank->id), flags); 480 if (err) { 481 dev_err(dev, "bgpio_init() failed\n"); 482 goto fail; 483 } 484 485 gc->of_node = np; 486 gc->owner = THIS_MODULE; 487 gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", dev->of_node); 488 gc->base = gpio_base; 489 gc->of_gpio_n_cells = 2; 490 gc->of_xlate = brcmstb_gpio_of_xlate; 491 /* not all ngpio lines are valid, will use bank width later */ 492 gc->ngpio = MAX_GPIO_PER_BANK; 493 494 /* 495 * Mask all interrupts by default, since wakeup interrupts may 496 * be retained from S5 cold boot 497 */ 498 gc->write_reg(reg_base + GIO_MASK(bank->id), 0); 499 500 err = gpiochip_add_data(gc, bank); 501 if (err) { 502 dev_err(dev, "Could not add gpiochip for bank %d\n", 503 bank->id); 504 goto fail; 505 } 506 gpio_base += gc->ngpio; 507 508 if (priv->parent_irq > 0) { 509 err = brcmstb_gpio_irq_setup(pdev, bank); 510 if (err) 511 goto fail; 512 } 513 514 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id, 515 gc->base, gc->ngpio, bank->width); 516 517 /* Everything looks good, so add bank to list */ 518 list_add(&bank->node, &priv->bank_list); 519 520 num_banks++; 521 } 522 523 dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n", 524 num_banks, priv->gpio_base, gpio_base - 1); 525 526 return 0; 527 528 fail: 529 (void) brcmstb_gpio_remove(pdev); 530 return err; 531 } 532 533 static const struct of_device_id brcmstb_gpio_of_match[] = { 534 { .compatible = "brcm,brcmstb-gpio" }, 535 {}, 536 }; 537 538 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match); 539 540 static struct platform_driver brcmstb_gpio_driver = { 541 .driver = { 542 .name = "brcmstb-gpio", 543 .of_match_table = brcmstb_gpio_of_match, 544 }, 545 .probe = brcmstb_gpio_probe, 546 .remove = brcmstb_gpio_remove, 547 }; 548 module_platform_driver(brcmstb_gpio_driver); 549 550 MODULE_AUTHOR("Gregory Fong"); 551 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO"); 552 MODULE_LICENSE("GPL v2"); 553