xref: /openbmc/linux/drivers/gpio/gpio-brcmstb.c (revision 2cf1c348)
1 /*
2  * Copyright (C) 2015-2017 Broadcom
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation version 2.
7  *
8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9  * kind, whether express or implied; without even the implied warranty
10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 #include <linux/bitops.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/of_device.h>
17 #include <linux/of_irq.h>
18 #include <linux/module.h>
19 #include <linux/irqdomain.h>
20 #include <linux/irqchip/chained_irq.h>
21 #include <linux/interrupt.h>
22 
23 enum gio_reg_index {
24 	GIO_REG_ODEN = 0,
25 	GIO_REG_DATA,
26 	GIO_REG_IODIR,
27 	GIO_REG_EC,
28 	GIO_REG_EI,
29 	GIO_REG_MASK,
30 	GIO_REG_LEVEL,
31 	GIO_REG_STAT,
32 	NUMBER_OF_GIO_REGISTERS
33 };
34 
35 #define GIO_BANK_SIZE           (NUMBER_OF_GIO_REGISTERS * sizeof(u32))
36 #define GIO_BANK_OFF(bank, off)	(((bank) * GIO_BANK_SIZE) + (off * sizeof(u32)))
37 #define GIO_ODEN(bank)          GIO_BANK_OFF(bank, GIO_REG_ODEN)
38 #define GIO_DATA(bank)          GIO_BANK_OFF(bank, GIO_REG_DATA)
39 #define GIO_IODIR(bank)         GIO_BANK_OFF(bank, GIO_REG_IODIR)
40 #define GIO_EC(bank)            GIO_BANK_OFF(bank, GIO_REG_EC)
41 #define GIO_EI(bank)            GIO_BANK_OFF(bank, GIO_REG_EI)
42 #define GIO_MASK(bank)          GIO_BANK_OFF(bank, GIO_REG_MASK)
43 #define GIO_LEVEL(bank)         GIO_BANK_OFF(bank, GIO_REG_LEVEL)
44 #define GIO_STAT(bank)          GIO_BANK_OFF(bank, GIO_REG_STAT)
45 
46 struct brcmstb_gpio_bank {
47 	struct list_head node;
48 	int id;
49 	struct gpio_chip gc;
50 	struct brcmstb_gpio_priv *parent_priv;
51 	u32 width;
52 	u32 wake_active;
53 	u32 saved_regs[GIO_REG_STAT]; /* Don't save and restore GIO_REG_STAT */
54 };
55 
56 struct brcmstb_gpio_priv {
57 	struct list_head bank_list;
58 	void __iomem *reg_base;
59 	struct platform_device *pdev;
60 	struct irq_domain *irq_domain;
61 	struct irq_chip irq_chip;
62 	int parent_irq;
63 	int gpio_base;
64 	int num_gpios;
65 	int parent_wake_irq;
66 };
67 
68 #define MAX_GPIO_PER_BANK       32
69 #define GPIO_BANK(gpio)         ((gpio) >> 5)
70 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
71 #define GPIO_BIT(gpio)          ((gpio) & (MAX_GPIO_PER_BANK - 1))
72 
73 static inline struct brcmstb_gpio_priv *
74 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
75 {
76 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
77 	return bank->parent_priv;
78 }
79 
80 static unsigned long
81 __brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
82 {
83 	void __iomem *reg_base = bank->parent_priv->reg_base;
84 
85 	return bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
86 	       bank->gc.read_reg(reg_base + GIO_MASK(bank->id));
87 }
88 
89 static unsigned long
90 brcmstb_gpio_get_active_irqs(struct brcmstb_gpio_bank *bank)
91 {
92 	unsigned long status;
93 	unsigned long flags;
94 
95 	spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
96 	status = __brcmstb_gpio_get_active_irqs(bank);
97 	spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
98 
99 	return status;
100 }
101 
102 static int brcmstb_gpio_hwirq_to_offset(irq_hw_number_t hwirq,
103 					struct brcmstb_gpio_bank *bank)
104 {
105 	return hwirq - (bank->gc.base - bank->parent_priv->gpio_base);
106 }
107 
108 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
109 		unsigned int hwirq, bool enable)
110 {
111 	struct gpio_chip *gc = &bank->gc;
112 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
113 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(hwirq, bank));
114 	u32 imask;
115 	unsigned long flags;
116 
117 	spin_lock_irqsave(&gc->bgpio_lock, flags);
118 	imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
119 	if (enable)
120 		imask |= mask;
121 	else
122 		imask &= ~mask;
123 	gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
124 	spin_unlock_irqrestore(&gc->bgpio_lock, flags);
125 }
126 
127 static int brcmstb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
128 {
129 	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
130 	/* gc_offset is relative to this gpio_chip; want real offset */
131 	int hwirq = offset + (gc->base - priv->gpio_base);
132 
133 	if (hwirq >= priv->num_gpios)
134 		return -ENXIO;
135 	return irq_create_mapping(priv->irq_domain, hwirq);
136 }
137 
138 /* -------------------- IRQ chip functions -------------------- */
139 
140 static void brcmstb_gpio_irq_mask(struct irq_data *d)
141 {
142 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
143 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
144 
145 	brcmstb_gpio_set_imask(bank, d->hwirq, false);
146 }
147 
148 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
149 {
150 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
151 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
152 
153 	brcmstb_gpio_set_imask(bank, d->hwirq, true);
154 }
155 
156 static void brcmstb_gpio_irq_ack(struct irq_data *d)
157 {
158 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
159 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
160 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
161 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
162 
163 	gc->write_reg(priv->reg_base + GIO_STAT(bank->id), mask);
164 }
165 
166 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
167 {
168 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
169 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
170 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
171 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
172 	u32 edge_insensitive, iedge_insensitive;
173 	u32 edge_config, iedge_config;
174 	u32 level, ilevel;
175 	unsigned long flags;
176 
177 	switch (type) {
178 	case IRQ_TYPE_LEVEL_LOW:
179 		level = mask;
180 		edge_config = 0;
181 		edge_insensitive = 0;
182 		break;
183 	case IRQ_TYPE_LEVEL_HIGH:
184 		level = mask;
185 		edge_config = mask;
186 		edge_insensitive = 0;
187 		break;
188 	case IRQ_TYPE_EDGE_FALLING:
189 		level = 0;
190 		edge_config = 0;
191 		edge_insensitive = 0;
192 		break;
193 	case IRQ_TYPE_EDGE_RISING:
194 		level = 0;
195 		edge_config = mask;
196 		edge_insensitive = 0;
197 		break;
198 	case IRQ_TYPE_EDGE_BOTH:
199 		level = 0;
200 		edge_config = 0;  /* don't care, but want known value */
201 		edge_insensitive = mask;
202 		break;
203 	default:
204 		return -EINVAL;
205 	}
206 
207 	spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
208 
209 	iedge_config = bank->gc.read_reg(priv->reg_base +
210 			GIO_EC(bank->id)) & ~mask;
211 	iedge_insensitive = bank->gc.read_reg(priv->reg_base +
212 			GIO_EI(bank->id)) & ~mask;
213 	ilevel = bank->gc.read_reg(priv->reg_base +
214 			GIO_LEVEL(bank->id)) & ~mask;
215 
216 	bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
217 			iedge_config | edge_config);
218 	bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
219 			iedge_insensitive | edge_insensitive);
220 	bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
221 			ilevel | level);
222 
223 	spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
224 	return 0;
225 }
226 
227 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
228 		unsigned int enable)
229 {
230 	int ret = 0;
231 
232 	if (enable)
233 		ret = enable_irq_wake(priv->parent_wake_irq);
234 	else
235 		ret = disable_irq_wake(priv->parent_wake_irq);
236 	if (ret)
237 		dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
238 				enable ? "enable" : "disable");
239 	return ret;
240 }
241 
242 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
243 {
244 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
245 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
246 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
247 	u32 mask = BIT(brcmstb_gpio_hwirq_to_offset(d->hwirq, bank));
248 
249 	/*
250 	 * Do not do anything specific for now, suspend/resume callbacks will
251 	 * configure the interrupt mask appropriately
252 	 */
253 	if (enable)
254 		bank->wake_active |= mask;
255 	else
256 		bank->wake_active &= ~mask;
257 
258 	return brcmstb_gpio_priv_set_wake(priv, enable);
259 }
260 
261 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
262 {
263 	struct brcmstb_gpio_priv *priv = data;
264 
265 	if (!priv || irq != priv->parent_wake_irq)
266 		return IRQ_NONE;
267 
268 	/* Nothing to do */
269 	return IRQ_HANDLED;
270 }
271 
272 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
273 {
274 	struct brcmstb_gpio_priv *priv = bank->parent_priv;
275 	struct irq_domain *domain = priv->irq_domain;
276 	int hwbase = bank->gc.base - priv->gpio_base;
277 	unsigned long status;
278 
279 	while ((status = brcmstb_gpio_get_active_irqs(bank))) {
280 		unsigned int offset;
281 
282 		for_each_set_bit(offset, &status, 32) {
283 			if (offset >= bank->width)
284 				dev_warn(&priv->pdev->dev,
285 					 "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
286 					 bank->id, offset);
287 			generic_handle_domain_irq(domain, hwbase + offset);
288 		}
289 	}
290 }
291 
292 /* Each UPG GIO block has one IRQ for all banks */
293 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
294 {
295 	struct brcmstb_gpio_priv *priv = irq_desc_get_handler_data(desc);
296 	struct irq_chip *chip = irq_desc_get_chip(desc);
297 	struct brcmstb_gpio_bank *bank;
298 
299 	/* Interrupts weren't properly cleared during probe */
300 	BUG_ON(!priv || !chip);
301 
302 	chained_irq_enter(chip, desc);
303 	list_for_each_entry(bank, &priv->bank_list, node)
304 		brcmstb_gpio_irq_bank_handler(bank);
305 	chained_irq_exit(chip, desc);
306 }
307 
308 static struct brcmstb_gpio_bank *brcmstb_gpio_hwirq_to_bank(
309 		struct brcmstb_gpio_priv *priv, irq_hw_number_t hwirq)
310 {
311 	struct brcmstb_gpio_bank *bank;
312 	int i = 0;
313 
314 	/* banks are in descending order */
315 	list_for_each_entry_reverse(bank, &priv->bank_list, node) {
316 		i += bank->gc.ngpio;
317 		if (hwirq < i)
318 			return bank;
319 	}
320 	return NULL;
321 }
322 
323 /*
324  * This lock class tells lockdep that GPIO irqs are in a different
325  * category than their parents, so it won't report false recursion.
326  */
327 static struct lock_class_key brcmstb_gpio_irq_lock_class;
328 static struct lock_class_key brcmstb_gpio_irq_request_class;
329 
330 
331 static int brcmstb_gpio_irq_map(struct irq_domain *d, unsigned int irq,
332 		irq_hw_number_t hwirq)
333 {
334 	struct brcmstb_gpio_priv *priv = d->host_data;
335 	struct brcmstb_gpio_bank *bank =
336 		brcmstb_gpio_hwirq_to_bank(priv, hwirq);
337 	struct platform_device *pdev = priv->pdev;
338 	int ret;
339 
340 	if (!bank)
341 		return -EINVAL;
342 
343 	dev_dbg(&pdev->dev, "Mapping irq %d for gpio line %d (bank %d)\n",
344 		irq, (int)hwirq, bank->id);
345 	ret = irq_set_chip_data(irq, &bank->gc);
346 	if (ret < 0)
347 		return ret;
348 	irq_set_lockdep_class(irq, &brcmstb_gpio_irq_lock_class,
349 			      &brcmstb_gpio_irq_request_class);
350 	irq_set_chip_and_handler(irq, &priv->irq_chip, handle_level_irq);
351 	irq_set_noprobe(irq);
352 	return 0;
353 }
354 
355 static void brcmstb_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
356 {
357 	irq_set_chip_and_handler(irq, NULL, NULL);
358 	irq_set_chip_data(irq, NULL);
359 }
360 
361 static const struct irq_domain_ops brcmstb_gpio_irq_domain_ops = {
362 	.map = brcmstb_gpio_irq_map,
363 	.unmap = brcmstb_gpio_irq_unmap,
364 	.xlate = irq_domain_xlate_twocell,
365 };
366 
367 /* Make sure that the number of banks matches up between properties */
368 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
369 		struct device_node *np, struct resource *res)
370 {
371 	int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
372 	int num_banks =
373 		of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
374 
375 	if (res_num_banks != num_banks) {
376 		dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
377 				res_num_banks, num_banks);
378 		return -EINVAL;
379 	} else {
380 		return 0;
381 	}
382 }
383 
384 static int brcmstb_gpio_remove(struct platform_device *pdev)
385 {
386 	struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
387 	struct brcmstb_gpio_bank *bank;
388 	int offset, ret = 0, virq;
389 
390 	if (!priv) {
391 		dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
392 		return -EFAULT;
393 	}
394 
395 	if (priv->parent_irq > 0)
396 		irq_set_chained_handler_and_data(priv->parent_irq, NULL, NULL);
397 
398 	/* Remove all IRQ mappings and delete the domain */
399 	if (priv->irq_domain) {
400 		for (offset = 0; offset < priv->num_gpios; offset++) {
401 			virq = irq_find_mapping(priv->irq_domain, offset);
402 			irq_dispose_mapping(virq);
403 		}
404 		irq_domain_remove(priv->irq_domain);
405 	}
406 
407 	/*
408 	 * You can lose return values below, but we report all errors, and it's
409 	 * more important to actually perform all of the steps.
410 	 */
411 	list_for_each_entry(bank, &priv->bank_list, node)
412 		gpiochip_remove(&bank->gc);
413 
414 	return ret;
415 }
416 
417 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
418 		const struct of_phandle_args *gpiospec, u32 *flags)
419 {
420 	struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
421 	struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
422 	int offset;
423 
424 	if (gc->of_gpio_n_cells != 2) {
425 		WARN_ON(1);
426 		return -EINVAL;
427 	}
428 
429 	if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
430 		return -EINVAL;
431 
432 	offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
433 	if (offset >= gc->ngpio || offset < 0)
434 		return -EINVAL;
435 
436 	if (unlikely(offset >= bank->width)) {
437 		dev_warn_ratelimited(&priv->pdev->dev,
438 			"Received request for invalid GPIO offset %d\n",
439 			gpiospec->args[0]);
440 	}
441 
442 	if (flags)
443 		*flags = gpiospec->args[1];
444 
445 	return offset;
446 }
447 
448 /* priv->parent_irq and priv->num_gpios must be set before calling */
449 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
450 		struct brcmstb_gpio_priv *priv)
451 {
452 	struct device *dev = &pdev->dev;
453 	struct device_node *np = dev->of_node;
454 	int err;
455 
456 	priv->irq_domain =
457 		irq_domain_add_linear(np, priv->num_gpios,
458 				      &brcmstb_gpio_irq_domain_ops,
459 				      priv);
460 	if (!priv->irq_domain) {
461 		dev_err(dev, "Couldn't allocate IRQ domain\n");
462 		return -ENXIO;
463 	}
464 
465 	if (of_property_read_bool(np, "wakeup-source")) {
466 		priv->parent_wake_irq = platform_get_irq(pdev, 1);
467 		if (priv->parent_wake_irq < 0) {
468 			priv->parent_wake_irq = 0;
469 			dev_warn(dev,
470 				"Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
471 		} else {
472 			/*
473 			 * Set wakeup capability so we can process boot-time
474 			 * "wakeups" (e.g., from S5 cold boot)
475 			 */
476 			device_set_wakeup_capable(dev, true);
477 			device_wakeup_enable(dev);
478 			err = devm_request_irq(dev, priv->parent_wake_irq,
479 					       brcmstb_gpio_wake_irq_handler,
480 					       IRQF_SHARED,
481 					       "brcmstb-gpio-wake", priv);
482 
483 			if (err < 0) {
484 				dev_err(dev, "Couldn't request wake IRQ");
485 				goto out_free_domain;
486 			}
487 		}
488 	}
489 
490 	priv->irq_chip.name = dev_name(dev);
491 	priv->irq_chip.irq_disable = brcmstb_gpio_irq_mask;
492 	priv->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
493 	priv->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
494 	priv->irq_chip.irq_ack = brcmstb_gpio_irq_ack;
495 	priv->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
496 
497 	if (priv->parent_wake_irq)
498 		priv->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
499 
500 	irq_set_chained_handler_and_data(priv->parent_irq,
501 					 brcmstb_gpio_irq_handler, priv);
502 	irq_set_status_flags(priv->parent_irq, IRQ_DISABLE_UNLAZY);
503 
504 	return 0;
505 
506 out_free_domain:
507 	irq_domain_remove(priv->irq_domain);
508 
509 	return err;
510 }
511 
512 static void brcmstb_gpio_bank_save(struct brcmstb_gpio_priv *priv,
513 				   struct brcmstb_gpio_bank *bank)
514 {
515 	struct gpio_chip *gc = &bank->gc;
516 	unsigned int i;
517 
518 	for (i = 0; i < GIO_REG_STAT; i++)
519 		bank->saved_regs[i] = gc->read_reg(priv->reg_base +
520 						   GIO_BANK_OFF(bank->id, i));
521 }
522 
523 static void brcmstb_gpio_quiesce(struct device *dev, bool save)
524 {
525 	struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
526 	struct brcmstb_gpio_bank *bank;
527 	struct gpio_chip *gc;
528 	u32 imask;
529 
530 	/* disable non-wake interrupt */
531 	if (priv->parent_irq >= 0)
532 		disable_irq(priv->parent_irq);
533 
534 	list_for_each_entry(bank, &priv->bank_list, node) {
535 		gc = &bank->gc;
536 
537 		if (save)
538 			brcmstb_gpio_bank_save(priv, bank);
539 
540 		/* Unmask GPIOs which have been flagged as wake-up sources */
541 		if (priv->parent_wake_irq)
542 			imask = bank->wake_active;
543 		else
544 			imask = 0;
545 		gc->write_reg(priv->reg_base + GIO_MASK(bank->id),
546 			       imask);
547 	}
548 }
549 
550 static void brcmstb_gpio_shutdown(struct platform_device *pdev)
551 {
552 	/* Enable GPIO for S5 cold boot */
553 	brcmstb_gpio_quiesce(&pdev->dev, false);
554 }
555 
556 #ifdef CONFIG_PM_SLEEP
557 static void brcmstb_gpio_bank_restore(struct brcmstb_gpio_priv *priv,
558 				      struct brcmstb_gpio_bank *bank)
559 {
560 	struct gpio_chip *gc = &bank->gc;
561 	unsigned int i;
562 
563 	for (i = 0; i < GIO_REG_STAT; i++)
564 		gc->write_reg(priv->reg_base + GIO_BANK_OFF(bank->id, i),
565 			      bank->saved_regs[i]);
566 }
567 
568 static int brcmstb_gpio_suspend(struct device *dev)
569 {
570 	brcmstb_gpio_quiesce(dev, true);
571 	return 0;
572 }
573 
574 static int brcmstb_gpio_resume(struct device *dev)
575 {
576 	struct brcmstb_gpio_priv *priv = dev_get_drvdata(dev);
577 	struct brcmstb_gpio_bank *bank;
578 	bool need_wakeup_event = false;
579 
580 	list_for_each_entry(bank, &priv->bank_list, node) {
581 		need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
582 		brcmstb_gpio_bank_restore(priv, bank);
583 	}
584 
585 	if (priv->parent_wake_irq && need_wakeup_event)
586 		pm_wakeup_event(dev, 0);
587 
588 	/* enable non-wake interrupt */
589 	if (priv->parent_irq >= 0)
590 		enable_irq(priv->parent_irq);
591 
592 	return 0;
593 }
594 
595 #else
596 #define brcmstb_gpio_suspend	NULL
597 #define brcmstb_gpio_resume	NULL
598 #endif /* CONFIG_PM_SLEEP */
599 
600 static const struct dev_pm_ops brcmstb_gpio_pm_ops = {
601 	.suspend_noirq	= brcmstb_gpio_suspend,
602 	.resume_noirq = brcmstb_gpio_resume,
603 };
604 
605 static int brcmstb_gpio_probe(struct platform_device *pdev)
606 {
607 	struct device *dev = &pdev->dev;
608 	struct device_node *np = dev->of_node;
609 	void __iomem *reg_base;
610 	struct brcmstb_gpio_priv *priv;
611 	struct resource *res;
612 	struct property *prop;
613 	const __be32 *p;
614 	u32 bank_width;
615 	int num_banks = 0;
616 	int err;
617 	static int gpio_base;
618 	unsigned long flags = 0;
619 	bool need_wakeup_event = false;
620 
621 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
622 	if (!priv)
623 		return -ENOMEM;
624 	platform_set_drvdata(pdev, priv);
625 	INIT_LIST_HEAD(&priv->bank_list);
626 
627 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
628 	reg_base = devm_ioremap_resource(dev, res);
629 	if (IS_ERR(reg_base))
630 		return PTR_ERR(reg_base);
631 
632 	priv->gpio_base = gpio_base;
633 	priv->reg_base = reg_base;
634 	priv->pdev = pdev;
635 
636 	if (of_property_read_bool(np, "interrupt-controller")) {
637 		priv->parent_irq = platform_get_irq(pdev, 0);
638 		if (priv->parent_irq <= 0)
639 			return -ENOENT;
640 	} else {
641 		priv->parent_irq = -ENOENT;
642 	}
643 
644 	if (brcmstb_gpio_sanity_check_banks(dev, np, res))
645 		return -EINVAL;
646 
647 	/*
648 	 * MIPS endianness is configured by boot strap, which also reverses all
649 	 * bus endianness (i.e., big-endian CPU + big endian bus ==> native
650 	 * endian I/O).
651 	 *
652 	 * Other architectures (e.g., ARM) either do not support big endian, or
653 	 * else leave I/O in little endian mode.
654 	 */
655 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
656 	flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
657 #endif
658 
659 	of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
660 			bank_width) {
661 		struct brcmstb_gpio_bank *bank;
662 		struct gpio_chip *gc;
663 
664 		/*
665 		 * If bank_width is 0, then there is an empty bank in the
666 		 * register block. Special handling for this case.
667 		 */
668 		if (bank_width == 0) {
669 			dev_dbg(dev, "Width 0 found: Empty bank @ %d\n",
670 				num_banks);
671 			num_banks++;
672 			gpio_base += MAX_GPIO_PER_BANK;
673 			continue;
674 		}
675 
676 		bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
677 		if (!bank) {
678 			err = -ENOMEM;
679 			goto fail;
680 		}
681 
682 		bank->parent_priv = priv;
683 		bank->id = num_banks;
684 		if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
685 			dev_err(dev, "Invalid bank width %d\n", bank_width);
686 			err = -EINVAL;
687 			goto fail;
688 		} else {
689 			bank->width = bank_width;
690 		}
691 
692 		/*
693 		 * Regs are 4 bytes wide, have data reg, no set/clear regs,
694 		 * and direction bits have 0 = output and 1 = input
695 		 */
696 		gc = &bank->gc;
697 		err = bgpio_init(gc, dev, 4,
698 				reg_base + GIO_DATA(bank->id),
699 				NULL, NULL, NULL,
700 				reg_base + GIO_IODIR(bank->id), flags);
701 		if (err) {
702 			dev_err(dev, "bgpio_init() failed\n");
703 			goto fail;
704 		}
705 
706 		gc->owner = THIS_MODULE;
707 		gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
708 		if (!gc->label) {
709 			err = -ENOMEM;
710 			goto fail;
711 		}
712 		gc->base = gpio_base;
713 		gc->of_gpio_n_cells = 2;
714 		gc->of_xlate = brcmstb_gpio_of_xlate;
715 		/* not all ngpio lines are valid, will use bank width later */
716 		gc->ngpio = MAX_GPIO_PER_BANK;
717 		gc->offset = bank->id * MAX_GPIO_PER_BANK;
718 		if (priv->parent_irq > 0)
719 			gc->to_irq = brcmstb_gpio_to_irq;
720 
721 		/*
722 		 * Mask all interrupts by default, since wakeup interrupts may
723 		 * be retained from S5 cold boot
724 		 */
725 		need_wakeup_event |= !!__brcmstb_gpio_get_active_irqs(bank);
726 		gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
727 
728 		err = gpiochip_add_data(gc, bank);
729 		if (err) {
730 			dev_err(dev, "Could not add gpiochip for bank %d\n",
731 					bank->id);
732 			goto fail;
733 		}
734 		gpio_base += gc->ngpio;
735 
736 		dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
737 			gc->base, gc->ngpio, bank->width);
738 
739 		/* Everything looks good, so add bank to list */
740 		list_add(&bank->node, &priv->bank_list);
741 
742 		num_banks++;
743 	}
744 
745 	priv->num_gpios = gpio_base - priv->gpio_base;
746 	if (priv->parent_irq > 0) {
747 		err = brcmstb_gpio_irq_setup(pdev, priv);
748 		if (err)
749 			goto fail;
750 	}
751 
752 	if (priv->parent_wake_irq && need_wakeup_event)
753 		pm_wakeup_event(dev, 0);
754 
755 	return 0;
756 
757 fail:
758 	(void) brcmstb_gpio_remove(pdev);
759 	return err;
760 }
761 
762 static const struct of_device_id brcmstb_gpio_of_match[] = {
763 	{ .compatible = "brcm,brcmstb-gpio" },
764 	{},
765 };
766 
767 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
768 
769 static struct platform_driver brcmstb_gpio_driver = {
770 	.driver = {
771 		.name = "brcmstb-gpio",
772 		.of_match_table = brcmstb_gpio_of_match,
773 		.pm = &brcmstb_gpio_pm_ops,
774 	},
775 	.probe = brcmstb_gpio_probe,
776 	.remove = brcmstb_gpio_remove,
777 	.shutdown = brcmstb_gpio_shutdown,
778 };
779 module_platform_driver(brcmstb_gpio_driver);
780 
781 MODULE_AUTHOR("Gregory Fong");
782 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
783 MODULE_LICENSE("GPL v2");
784