xref: /openbmc/linux/drivers/gpio/gpio-bcm-kona.c (revision bc000245)
1 /*
2  * Copyright (C) 2012-2013 Broadcom Corporation
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation version 2.
7  *
8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9  * kind, whether express or implied; without even the implied warranty
10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11  * GNU General Public License for more details.
12  */
13 
14 #include <linux/bitops.h>
15 #include <linux/err.h>
16 #include <linux/io.h>
17 #include <linux/gpio.h>
18 #include <linux/of_device.h>
19 #include <linux/of_irq.h>
20 #include <linux/module.h>
21 #include <linux/irqdomain.h>
22 #include <linux/irqchip/chained_irq.h>
23 
24 #define BCM_GPIO_PASSWD				0x00a5a501
25 #define GPIO_PER_BANK				32
26 #define GPIO_MAX_BANK_NUM			8
27 
28 #define GPIO_BANK(gpio)				((gpio) >> 5)
29 #define GPIO_BIT(gpio)				((gpio) & (GPIO_PER_BANK - 1))
30 
31 #define GPIO_OUT_STATUS(bank)			(0x00000000 + ((bank) << 2))
32 #define GPIO_IN_STATUS(bank)			(0x00000020 + ((bank) << 2))
33 #define GPIO_OUT_SET(bank)			(0x00000040 + ((bank) << 2))
34 #define GPIO_OUT_CLEAR(bank)			(0x00000060 + ((bank) << 2))
35 #define GPIO_INT_STATUS(bank)			(0x00000080 + ((bank) << 2))
36 #define GPIO_INT_MASK(bank)			(0x000000a0 + ((bank) << 2))
37 #define GPIO_INT_MSKCLR(bank)			(0x000000c0 + ((bank) << 2))
38 #define GPIO_CONTROL(bank)			(0x00000100 + ((bank) << 2))
39 #define GPIO_PWD_STATUS(bank)			(0x00000500 + ((bank) << 2))
40 
41 #define GPIO_GPPWR_OFFSET			0x00000520
42 
43 #define GPIO_GPCTR0_DBR_SHIFT			5
44 #define GPIO_GPCTR0_DBR_MASK			0x000001e0
45 
46 #define GPIO_GPCTR0_ITR_SHIFT			3
47 #define GPIO_GPCTR0_ITR_MASK			0x00000018
48 #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE		0x00000001
49 #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE	0x00000002
50 #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE		0x00000003
51 
52 #define GPIO_GPCTR0_IOTR_MASK			0x00000001
53 #define GPIO_GPCTR0_IOTR_CMD_0UTPUT		0x00000000
54 #define GPIO_GPCTR0_IOTR_CMD_INPUT		0x00000001
55 
56 #define GPIO_GPCTR0_DB_ENABLE_MASK		0x00000100
57 
58 #define LOCK_CODE				0xffffffff
59 #define UNLOCK_CODE				0x00000000
60 
61 struct bcm_kona_gpio {
62 	void __iomem *reg_base;
63 	int num_bank;
64 	spinlock_t lock;
65 	struct gpio_chip gpio_chip;
66 	struct irq_domain *irq_domain;
67 	struct bcm_kona_gpio_bank *banks;
68 	struct platform_device *pdev;
69 };
70 
71 struct bcm_kona_gpio_bank {
72 	int id;
73 	int irq;
74 	/* Used in the interrupt handler */
75 	struct bcm_kona_gpio *kona_gpio;
76 };
77 
78 static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
79 {
80 	return container_of(chip, struct bcm_kona_gpio, gpio_chip);
81 }
82 
83 static void bcm_kona_gpio_set_lockcode_bank(void __iomem *reg_base,
84 					    int bank_id, int lockcode)
85 {
86 	writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
87 	writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
88 }
89 
90 static inline void bcm_kona_gpio_lock_bank(void __iomem *reg_base, int bank_id)
91 {
92 	bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, LOCK_CODE);
93 }
94 
95 static inline void bcm_kona_gpio_unlock_bank(void __iomem *reg_base,
96 					     int bank_id)
97 {
98 	bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, UNLOCK_CODE);
99 }
100 
101 static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
102 {
103 	struct bcm_kona_gpio *kona_gpio;
104 	void __iomem *reg_base;
105 	int bank_id = GPIO_BANK(gpio);
106 	int bit = GPIO_BIT(gpio);
107 	u32 val, reg_offset;
108 	unsigned long flags;
109 
110 	kona_gpio = to_kona_gpio(chip);
111 	reg_base = kona_gpio->reg_base;
112 	spin_lock_irqsave(&kona_gpio->lock, flags);
113 	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
114 
115 	/* determine the GPIO pin direction */
116 	val = readl(reg_base + GPIO_CONTROL(gpio));
117 	val &= GPIO_GPCTR0_IOTR_MASK;
118 
119 	/* this function only applies to output pin */
120 	if (GPIO_GPCTR0_IOTR_CMD_INPUT == val)
121 		goto out;
122 
123 	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
124 
125 	val = readl(reg_base + reg_offset);
126 	val |= BIT(bit);
127 	writel(val, reg_base + reg_offset);
128 
129 out:
130 	bcm_kona_gpio_lock_bank(reg_base, bank_id);
131 	spin_unlock_irqrestore(&kona_gpio->lock, flags);
132 }
133 
134 static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
135 {
136 	struct bcm_kona_gpio *kona_gpio;
137 	void __iomem *reg_base;
138 	int bank_id = GPIO_BANK(gpio);
139 	int bit = GPIO_BIT(gpio);
140 	u32 val, reg_offset;
141 	unsigned long flags;
142 
143 	kona_gpio = to_kona_gpio(chip);
144 	reg_base = kona_gpio->reg_base;
145 	spin_lock_irqsave(&kona_gpio->lock, flags);
146 	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
147 
148 	/* determine the GPIO pin direction */
149 	val = readl(reg_base + GPIO_CONTROL(gpio));
150 	val &= GPIO_GPCTR0_IOTR_MASK;
151 
152 	/* read the GPIO bank status */
153 	reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
154 	    GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
155 	val = readl(reg_base + reg_offset);
156 
157 	bcm_kona_gpio_lock_bank(reg_base, bank_id);
158 	spin_unlock_irqrestore(&kona_gpio->lock, flags);
159 
160 	/* return the specified bit status */
161 	return !!(val & BIT(bit));
162 }
163 
164 static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
165 {
166 	struct bcm_kona_gpio *kona_gpio;
167 	void __iomem *reg_base;
168 	u32 val;
169 	unsigned long flags;
170 	int bank_id = GPIO_BANK(gpio);
171 
172 	kona_gpio = to_kona_gpio(chip);
173 	reg_base = kona_gpio->reg_base;
174 	spin_lock_irqsave(&kona_gpio->lock, flags);
175 	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
176 
177 	val = readl(reg_base + GPIO_CONTROL(gpio));
178 	val &= ~GPIO_GPCTR0_IOTR_MASK;
179 	val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
180 	writel(val, reg_base + GPIO_CONTROL(gpio));
181 
182 	bcm_kona_gpio_lock_bank(reg_base, bank_id);
183 	spin_unlock_irqrestore(&kona_gpio->lock, flags);
184 
185 	return 0;
186 }
187 
188 static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
189 					  unsigned gpio, int value)
190 {
191 	struct bcm_kona_gpio *kona_gpio;
192 	void __iomem *reg_base;
193 	int bank_id = GPIO_BANK(gpio);
194 	int bit = GPIO_BIT(gpio);
195 	u32 val, reg_offset;
196 	unsigned long flags;
197 
198 	kona_gpio = to_kona_gpio(chip);
199 	reg_base = kona_gpio->reg_base;
200 	spin_lock_irqsave(&kona_gpio->lock, flags);
201 	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
202 
203 	val = readl(reg_base + GPIO_CONTROL(gpio));
204 	val &= ~GPIO_GPCTR0_IOTR_MASK;
205 	val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
206 	writel(val, reg_base + GPIO_CONTROL(gpio));
207 	reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
208 
209 	val = readl(reg_base + reg_offset);
210 	val |= BIT(bit);
211 	writel(val, reg_base + reg_offset);
212 
213 	bcm_kona_gpio_lock_bank(reg_base, bank_id);
214 	spin_unlock_irqrestore(&kona_gpio->lock, flags);
215 
216 	return 0;
217 }
218 
219 static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
220 {
221 	struct bcm_kona_gpio *kona_gpio;
222 
223 	kona_gpio = to_kona_gpio(chip);
224 	if (gpio >= kona_gpio->gpio_chip.ngpio)
225 		return -ENXIO;
226 	return irq_create_mapping(kona_gpio->irq_domain, gpio);
227 }
228 
229 static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
230 				      unsigned debounce)
231 {
232 	struct bcm_kona_gpio *kona_gpio;
233 	void __iomem *reg_base;
234 	u32 val, res;
235 	unsigned long flags;
236 	int bank_id = GPIO_BANK(gpio);
237 
238 	kona_gpio = to_kona_gpio(chip);
239 	reg_base = kona_gpio->reg_base;
240 	/* debounce must be 1-128ms (or 0) */
241 	if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
242 		dev_err(chip->dev, "Debounce value %u not in range\n",
243 			debounce);
244 		return -EINVAL;
245 	}
246 
247 	/* calculate debounce bit value */
248 	if (debounce != 0) {
249 		/* Convert to ms */
250 		debounce /= 1000;
251 		/* find the MSB */
252 		res = fls(debounce) - 1;
253 		/* Check if MSB-1 is set (round up or down) */
254 		if (res > 0 && (debounce & BIT(res - 1)))
255 			res++;
256 	}
257 
258 	/* spin lock for read-modify-write of the GPIO register */
259 	spin_lock_irqsave(&kona_gpio->lock, flags);
260 	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
261 
262 	val = readl(reg_base + GPIO_CONTROL(gpio));
263 	val &= ~GPIO_GPCTR0_DBR_MASK;
264 
265 	if (debounce == 0) {
266 		/* disable debounce */
267 		val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
268 	} else {
269 		val |= GPIO_GPCTR0_DB_ENABLE_MASK |
270 		    (res << GPIO_GPCTR0_DBR_SHIFT);
271 	}
272 
273 	writel(val, reg_base + GPIO_CONTROL(gpio));
274 
275 	bcm_kona_gpio_lock_bank(reg_base, bank_id);
276 	spin_unlock_irqrestore(&kona_gpio->lock, flags);
277 
278 	return 0;
279 }
280 
281 static struct gpio_chip template_chip = {
282 	.label = "bcm-kona-gpio",
283 	.owner = THIS_MODULE,
284 	.direction_input = bcm_kona_gpio_direction_input,
285 	.get = bcm_kona_gpio_get,
286 	.direction_output = bcm_kona_gpio_direction_output,
287 	.set = bcm_kona_gpio_set,
288 	.set_debounce = bcm_kona_gpio_set_debounce,
289 	.to_irq = bcm_kona_gpio_to_irq,
290 	.base = 0,
291 };
292 
293 static void bcm_kona_gpio_irq_ack(struct irq_data *d)
294 {
295 	struct bcm_kona_gpio *kona_gpio;
296 	void __iomem *reg_base;
297 	int gpio = d->hwirq;
298 	int bank_id = GPIO_BANK(gpio);
299 	int bit = GPIO_BIT(gpio);
300 	u32 val;
301 	unsigned long flags;
302 
303 	kona_gpio = irq_data_get_irq_chip_data(d);
304 	reg_base = kona_gpio->reg_base;
305 	spin_lock_irqsave(&kona_gpio->lock, flags);
306 	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
307 
308 	val = readl(reg_base + GPIO_INT_STATUS(bank_id));
309 	val |= BIT(bit);
310 	writel(val, reg_base + GPIO_INT_STATUS(bank_id));
311 
312 	bcm_kona_gpio_lock_bank(reg_base, bank_id);
313 	spin_unlock_irqrestore(&kona_gpio->lock, flags);
314 }
315 
316 static void bcm_kona_gpio_irq_mask(struct irq_data *d)
317 {
318 	struct bcm_kona_gpio *kona_gpio;
319 	void __iomem *reg_base;
320 	int gpio = d->hwirq;
321 	int bank_id = GPIO_BANK(gpio);
322 	int bit = GPIO_BIT(gpio);
323 	u32 val;
324 	unsigned long flags;
325 
326 	kona_gpio = irq_data_get_irq_chip_data(d);
327 	reg_base = kona_gpio->reg_base;
328 	spin_lock_irqsave(&kona_gpio->lock, flags);
329 	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
330 
331 	val = readl(reg_base + GPIO_INT_MASK(bank_id));
332 	val |= BIT(bit);
333 	writel(val, reg_base + GPIO_INT_MASK(bank_id));
334 
335 	bcm_kona_gpio_lock_bank(reg_base, bank_id);
336 	spin_unlock_irqrestore(&kona_gpio->lock, flags);
337 }
338 
339 static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
340 {
341 	struct bcm_kona_gpio *kona_gpio;
342 	void __iomem *reg_base;
343 	int gpio = d->hwirq;
344 	int bank_id = GPIO_BANK(gpio);
345 	int bit = GPIO_BIT(gpio);
346 	u32 val;
347 	unsigned long flags;
348 
349 	kona_gpio = irq_data_get_irq_chip_data(d);
350 	reg_base = kona_gpio->reg_base;
351 	spin_lock_irqsave(&kona_gpio->lock, flags);
352 	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
353 
354 	val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
355 	val |= BIT(bit);
356 	writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
357 
358 	bcm_kona_gpio_lock_bank(reg_base, bank_id);
359 	spin_unlock_irqrestore(&kona_gpio->lock, flags);
360 }
361 
362 static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
363 {
364 	struct bcm_kona_gpio *kona_gpio;
365 	void __iomem *reg_base;
366 	int gpio = d->hwirq;
367 	u32 lvl_type;
368 	u32 val;
369 	unsigned long flags;
370 	int bank_id = GPIO_BANK(gpio);
371 
372 	kona_gpio = irq_data_get_irq_chip_data(d);
373 	reg_base = kona_gpio->reg_base;
374 	switch (type & IRQ_TYPE_SENSE_MASK) {
375 	case IRQ_TYPE_EDGE_RISING:
376 		lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
377 		break;
378 
379 	case IRQ_TYPE_EDGE_FALLING:
380 		lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
381 		break;
382 
383 	case IRQ_TYPE_EDGE_BOTH:
384 		lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
385 		break;
386 
387 	case IRQ_TYPE_LEVEL_HIGH:
388 	case IRQ_TYPE_LEVEL_LOW:
389 		/* BCM GPIO doesn't support level triggering */
390 	default:
391 		dev_err(kona_gpio->gpio_chip.dev,
392 			"Invalid BCM GPIO irq type 0x%x\n", type);
393 		return -EINVAL;
394 	}
395 
396 	spin_lock_irqsave(&kona_gpio->lock, flags);
397 	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
398 
399 	val = readl(reg_base + GPIO_CONTROL(gpio));
400 	val &= ~GPIO_GPCTR0_ITR_MASK;
401 	val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
402 	writel(val, reg_base + GPIO_CONTROL(gpio));
403 
404 	bcm_kona_gpio_lock_bank(reg_base, bank_id);
405 	spin_unlock_irqrestore(&kona_gpio->lock, flags);
406 
407 	return 0;
408 }
409 
410 static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
411 {
412 	void __iomem *reg_base;
413 	int bit, bank_id;
414 	unsigned long sta;
415 	struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq);
416 	struct irq_chip *chip = irq_desc_get_chip(desc);
417 
418 	chained_irq_enter(chip, desc);
419 
420 	/*
421 	 * For bank interrupts, we can't use chip_data to store the kona_gpio
422 	 * pointer, since GIC needs it for its own purposes. Therefore, we get
423 	 * our pointer from the bank structure.
424 	 */
425 	reg_base = bank->kona_gpio->reg_base;
426 	bank_id = bank->id;
427 	bcm_kona_gpio_unlock_bank(reg_base, bank_id);
428 
429 	while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
430 		    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
431 		for_each_set_bit(bit, &sta, 32) {
432 			int hwirq = GPIO_PER_BANK * bank_id + bit;
433 			int child_irq =
434 				irq_find_mapping(bank->kona_gpio->irq_domain,
435 						 hwirq);
436 			/*
437 			 * Clear interrupt before handler is called so we don't
438 			 * miss any interrupt occurred during executing them.
439 			 */
440 			writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
441 			       BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
442 			/* Invoke interrupt handler */
443 			generic_handle_irq(child_irq);
444 		}
445 	}
446 
447 	bcm_kona_gpio_lock_bank(reg_base, bank_id);
448 
449 	chained_irq_exit(chip, desc);
450 }
451 
452 static struct irq_chip bcm_gpio_irq_chip = {
453 	.name = "bcm-kona-gpio",
454 	.irq_ack = bcm_kona_gpio_irq_ack,
455 	.irq_mask = bcm_kona_gpio_irq_mask,
456 	.irq_unmask = bcm_kona_gpio_irq_unmask,
457 	.irq_set_type = bcm_kona_gpio_irq_set_type,
458 };
459 
460 static struct __initconst of_device_id bcm_kona_gpio_of_match[] = {
461 	{ .compatible = "brcm,kona-gpio" },
462 	{}
463 };
464 
465 MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
466 
467 /*
468  * This lock class tells lockdep that GPIO irqs are in a different
469  * category than their parents, so it won't report false recursion.
470  */
471 static struct lock_class_key gpio_lock_class;
472 
473 static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
474 				 irq_hw_number_t hwirq)
475 {
476 	int ret;
477 
478 	ret = irq_set_chip_data(irq, d->host_data);
479 	if (ret < 0)
480 		return ret;
481 	irq_set_lockdep_class(irq, &gpio_lock_class);
482 	irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
483 #ifdef CONFIG_ARM
484 	set_irq_flags(irq, IRQF_VALID);
485 #else
486 	irq_set_noprobe(irq);
487 #endif
488 
489 	return 0;
490 }
491 
492 static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
493 {
494 	irq_set_chip_and_handler(irq, NULL, NULL);
495 	irq_set_chip_data(irq, NULL);
496 }
497 
498 static struct irq_domain_ops bcm_kona_irq_ops = {
499 	.map = bcm_kona_gpio_irq_map,
500 	.unmap = bcm_kona_gpio_irq_unmap,
501 	.xlate = irq_domain_xlate_twocell,
502 };
503 
504 static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
505 {
506 	void __iomem *reg_base;
507 	int i;
508 
509 	reg_base = kona_gpio->reg_base;
510 	/* disable interrupts and clear status */
511 	for (i = 0; i < kona_gpio->num_bank; i++) {
512 		bcm_kona_gpio_unlock_bank(reg_base, i);
513 		writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
514 		writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
515 		bcm_kona_gpio_lock_bank(reg_base, i);
516 	}
517 }
518 
519 static int bcm_kona_gpio_probe(struct platform_device *pdev)
520 {
521 	struct device *dev = &pdev->dev;
522 	const struct of_device_id *match;
523 	struct resource *res;
524 	struct bcm_kona_gpio_bank *bank;
525 	struct bcm_kona_gpio *kona_gpio;
526 	struct gpio_chip *chip;
527 	int ret;
528 	int i;
529 
530 	match = of_match_device(bcm_kona_gpio_of_match, dev);
531 	if (!match) {
532 		dev_err(dev, "Failed to find gpio controller\n");
533 		return -ENODEV;
534 	}
535 
536 	kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
537 	if (!kona_gpio)
538 		return -ENOMEM;
539 
540 	kona_gpio->gpio_chip = template_chip;
541 	chip = &kona_gpio->gpio_chip;
542 	kona_gpio->num_bank = of_irq_count(dev->of_node);
543 	if (kona_gpio->num_bank == 0) {
544 		dev_err(dev, "Couldn't determine # GPIO banks\n");
545 		return -ENOENT;
546 	}
547 	if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
548 		dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
549 			GPIO_MAX_BANK_NUM);
550 		return -ENXIO;
551 	}
552 	kona_gpio->banks = devm_kzalloc(dev,
553 					kona_gpio->num_bank *
554 					sizeof(*kona_gpio->banks), GFP_KERNEL);
555 	if (!kona_gpio->banks)
556 		return -ENOMEM;
557 
558 	kona_gpio->pdev = pdev;
559 	platform_set_drvdata(pdev, kona_gpio);
560 	chip->of_node = dev->of_node;
561 	chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
562 
563 	kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
564 						      chip->ngpio,
565 						      &bcm_kona_irq_ops,
566 						      kona_gpio);
567 	if (!kona_gpio->irq_domain) {
568 		dev_err(dev, "Couldn't allocate IRQ domain\n");
569 		return -ENXIO;
570 	}
571 
572 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
573 	kona_gpio->reg_base = devm_ioremap_resource(dev, res);
574 	if (IS_ERR(kona_gpio->reg_base)) {
575 		ret = -ENXIO;
576 		goto err_irq_domain;
577 	}
578 
579 	for (i = 0; i < kona_gpio->num_bank; i++) {
580 		bank = &kona_gpio->banks[i];
581 		bank->id = i;
582 		bank->irq = platform_get_irq(pdev, i);
583 		bank->kona_gpio = kona_gpio;
584 		if (bank->irq < 0) {
585 			dev_err(dev, "Couldn't get IRQ for bank %d", i);
586 			ret = -ENOENT;
587 			goto err_irq_domain;
588 		}
589 	}
590 
591 	dev_info(&pdev->dev, "Setting up Kona GPIO\n");
592 
593 	bcm_kona_gpio_reset(kona_gpio);
594 
595 	ret = gpiochip_add(chip);
596 	if (ret < 0) {
597 		dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
598 		goto err_irq_domain;
599 	}
600 	for (i = 0; i < chip->ngpio; i++) {
601 		int irq = bcm_kona_gpio_to_irq(chip, i);
602 		irq_set_lockdep_class(irq, &gpio_lock_class);
603 		irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip,
604 					 handle_simple_irq);
605 #ifdef CONFIG_ARM
606 		set_irq_flags(irq, IRQF_VALID);
607 #else
608 		irq_set_noprobe(irq);
609 #endif
610 	}
611 	for (i = 0; i < kona_gpio->num_bank; i++) {
612 		bank = &kona_gpio->banks[i];
613 		irq_set_chained_handler(bank->irq, bcm_kona_gpio_irq_handler);
614 		irq_set_handler_data(bank->irq, bank);
615 	}
616 
617 	spin_lock_init(&kona_gpio->lock);
618 
619 	return 0;
620 
621 err_irq_domain:
622 	irq_domain_remove(kona_gpio->irq_domain);
623 
624 	return ret;
625 }
626 
627 static struct platform_driver bcm_kona_gpio_driver = {
628 	.driver = {
629 			.name = "bcm-kona-gpio",
630 			.owner = THIS_MODULE,
631 			.of_match_table = bcm_kona_gpio_of_match,
632 	},
633 	.probe = bcm_kona_gpio_probe,
634 };
635 
636 module_platform_driver(bcm_kona_gpio_driver);
637 
638 MODULE_AUTHOR("Broadcom");
639 MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
640 MODULE_LICENSE("GPL v2");
641