1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atheros AR71XX/AR724X/AR913X GPIO API support 4 * 5 * Copyright (C) 2015 Alban Bedel <albeu@free.fr> 6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com> 7 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org> 8 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org> 9 */ 10 11 #include <linux/gpio/driver.h> 12 #include <linux/platform_data/gpio-ath79.h> 13 #include <linux/of_device.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/irq.h> 17 18 #define AR71XX_GPIO_REG_OE 0x00 19 #define AR71XX_GPIO_REG_IN 0x04 20 #define AR71XX_GPIO_REG_SET 0x0c 21 #define AR71XX_GPIO_REG_CLEAR 0x10 22 23 #define AR71XX_GPIO_REG_INT_ENABLE 0x14 24 #define AR71XX_GPIO_REG_INT_TYPE 0x18 25 #define AR71XX_GPIO_REG_INT_POLARITY 0x1c 26 #define AR71XX_GPIO_REG_INT_PENDING 0x20 27 #define AR71XX_GPIO_REG_INT_MASK 0x24 28 29 struct ath79_gpio_ctrl { 30 struct gpio_chip gc; 31 void __iomem *base; 32 raw_spinlock_t lock; 33 unsigned long both_edges; 34 }; 35 36 static struct ath79_gpio_ctrl *irq_data_to_ath79_gpio(struct irq_data *data) 37 { 38 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 39 40 return container_of(gc, struct ath79_gpio_ctrl, gc); 41 } 42 43 static u32 ath79_gpio_read(struct ath79_gpio_ctrl *ctrl, unsigned reg) 44 { 45 return readl(ctrl->base + reg); 46 } 47 48 static void ath79_gpio_write(struct ath79_gpio_ctrl *ctrl, 49 unsigned reg, u32 val) 50 { 51 writel(val, ctrl->base + reg); 52 } 53 54 static bool ath79_gpio_update_bits( 55 struct ath79_gpio_ctrl *ctrl, unsigned reg, u32 mask, u32 bits) 56 { 57 u32 old_val, new_val; 58 59 old_val = ath79_gpio_read(ctrl, reg); 60 new_val = (old_val & ~mask) | (bits & mask); 61 62 if (new_val != old_val) 63 ath79_gpio_write(ctrl, reg, new_val); 64 65 return new_val != old_val; 66 } 67 68 static void ath79_gpio_irq_unmask(struct irq_data *data) 69 { 70 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 71 u32 mask = BIT(irqd_to_hwirq(data)); 72 unsigned long flags; 73 74 gpiochip_enable_irq(&ctrl->gc, irqd_to_hwirq(data)); 75 raw_spin_lock_irqsave(&ctrl->lock, flags); 76 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 77 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 78 } 79 80 static void ath79_gpio_irq_mask(struct irq_data *data) 81 { 82 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 83 u32 mask = BIT(irqd_to_hwirq(data)); 84 unsigned long flags; 85 86 raw_spin_lock_irqsave(&ctrl->lock, flags); 87 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 88 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 89 gpiochip_disable_irq(&ctrl->gc, irqd_to_hwirq(data)); 90 } 91 92 static void ath79_gpio_irq_enable(struct irq_data *data) 93 { 94 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 95 u32 mask = BIT(irqd_to_hwirq(data)); 96 unsigned long flags; 97 98 raw_spin_lock_irqsave(&ctrl->lock, flags); 99 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); 100 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, mask); 101 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 102 } 103 104 static void ath79_gpio_irq_disable(struct irq_data *data) 105 { 106 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 107 u32 mask = BIT(irqd_to_hwirq(data)); 108 unsigned long flags; 109 110 raw_spin_lock_irqsave(&ctrl->lock, flags); 111 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_MASK, mask, 0); 112 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); 113 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 114 } 115 116 static int ath79_gpio_irq_set_type(struct irq_data *data, 117 unsigned int flow_type) 118 { 119 struct ath79_gpio_ctrl *ctrl = irq_data_to_ath79_gpio(data); 120 u32 mask = BIT(irqd_to_hwirq(data)); 121 u32 type = 0, polarity = 0; 122 unsigned long flags; 123 bool disabled; 124 125 switch (flow_type) { 126 case IRQ_TYPE_EDGE_RISING: 127 polarity |= mask; 128 fallthrough; 129 case IRQ_TYPE_EDGE_FALLING: 130 case IRQ_TYPE_EDGE_BOTH: 131 break; 132 133 case IRQ_TYPE_LEVEL_HIGH: 134 polarity |= mask; 135 fallthrough; 136 case IRQ_TYPE_LEVEL_LOW: 137 type |= mask; 138 break; 139 140 default: 141 return -EINVAL; 142 } 143 144 raw_spin_lock_irqsave(&ctrl->lock, flags); 145 146 if (flow_type == IRQ_TYPE_EDGE_BOTH) { 147 ctrl->both_edges |= mask; 148 polarity = ~ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); 149 } else { 150 ctrl->both_edges &= ~mask; 151 } 152 153 /* As the IRQ configuration can't be loaded atomically we 154 * have to disable the interrupt while the configuration state 155 * is invalid. 156 */ 157 disabled = ath79_gpio_update_bits( 158 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, 0); 159 160 ath79_gpio_update_bits( 161 ctrl, AR71XX_GPIO_REG_INT_TYPE, mask, type); 162 ath79_gpio_update_bits( 163 ctrl, AR71XX_GPIO_REG_INT_POLARITY, mask, polarity); 164 165 if (disabled) 166 ath79_gpio_update_bits( 167 ctrl, AR71XX_GPIO_REG_INT_ENABLE, mask, mask); 168 169 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 170 171 return 0; 172 } 173 174 static const struct irq_chip ath79_gpio_irqchip = { 175 .name = "gpio-ath79", 176 .irq_enable = ath79_gpio_irq_enable, 177 .irq_disable = ath79_gpio_irq_disable, 178 .irq_mask = ath79_gpio_irq_mask, 179 .irq_unmask = ath79_gpio_irq_unmask, 180 .irq_set_type = ath79_gpio_irq_set_type, 181 .flags = IRQCHIP_IMMUTABLE, 182 GPIOCHIP_IRQ_RESOURCE_HELPERS, 183 }; 184 185 static void ath79_gpio_irq_handler(struct irq_desc *desc) 186 { 187 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 188 struct irq_chip *irqchip = irq_desc_get_chip(desc); 189 struct ath79_gpio_ctrl *ctrl = 190 container_of(gc, struct ath79_gpio_ctrl, gc); 191 unsigned long flags, pending; 192 u32 both_edges, state; 193 int irq; 194 195 chained_irq_enter(irqchip, desc); 196 197 raw_spin_lock_irqsave(&ctrl->lock, flags); 198 199 pending = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_INT_PENDING); 200 201 /* Update the polarity of the both edges irqs */ 202 both_edges = ctrl->both_edges & pending; 203 if (both_edges) { 204 state = ath79_gpio_read(ctrl, AR71XX_GPIO_REG_IN); 205 ath79_gpio_update_bits(ctrl, AR71XX_GPIO_REG_INT_POLARITY, 206 both_edges, ~state); 207 } 208 209 raw_spin_unlock_irqrestore(&ctrl->lock, flags); 210 211 for_each_set_bit(irq, &pending, gc->ngpio) 212 generic_handle_domain_irq(gc->irq.domain, irq); 213 214 chained_irq_exit(irqchip, desc); 215 } 216 217 static const struct of_device_id ath79_gpio_of_match[] = { 218 { .compatible = "qca,ar7100-gpio" }, 219 { .compatible = "qca,ar9340-gpio" }, 220 {}, 221 }; 222 MODULE_DEVICE_TABLE(of, ath79_gpio_of_match); 223 224 static int ath79_gpio_probe(struct platform_device *pdev) 225 { 226 struct ath79_gpio_platform_data *pdata = dev_get_platdata(&pdev->dev); 227 struct device *dev = &pdev->dev; 228 struct device_node *np = dev->of_node; 229 struct ath79_gpio_ctrl *ctrl; 230 struct gpio_irq_chip *girq; 231 u32 ath79_gpio_count; 232 bool oe_inverted; 233 int err; 234 235 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL); 236 if (!ctrl) 237 return -ENOMEM; 238 239 if (np) { 240 err = of_property_read_u32(np, "ngpios", &ath79_gpio_count); 241 if (err) { 242 dev_err(dev, "ngpios property is not valid\n"); 243 return err; 244 } 245 oe_inverted = of_device_is_compatible(np, "qca,ar9340-gpio"); 246 } else if (pdata) { 247 ath79_gpio_count = pdata->ngpios; 248 oe_inverted = pdata->oe_inverted; 249 } else { 250 dev_err(dev, "No DT node or platform data found\n"); 251 return -EINVAL; 252 } 253 254 if (ath79_gpio_count >= 32) { 255 dev_err(dev, "ngpios must be less than 32\n"); 256 return -EINVAL; 257 } 258 259 ctrl->base = devm_platform_ioremap_resource(pdev, 0); 260 if (IS_ERR(ctrl->base)) 261 return PTR_ERR(ctrl->base); 262 263 raw_spin_lock_init(&ctrl->lock); 264 err = bgpio_init(&ctrl->gc, dev, 4, 265 ctrl->base + AR71XX_GPIO_REG_IN, 266 ctrl->base + AR71XX_GPIO_REG_SET, 267 ctrl->base + AR71XX_GPIO_REG_CLEAR, 268 oe_inverted ? NULL : ctrl->base + AR71XX_GPIO_REG_OE, 269 oe_inverted ? ctrl->base + AR71XX_GPIO_REG_OE : NULL, 270 0); 271 if (err) { 272 dev_err(dev, "bgpio_init failed\n"); 273 return err; 274 } 275 /* Use base 0 to stay compatible with legacy platforms */ 276 ctrl->gc.base = 0; 277 278 /* Optional interrupt setup */ 279 if (!np || of_property_read_bool(np, "interrupt-controller")) { 280 girq = &ctrl->gc.irq; 281 gpio_irq_chip_set_chip(girq, &ath79_gpio_irqchip); 282 girq->parent_handler = ath79_gpio_irq_handler; 283 girq->num_parents = 1; 284 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 285 GFP_KERNEL); 286 if (!girq->parents) 287 return -ENOMEM; 288 girq->parents[0] = platform_get_irq(pdev, 0); 289 girq->default_type = IRQ_TYPE_NONE; 290 girq->handler = handle_simple_irq; 291 } 292 293 return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl); 294 } 295 296 static struct platform_driver ath79_gpio_driver = { 297 .driver = { 298 .name = "ath79-gpio", 299 .of_match_table = ath79_gpio_of_match, 300 }, 301 .probe = ath79_gpio_probe, 302 }; 303 304 module_platform_driver(ath79_gpio_driver); 305 306 MODULE_DESCRIPTION("Atheros AR71XX/AR724X/AR913X GPIO API support"); 307 MODULE_LICENSE("GPL v2"); 308