1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2015 IBM Corp. 4 * 5 * Joel Stanley <joel@jms.id.au> 6 */ 7 8 #include <asm/div64.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/gpio/aspeed.h> 12 #include <linux/hashtable.h> 13 #include <linux/init.h> 14 #include <linux/io.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/spinlock.h> 20 #include <linux/string.h> 21 22 /* 23 * These two headers aren't meant to be used by GPIO drivers. We need 24 * them in order to access gpio_chip_hwgpio() which we need to implement 25 * the aspeed specific API which allows the coprocessor to request 26 * access to some GPIOs and to arbitrate between coprocessor and ARM. 27 */ 28 #include <linux/gpio/consumer.h> 29 #include "gpiolib.h" 30 31 struct aspeed_bank_props { 32 unsigned int bank; 33 u32 input; 34 u32 output; 35 }; 36 37 struct aspeed_gpio_config { 38 unsigned int nr_gpios; 39 const struct aspeed_bank_props *props; 40 }; 41 42 /* 43 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled 44 * @timer_users: Tracks the number of users for each timer 45 * 46 * The @timer_users has four elements but the first element is unused. This is 47 * to simplify accounting and indexing, as a zero value in @offset_timer 48 * represents disabled debouncing for the GPIO. Any other value for an element 49 * of @offset_timer is used as an index into @timer_users. This behaviour of 50 * the zero value aligns with the behaviour of zero built from the timer 51 * configuration registers (i.e. debouncing is disabled). 52 */ 53 struct aspeed_gpio { 54 struct gpio_chip chip; 55 spinlock_t lock; 56 void __iomem *base; 57 int irq; 58 const struct aspeed_gpio_config *config; 59 60 u8 *offset_timer; 61 unsigned int timer_users[4]; 62 struct clk *clk; 63 64 u32 *dcache; 65 u8 *cf_copro_bankmap; 66 }; 67 68 struct aspeed_gpio_bank { 69 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch 70 * +4: Rd/Wr: Direction (0=in, 1=out) 71 */ 72 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */ 73 uint16_t irq_regs; 74 uint16_t debounce_regs; 75 uint16_t tolerance_regs; 76 uint16_t cmdsrc_regs; 77 const char names[4][3]; 78 }; 79 80 /* 81 * Note: The "value" register returns the input value sampled on the 82 * line even when the GPIO is configured as an output. Since 83 * that input goes through synchronizers, writing, then reading 84 * back may not return the written value right away. 85 * 86 * The "rdata" register returns the content of the write latch 87 * and thus can be used to read back what was last written 88 * reliably. 89 */ 90 91 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; 92 93 static const struct aspeed_gpio_copro_ops *copro_ops; 94 static void *copro_data; 95 96 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { 97 { 98 .val_regs = 0x0000, 99 .rdata_reg = 0x00c0, 100 .irq_regs = 0x0008, 101 .debounce_regs = 0x0040, 102 .tolerance_regs = 0x001c, 103 .cmdsrc_regs = 0x0060, 104 .names = { "A", "B", "C", "D" }, 105 }, 106 { 107 .val_regs = 0x0020, 108 .rdata_reg = 0x00c4, 109 .irq_regs = 0x0028, 110 .debounce_regs = 0x0048, 111 .tolerance_regs = 0x003c, 112 .cmdsrc_regs = 0x0068, 113 .names = { "E", "F", "G", "H" }, 114 }, 115 { 116 .val_regs = 0x0070, 117 .rdata_reg = 0x00c8, 118 .irq_regs = 0x0098, 119 .debounce_regs = 0x00b0, 120 .tolerance_regs = 0x00ac, 121 .cmdsrc_regs = 0x0090, 122 .names = { "I", "J", "K", "L" }, 123 }, 124 { 125 .val_regs = 0x0078, 126 .rdata_reg = 0x00cc, 127 .irq_regs = 0x00e8, 128 .debounce_regs = 0x0100, 129 .tolerance_regs = 0x00fc, 130 .cmdsrc_regs = 0x00e0, 131 .names = { "M", "N", "O", "P" }, 132 }, 133 { 134 .val_regs = 0x0080, 135 .rdata_reg = 0x00d0, 136 .irq_regs = 0x0118, 137 .debounce_regs = 0x0130, 138 .tolerance_regs = 0x012c, 139 .cmdsrc_regs = 0x0110, 140 .names = { "Q", "R", "S", "T" }, 141 }, 142 { 143 .val_regs = 0x0088, 144 .rdata_reg = 0x00d4, 145 .irq_regs = 0x0148, 146 .debounce_regs = 0x0160, 147 .tolerance_regs = 0x015c, 148 .cmdsrc_regs = 0x0140, 149 .names = { "U", "V", "W", "X" }, 150 }, 151 { 152 .val_regs = 0x01E0, 153 .rdata_reg = 0x00d8, 154 .irq_regs = 0x0178, 155 .debounce_regs = 0x0190, 156 .tolerance_regs = 0x018c, 157 .cmdsrc_regs = 0x0170, 158 .names = { "Y", "Z", "AA", "AB" }, 159 }, 160 { 161 .val_regs = 0x01e8, 162 .rdata_reg = 0x00dc, 163 .irq_regs = 0x01a8, 164 .debounce_regs = 0x01c0, 165 .tolerance_regs = 0x01bc, 166 .cmdsrc_regs = 0x01a0, 167 .names = { "AC", "", "", "" }, 168 }, 169 }; 170 171 enum aspeed_gpio_reg { 172 reg_val, 173 reg_rdata, 174 reg_dir, 175 reg_irq_enable, 176 reg_irq_type0, 177 reg_irq_type1, 178 reg_irq_type2, 179 reg_irq_status, 180 reg_debounce_sel1, 181 reg_debounce_sel2, 182 reg_tolerance, 183 reg_cmdsrc0, 184 reg_cmdsrc1, 185 }; 186 187 #define GPIO_VAL_VALUE 0x00 188 #define GPIO_VAL_DIR 0x04 189 190 #define GPIO_IRQ_ENABLE 0x00 191 #define GPIO_IRQ_TYPE0 0x04 192 #define GPIO_IRQ_TYPE1 0x08 193 #define GPIO_IRQ_TYPE2 0x0c 194 #define GPIO_IRQ_STATUS 0x10 195 196 #define GPIO_DEBOUNCE_SEL1 0x00 197 #define GPIO_DEBOUNCE_SEL2 0x04 198 199 #define GPIO_CMDSRC_0 0x00 200 #define GPIO_CMDSRC_1 0x04 201 #define GPIO_CMDSRC_ARM 0 202 #define GPIO_CMDSRC_LPC 1 203 #define GPIO_CMDSRC_COLDFIRE 2 204 #define GPIO_CMDSRC_RESERVED 3 205 206 /* This will be resolved at compile time */ 207 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, 208 const struct aspeed_gpio_bank *bank, 209 const enum aspeed_gpio_reg reg) 210 { 211 switch (reg) { 212 case reg_val: 213 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; 214 case reg_rdata: 215 return gpio->base + bank->rdata_reg; 216 case reg_dir: 217 return gpio->base + bank->val_regs + GPIO_VAL_DIR; 218 case reg_irq_enable: 219 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; 220 case reg_irq_type0: 221 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; 222 case reg_irq_type1: 223 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; 224 case reg_irq_type2: 225 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; 226 case reg_irq_status: 227 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; 228 case reg_debounce_sel1: 229 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; 230 case reg_debounce_sel2: 231 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; 232 case reg_tolerance: 233 return gpio->base + bank->tolerance_regs; 234 case reg_cmdsrc0: 235 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; 236 case reg_cmdsrc1: 237 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; 238 } 239 BUG(); 240 } 241 242 #define GPIO_BANK(x) ((x) >> 5) 243 #define GPIO_OFFSET(x) ((x) & 0x1f) 244 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) 245 246 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o)) 247 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1) 248 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0) 249 250 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) 251 { 252 unsigned int bank = GPIO_BANK(offset); 253 254 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); 255 return &aspeed_gpio_banks[bank]; 256 } 257 258 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) 259 { 260 return !(props->input || props->output); 261 } 262 263 static inline const struct aspeed_bank_props *find_bank_props( 264 struct aspeed_gpio *gpio, unsigned int offset) 265 { 266 const struct aspeed_bank_props *props = gpio->config->props; 267 268 while (!is_bank_props_sentinel(props)) { 269 if (props->bank == GPIO_BANK(offset)) 270 return props; 271 props++; 272 } 273 274 return NULL; 275 } 276 277 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) 278 { 279 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 280 const struct aspeed_gpio_bank *bank = to_bank(offset); 281 unsigned int group = GPIO_OFFSET(offset) / 8; 282 283 return bank->names[group][0] != '\0' && 284 (!props || ((props->input | props->output) & GPIO_BIT(offset))); 285 } 286 287 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) 288 { 289 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 290 291 return !props || (props->input & GPIO_BIT(offset)); 292 } 293 294 #define have_irq(g, o) have_input((g), (o)) 295 #define have_debounce(g, o) have_input((g), (o)) 296 297 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) 298 { 299 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 300 301 return !props || (props->output & GPIO_BIT(offset)); 302 } 303 304 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, 305 const struct aspeed_gpio_bank *bank, 306 int bindex, int cmdsrc) 307 { 308 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0); 309 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1); 310 u32 bit, reg; 311 312 /* 313 * Each register controls 4 banks, so take the bottom 2 314 * bits of the bank index, and use them to select the 315 * right control bit (0, 8, 16 or 24). 316 */ 317 bit = BIT((bindex & 3) << 3); 318 319 /* Source 1 first to avoid illegal 11 combination */ 320 reg = ioread32(c1); 321 if (cmdsrc & 2) 322 reg |= bit; 323 else 324 reg &= ~bit; 325 iowrite32(reg, c1); 326 327 /* Then Source 0 */ 328 reg = ioread32(c0); 329 if (cmdsrc & 1) 330 reg |= bit; 331 else 332 reg &= ~bit; 333 iowrite32(reg, c0); 334 } 335 336 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, 337 unsigned int offset) 338 { 339 const struct aspeed_gpio_bank *bank = to_bank(offset); 340 341 if (!copro_ops || !gpio->cf_copro_bankmap) 342 return false; 343 if (!gpio->cf_copro_bankmap[offset >> 3]) 344 return false; 345 if (!copro_ops->request_access) 346 return false; 347 348 /* Pause the coprocessor */ 349 copro_ops->request_access(copro_data); 350 351 /* Change command source back to ARM */ 352 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM); 353 354 /* Update cache */ 355 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); 356 357 return true; 358 } 359 360 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, 361 unsigned int offset) 362 { 363 const struct aspeed_gpio_bank *bank = to_bank(offset); 364 365 if (!copro_ops || !gpio->cf_copro_bankmap) 366 return; 367 if (!gpio->cf_copro_bankmap[offset >> 3]) 368 return; 369 if (!copro_ops->release_access) 370 return; 371 372 /* Change command source back to ColdFire */ 373 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, 374 GPIO_CMDSRC_COLDFIRE); 375 376 /* Restart the coprocessor */ 377 copro_ops->release_access(copro_data); 378 } 379 380 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) 381 { 382 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 383 const struct aspeed_gpio_bank *bank = to_bank(offset); 384 385 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); 386 } 387 388 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 389 int val) 390 { 391 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 392 const struct aspeed_gpio_bank *bank = to_bank(offset); 393 void __iomem *addr; 394 u32 reg; 395 396 addr = bank_reg(gpio, bank, reg_val); 397 reg = gpio->dcache[GPIO_BANK(offset)]; 398 399 if (val) 400 reg |= GPIO_BIT(offset); 401 else 402 reg &= ~GPIO_BIT(offset); 403 gpio->dcache[GPIO_BANK(offset)] = reg; 404 405 iowrite32(reg, addr); 406 } 407 408 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 409 int val) 410 { 411 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 412 unsigned long flags; 413 bool copro; 414 415 spin_lock_irqsave(&gpio->lock, flags); 416 copro = aspeed_gpio_copro_request(gpio, offset); 417 418 __aspeed_gpio_set(gc, offset, val); 419 420 if (copro) 421 aspeed_gpio_copro_release(gpio, offset); 422 spin_unlock_irqrestore(&gpio->lock, flags); 423 } 424 425 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 426 { 427 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 428 const struct aspeed_gpio_bank *bank = to_bank(offset); 429 void __iomem *addr = bank_reg(gpio, bank, reg_dir); 430 unsigned long flags; 431 bool copro; 432 u32 reg; 433 434 if (!have_input(gpio, offset)) 435 return -ENOTSUPP; 436 437 spin_lock_irqsave(&gpio->lock, flags); 438 439 reg = ioread32(addr); 440 reg &= ~GPIO_BIT(offset); 441 442 copro = aspeed_gpio_copro_request(gpio, offset); 443 iowrite32(reg, addr); 444 if (copro) 445 aspeed_gpio_copro_release(gpio, offset); 446 447 spin_unlock_irqrestore(&gpio->lock, flags); 448 449 return 0; 450 } 451 452 static int aspeed_gpio_dir_out(struct gpio_chip *gc, 453 unsigned int offset, int val) 454 { 455 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 456 const struct aspeed_gpio_bank *bank = to_bank(offset); 457 void __iomem *addr = bank_reg(gpio, bank, reg_dir); 458 unsigned long flags; 459 bool copro; 460 u32 reg; 461 462 if (!have_output(gpio, offset)) 463 return -ENOTSUPP; 464 465 spin_lock_irqsave(&gpio->lock, flags); 466 467 reg = ioread32(addr); 468 reg |= GPIO_BIT(offset); 469 470 copro = aspeed_gpio_copro_request(gpio, offset); 471 __aspeed_gpio_set(gc, offset, val); 472 iowrite32(reg, addr); 473 474 if (copro) 475 aspeed_gpio_copro_release(gpio, offset); 476 spin_unlock_irqrestore(&gpio->lock, flags); 477 478 return 0; 479 } 480 481 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 482 { 483 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 484 const struct aspeed_gpio_bank *bank = to_bank(offset); 485 unsigned long flags; 486 u32 val; 487 488 if (!have_input(gpio, offset)) 489 return 0; 490 491 if (!have_output(gpio, offset)) 492 return 1; 493 494 spin_lock_irqsave(&gpio->lock, flags); 495 496 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); 497 498 spin_unlock_irqrestore(&gpio->lock, flags); 499 500 return !val; 501 502 } 503 504 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, 505 struct aspeed_gpio **gpio, 506 const struct aspeed_gpio_bank **bank, 507 u32 *bit, int *offset) 508 { 509 struct aspeed_gpio *internal; 510 511 *offset = irqd_to_hwirq(d); 512 513 internal = irq_data_get_irq_chip_data(d); 514 515 /* This might be a bit of a questionable place to check */ 516 if (!have_irq(internal, *offset)) 517 return -ENOTSUPP; 518 519 *gpio = internal; 520 *bank = to_bank(*offset); 521 *bit = GPIO_BIT(*offset); 522 523 return 0; 524 } 525 526 static void aspeed_gpio_irq_ack(struct irq_data *d) 527 { 528 const struct aspeed_gpio_bank *bank; 529 struct aspeed_gpio *gpio; 530 unsigned long flags; 531 void __iomem *status_addr; 532 int rc, offset; 533 bool copro; 534 u32 bit; 535 536 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 537 if (rc) 538 return; 539 540 status_addr = bank_reg(gpio, bank, reg_irq_status); 541 542 spin_lock_irqsave(&gpio->lock, flags); 543 copro = aspeed_gpio_copro_request(gpio, offset); 544 545 iowrite32(bit, status_addr); 546 547 if (copro) 548 aspeed_gpio_copro_release(gpio, offset); 549 spin_unlock_irqrestore(&gpio->lock, flags); 550 } 551 552 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) 553 { 554 const struct aspeed_gpio_bank *bank; 555 struct aspeed_gpio *gpio; 556 unsigned long flags; 557 u32 reg, bit; 558 void __iomem *addr; 559 int rc, offset; 560 bool copro; 561 562 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 563 if (rc) 564 return; 565 566 addr = bank_reg(gpio, bank, reg_irq_enable); 567 568 spin_lock_irqsave(&gpio->lock, flags); 569 copro = aspeed_gpio_copro_request(gpio, offset); 570 571 reg = ioread32(addr); 572 if (set) 573 reg |= bit; 574 else 575 reg &= ~bit; 576 iowrite32(reg, addr); 577 578 if (copro) 579 aspeed_gpio_copro_release(gpio, offset); 580 spin_unlock_irqrestore(&gpio->lock, flags); 581 } 582 583 static void aspeed_gpio_irq_mask(struct irq_data *d) 584 { 585 aspeed_gpio_irq_set_mask(d, false); 586 } 587 588 static void aspeed_gpio_irq_unmask(struct irq_data *d) 589 { 590 aspeed_gpio_irq_set_mask(d, true); 591 } 592 593 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) 594 { 595 u32 type0 = 0; 596 u32 type1 = 0; 597 u32 type2 = 0; 598 u32 bit, reg; 599 const struct aspeed_gpio_bank *bank; 600 irq_flow_handler_t handler; 601 struct aspeed_gpio *gpio; 602 unsigned long flags; 603 void __iomem *addr; 604 int rc, offset; 605 bool copro; 606 607 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 608 if (rc) 609 return -EINVAL; 610 611 switch (type & IRQ_TYPE_SENSE_MASK) { 612 case IRQ_TYPE_EDGE_BOTH: 613 type2 |= bit; 614 /* fall through */ 615 case IRQ_TYPE_EDGE_RISING: 616 type0 |= bit; 617 /* fall through */ 618 case IRQ_TYPE_EDGE_FALLING: 619 handler = handle_edge_irq; 620 break; 621 case IRQ_TYPE_LEVEL_HIGH: 622 type0 |= bit; 623 /* fall through */ 624 case IRQ_TYPE_LEVEL_LOW: 625 type1 |= bit; 626 handler = handle_level_irq; 627 break; 628 default: 629 return -EINVAL; 630 } 631 632 spin_lock_irqsave(&gpio->lock, flags); 633 copro = aspeed_gpio_copro_request(gpio, offset); 634 635 addr = bank_reg(gpio, bank, reg_irq_type0); 636 reg = ioread32(addr); 637 reg = (reg & ~bit) | type0; 638 iowrite32(reg, addr); 639 640 addr = bank_reg(gpio, bank, reg_irq_type1); 641 reg = ioread32(addr); 642 reg = (reg & ~bit) | type1; 643 iowrite32(reg, addr); 644 645 addr = bank_reg(gpio, bank, reg_irq_type2); 646 reg = ioread32(addr); 647 reg = (reg & ~bit) | type2; 648 iowrite32(reg, addr); 649 650 if (copro) 651 aspeed_gpio_copro_release(gpio, offset); 652 spin_unlock_irqrestore(&gpio->lock, flags); 653 654 irq_set_handler_locked(d, handler); 655 656 return 0; 657 } 658 659 static void aspeed_gpio_irq_handler(struct irq_desc *desc) 660 { 661 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 662 struct irq_chip *ic = irq_desc_get_chip(desc); 663 struct aspeed_gpio *data = gpiochip_get_data(gc); 664 unsigned int i, p, girq; 665 unsigned long reg; 666 667 chained_irq_enter(ic, desc); 668 669 for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) { 670 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 671 672 reg = ioread32(bank_reg(data, bank, reg_irq_status)); 673 674 for_each_set_bit(p, ®, 32) { 675 girq = irq_find_mapping(gc->irq.domain, i * 32 + p); 676 generic_handle_irq(girq); 677 } 678 679 } 680 681 chained_irq_exit(ic, desc); 682 } 683 684 static struct irq_chip aspeed_gpio_irqchip = { 685 .name = "aspeed-gpio", 686 .irq_ack = aspeed_gpio_irq_ack, 687 .irq_mask = aspeed_gpio_irq_mask, 688 .irq_unmask = aspeed_gpio_irq_unmask, 689 .irq_set_type = aspeed_gpio_set_type, 690 }; 691 692 static void set_irq_valid_mask(struct aspeed_gpio *gpio) 693 { 694 const struct aspeed_bank_props *props = gpio->config->props; 695 696 while (!is_bank_props_sentinel(props)) { 697 unsigned int offset; 698 const unsigned long int input = props->input; 699 700 /* Pretty crummy approach, but similar to GPIO core */ 701 for_each_clear_bit(offset, &input, 32) { 702 unsigned int i = props->bank * 32 + offset; 703 704 if (i >= gpio->config->nr_gpios) 705 break; 706 707 clear_bit(i, gpio->chip.irq.valid_mask); 708 } 709 710 props++; 711 } 712 } 713 714 static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, 715 struct platform_device *pdev) 716 { 717 int rc; 718 719 rc = platform_get_irq(pdev, 0); 720 if (rc < 0) 721 return rc; 722 723 gpio->irq = rc; 724 725 set_irq_valid_mask(gpio); 726 727 rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip, 728 0, handle_bad_irq, IRQ_TYPE_NONE); 729 if (rc) { 730 dev_info(&pdev->dev, "Could not add irqchip\n"); 731 return rc; 732 } 733 734 gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip, 735 gpio->irq, aspeed_gpio_irq_handler); 736 737 return 0; 738 } 739 740 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, 741 unsigned int offset, bool enable) 742 { 743 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 744 unsigned long flags; 745 void __iomem *treg; 746 bool copro; 747 u32 val; 748 749 treg = bank_reg(gpio, to_bank(offset), reg_tolerance); 750 751 spin_lock_irqsave(&gpio->lock, flags); 752 copro = aspeed_gpio_copro_request(gpio, offset); 753 754 val = readl(treg); 755 756 if (enable) 757 val |= GPIO_BIT(offset); 758 else 759 val &= ~GPIO_BIT(offset); 760 761 writel(val, treg); 762 763 if (copro) 764 aspeed_gpio_copro_release(gpio, offset); 765 spin_unlock_irqrestore(&gpio->lock, flags); 766 767 return 0; 768 } 769 770 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) 771 { 772 if (!have_gpio(gpiochip_get_data(chip), offset)) 773 return -ENODEV; 774 775 return pinctrl_gpio_request(chip->base + offset); 776 } 777 778 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) 779 { 780 pinctrl_gpio_free(chip->base + offset); 781 } 782 783 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, 784 u32 *cycles) 785 { 786 u64 rate; 787 u64 n; 788 u32 r; 789 790 rate = clk_get_rate(gpio->clk); 791 if (!rate) 792 return -ENOTSUPP; 793 794 n = rate * usecs; 795 r = do_div(n, 1000000); 796 797 if (n >= U32_MAX) 798 return -ERANGE; 799 800 /* At least as long as the requested time */ 801 *cycles = n + (!!r); 802 803 return 0; 804 } 805 806 /* Call under gpio->lock */ 807 static int register_allocated_timer(struct aspeed_gpio *gpio, 808 unsigned int offset, unsigned int timer) 809 { 810 if (WARN(gpio->offset_timer[offset] != 0, 811 "Offset %d already allocated timer %d\n", 812 offset, gpio->offset_timer[offset])) 813 return -EINVAL; 814 815 if (WARN(gpio->timer_users[timer] == UINT_MAX, 816 "Timer user count would overflow\n")) 817 return -EPERM; 818 819 gpio->offset_timer[offset] = timer; 820 gpio->timer_users[timer]++; 821 822 return 0; 823 } 824 825 /* Call under gpio->lock */ 826 static int unregister_allocated_timer(struct aspeed_gpio *gpio, 827 unsigned int offset) 828 { 829 if (WARN(gpio->offset_timer[offset] == 0, 830 "No timer allocated to offset %d\n", offset)) 831 return -EINVAL; 832 833 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, 834 "No users recorded for timer %d\n", 835 gpio->offset_timer[offset])) 836 return -EINVAL; 837 838 gpio->timer_users[gpio->offset_timer[offset]]--; 839 gpio->offset_timer[offset] = 0; 840 841 return 0; 842 } 843 844 /* Call under gpio->lock */ 845 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, 846 unsigned int offset) 847 { 848 return gpio->offset_timer[offset] > 0; 849 } 850 851 /* Call under gpio->lock */ 852 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, 853 unsigned int timer) 854 { 855 const struct aspeed_gpio_bank *bank = to_bank(offset); 856 const u32 mask = GPIO_BIT(offset); 857 void __iomem *addr; 858 u32 val; 859 860 /* Note: Debounce timer isn't under control of the command 861 * source registers, so no need to sync with the coprocessor 862 */ 863 addr = bank_reg(gpio, bank, reg_debounce_sel1); 864 val = ioread32(addr); 865 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); 866 867 addr = bank_reg(gpio, bank, reg_debounce_sel2); 868 val = ioread32(addr); 869 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); 870 } 871 872 static int enable_debounce(struct gpio_chip *chip, unsigned int offset, 873 unsigned long usecs) 874 { 875 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 876 u32 requested_cycles; 877 unsigned long flags; 878 int rc; 879 int i; 880 881 if (!gpio->clk) 882 return -EINVAL; 883 884 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); 885 if (rc < 0) { 886 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", 887 usecs, clk_get_rate(gpio->clk), rc); 888 return rc; 889 } 890 891 spin_lock_irqsave(&gpio->lock, flags); 892 893 if (timer_allocation_registered(gpio, offset)) { 894 rc = unregister_allocated_timer(gpio, offset); 895 if (rc < 0) 896 goto out; 897 } 898 899 /* Try to find a timer already configured for the debounce period */ 900 for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) { 901 u32 cycles; 902 903 cycles = ioread32(gpio->base + debounce_timers[i]); 904 if (requested_cycles == cycles) 905 break; 906 } 907 908 if (i == ARRAY_SIZE(debounce_timers)) { 909 int j; 910 911 /* 912 * As there are no timers configured for the requested debounce 913 * period, find an unused timer instead 914 */ 915 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { 916 if (gpio->timer_users[j] == 0) 917 break; 918 } 919 920 if (j == ARRAY_SIZE(gpio->timer_users)) { 921 dev_warn(chip->parent, 922 "Debounce timers exhausted, cannot debounce for period %luus\n", 923 usecs); 924 925 rc = -EPERM; 926 927 /* 928 * We already adjusted the accounting to remove @offset 929 * as a user of its previous timer, so also configure 930 * the hardware so @offset has timers disabled for 931 * consistency. 932 */ 933 configure_timer(gpio, offset, 0); 934 goto out; 935 } 936 937 i = j; 938 939 iowrite32(requested_cycles, gpio->base + debounce_timers[i]); 940 } 941 942 if (WARN(i == 0, "Cannot register index of disabled timer\n")) { 943 rc = -EINVAL; 944 goto out; 945 } 946 947 register_allocated_timer(gpio, offset, i); 948 configure_timer(gpio, offset, i); 949 950 out: 951 spin_unlock_irqrestore(&gpio->lock, flags); 952 953 return rc; 954 } 955 956 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) 957 { 958 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 959 unsigned long flags; 960 int rc; 961 962 spin_lock_irqsave(&gpio->lock, flags); 963 964 rc = unregister_allocated_timer(gpio, offset); 965 if (!rc) 966 configure_timer(gpio, offset, 0); 967 968 spin_unlock_irqrestore(&gpio->lock, flags); 969 970 return rc; 971 } 972 973 static int set_debounce(struct gpio_chip *chip, unsigned int offset, 974 unsigned long usecs) 975 { 976 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 977 978 if (!have_debounce(gpio, offset)) 979 return -ENOTSUPP; 980 981 if (usecs) 982 return enable_debounce(chip, offset, usecs); 983 984 return disable_debounce(chip, offset); 985 } 986 987 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 988 unsigned long config) 989 { 990 unsigned long param = pinconf_to_config_param(config); 991 u32 arg = pinconf_to_config_argument(config); 992 993 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 994 return set_debounce(chip, offset, arg); 995 else if (param == PIN_CONFIG_BIAS_DISABLE || 996 param == PIN_CONFIG_BIAS_PULL_DOWN || 997 param == PIN_CONFIG_DRIVE_STRENGTH) 998 return pinctrl_gpio_set_config(offset, config); 999 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || 1000 param == PIN_CONFIG_DRIVE_OPEN_SOURCE) 1001 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ 1002 return -ENOTSUPP; 1003 else if (param == PIN_CONFIG_PERSIST_STATE) 1004 return aspeed_gpio_reset_tolerance(chip, offset, arg); 1005 1006 return -ENOTSUPP; 1007 } 1008 1009 /** 1010 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handhsaking with 1011 * the coprocessor for shared GPIO banks 1012 * @ops: The callbacks 1013 * @data: Pointer passed back to the callbacks 1014 */ 1015 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data) 1016 { 1017 copro_data = data; 1018 copro_ops = ops; 1019 1020 return 0; 1021 } 1022 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops); 1023 1024 /** 1025 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire 1026 * bank gets marked and any access from the ARM will 1027 * result in handshaking via callbacks. 1028 * @desc: The GPIO to be marked 1029 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space 1030 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space 1031 * @bit: If non-NULL, returns the bit number of the GPIO in the registers 1032 */ 1033 int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, 1034 u16 *vreg_offset, u16 *dreg_offset, u8 *bit) 1035 { 1036 struct gpio_chip *chip = gpiod_to_chip(desc); 1037 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 1038 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 1039 const struct aspeed_gpio_bank *bank = to_bank(offset); 1040 unsigned long flags; 1041 1042 if (!gpio->cf_copro_bankmap) 1043 gpio->cf_copro_bankmap = kzalloc(gpio->config->nr_gpios >> 3, GFP_KERNEL); 1044 if (!gpio->cf_copro_bankmap) 1045 return -ENOMEM; 1046 if (offset < 0 || offset > gpio->config->nr_gpios) 1047 return -EINVAL; 1048 bindex = offset >> 3; 1049 1050 spin_lock_irqsave(&gpio->lock, flags); 1051 1052 /* Sanity check, this shouldn't happen */ 1053 if (gpio->cf_copro_bankmap[bindex] == 0xff) { 1054 rc = -EIO; 1055 goto bail; 1056 } 1057 gpio->cf_copro_bankmap[bindex]++; 1058 1059 /* Switch command source */ 1060 if (gpio->cf_copro_bankmap[bindex] == 1) 1061 aspeed_gpio_change_cmd_source(gpio, bank, bindex, 1062 GPIO_CMDSRC_COLDFIRE); 1063 1064 if (vreg_offset) 1065 *vreg_offset = bank->val_regs; 1066 if (dreg_offset) 1067 *dreg_offset = bank->rdata_reg; 1068 if (bit) 1069 *bit = GPIO_OFFSET(offset); 1070 bail: 1071 spin_unlock_irqrestore(&gpio->lock, flags); 1072 return rc; 1073 } 1074 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio); 1075 1076 /** 1077 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor. 1078 * @desc: The GPIO to be marked 1079 */ 1080 int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) 1081 { 1082 struct gpio_chip *chip = gpiod_to_chip(desc); 1083 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 1084 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 1085 const struct aspeed_gpio_bank *bank = to_bank(offset); 1086 unsigned long flags; 1087 1088 if (!gpio->cf_copro_bankmap) 1089 return -ENXIO; 1090 1091 if (offset < 0 || offset > gpio->config->nr_gpios) 1092 return -EINVAL; 1093 bindex = offset >> 3; 1094 1095 spin_lock_irqsave(&gpio->lock, flags); 1096 1097 /* Sanity check, this shouldn't happen */ 1098 if (gpio->cf_copro_bankmap[bindex] == 0) { 1099 rc = -EIO; 1100 goto bail; 1101 } 1102 gpio->cf_copro_bankmap[bindex]--; 1103 1104 /* Switch command source */ 1105 if (gpio->cf_copro_bankmap[bindex] == 0) 1106 aspeed_gpio_change_cmd_source(gpio, bank, bindex, 1107 GPIO_CMDSRC_ARM); 1108 bail: 1109 spin_unlock_irqrestore(&gpio->lock, flags); 1110 return rc; 1111 } 1112 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); 1113 1114 /* 1115 * Any banks not specified in a struct aspeed_bank_props array are assumed to 1116 * have the properties: 1117 * 1118 * { .input = 0xffffffff, .output = 0xffffffff } 1119 */ 1120 1121 static const struct aspeed_bank_props ast2400_bank_props[] = { 1122 /* input output */ 1123 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1124 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ 1125 { }, 1126 }; 1127 1128 static const struct aspeed_gpio_config ast2400_config = 1129 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ 1130 { .nr_gpios = 220, .props = ast2400_bank_props, }; 1131 1132 static const struct aspeed_bank_props ast2500_bank_props[] = { 1133 /* input output */ 1134 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1135 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ 1136 { 7, 0x000000ff, 0x000000ff }, /* AC */ 1137 { }, 1138 }; 1139 1140 static const struct aspeed_gpio_config ast2500_config = 1141 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ 1142 { .nr_gpios = 232, .props = ast2500_bank_props, }; 1143 1144 static const struct of_device_id aspeed_gpio_of_table[] = { 1145 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, 1146 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, 1147 {} 1148 }; 1149 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); 1150 1151 static int __init aspeed_gpio_probe(struct platform_device *pdev) 1152 { 1153 const struct of_device_id *gpio_id; 1154 struct aspeed_gpio *gpio; 1155 int rc, i, banks; 1156 1157 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 1158 if (!gpio) 1159 return -ENOMEM; 1160 1161 gpio->base = devm_platform_ioremap_resource(pdev, 0); 1162 if (IS_ERR(gpio->base)) 1163 return PTR_ERR(gpio->base); 1164 1165 spin_lock_init(&gpio->lock); 1166 1167 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); 1168 if (!gpio_id) 1169 return -EINVAL; 1170 1171 gpio->clk = of_clk_get(pdev->dev.of_node, 0); 1172 if (IS_ERR(gpio->clk)) { 1173 dev_warn(&pdev->dev, 1174 "Failed to get clock from devicetree, debouncing disabled\n"); 1175 gpio->clk = NULL; 1176 } 1177 1178 gpio->config = gpio_id->data; 1179 1180 gpio->chip.parent = &pdev->dev; 1181 gpio->chip.ngpio = gpio->config->nr_gpios; 1182 gpio->chip.direction_input = aspeed_gpio_dir_in; 1183 gpio->chip.direction_output = aspeed_gpio_dir_out; 1184 gpio->chip.get_direction = aspeed_gpio_get_direction; 1185 gpio->chip.request = aspeed_gpio_request; 1186 gpio->chip.free = aspeed_gpio_free; 1187 gpio->chip.get = aspeed_gpio_get; 1188 gpio->chip.set = aspeed_gpio_set; 1189 gpio->chip.set_config = aspeed_gpio_set_config; 1190 gpio->chip.label = dev_name(&pdev->dev); 1191 gpio->chip.base = -1; 1192 gpio->chip.irq.need_valid_mask = true; 1193 1194 /* Allocate a cache of the output registers */ 1195 banks = gpio->config->nr_gpios >> 5; 1196 gpio->dcache = devm_kcalloc(&pdev->dev, 1197 banks, sizeof(u32), GFP_KERNEL); 1198 if (!gpio->dcache) 1199 return -ENOMEM; 1200 1201 /* 1202 * Populate it with initial values read from the HW and switch 1203 * all command sources to the ARM by default 1204 */ 1205 for (i = 0; i < banks; i++) { 1206 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 1207 void __iomem *addr = bank_reg(gpio, bank, reg_rdata); 1208 gpio->dcache[i] = ioread32(addr); 1209 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM); 1210 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM); 1211 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM); 1212 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM); 1213 } 1214 1215 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 1216 if (rc < 0) 1217 return rc; 1218 1219 gpio->offset_timer = 1220 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); 1221 if (!gpio->offset_timer) 1222 return -ENOMEM; 1223 1224 return aspeed_gpio_setup_irqs(gpio, pdev); 1225 } 1226 1227 static struct platform_driver aspeed_gpio_driver = { 1228 .driver = { 1229 .name = KBUILD_MODNAME, 1230 .of_match_table = aspeed_gpio_of_table, 1231 }, 1232 }; 1233 1234 module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe); 1235 1236 MODULE_DESCRIPTION("Aspeed GPIO Driver"); 1237 MODULE_LICENSE("GPL"); 1238