1 /* 2 * Copyright 2015 IBM Corp. 3 * 4 * Joel Stanley <joel@jms.id.au> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <asm/div64.h> 13 #include <linux/clk.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/hashtable.h> 16 #include <linux/init.h> 17 #include <linux/io.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/platform_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/string.h> 24 25 struct aspeed_bank_props { 26 unsigned int bank; 27 u32 input; 28 u32 output; 29 }; 30 31 struct aspeed_gpio_config { 32 unsigned int nr_gpios; 33 const struct aspeed_bank_props *props; 34 }; 35 36 /* 37 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled 38 * @timer_users: Tracks the number of users for each timer 39 * 40 * The @timer_users has four elements but the first element is unused. This is 41 * to simplify accounting and indexing, as a zero value in @offset_timer 42 * represents disabled debouncing for the GPIO. Any other value for an element 43 * of @offset_timer is used as an index into @timer_users. This behaviour of 44 * the zero value aligns with the behaviour of zero built from the timer 45 * configuration registers (i.e. debouncing is disabled). 46 */ 47 struct aspeed_gpio { 48 struct gpio_chip chip; 49 spinlock_t lock; 50 void __iomem *base; 51 int irq; 52 const struct aspeed_gpio_config *config; 53 54 u8 *offset_timer; 55 unsigned int timer_users[4]; 56 struct clk *clk; 57 58 u32 *dcache; 59 }; 60 61 struct aspeed_gpio_bank { 62 uint16_t val_regs; 63 uint16_t irq_regs; 64 uint16_t debounce_regs; 65 uint16_t tolerance_regs; 66 const char names[4][3]; 67 }; 68 69 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; 70 71 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { 72 { 73 .val_regs = 0x0000, 74 .irq_regs = 0x0008, 75 .debounce_regs = 0x0040, 76 .tolerance_regs = 0x001c, 77 .names = { "A", "B", "C", "D" }, 78 }, 79 { 80 .val_regs = 0x0020, 81 .irq_regs = 0x0028, 82 .debounce_regs = 0x0048, 83 .tolerance_regs = 0x003c, 84 .names = { "E", "F", "G", "H" }, 85 }, 86 { 87 .val_regs = 0x0070, 88 .irq_regs = 0x0098, 89 .debounce_regs = 0x00b0, 90 .tolerance_regs = 0x00ac, 91 .names = { "I", "J", "K", "L" }, 92 }, 93 { 94 .val_regs = 0x0078, 95 .irq_regs = 0x00e8, 96 .debounce_regs = 0x0100, 97 .tolerance_regs = 0x00fc, 98 .names = { "M", "N", "O", "P" }, 99 }, 100 { 101 .val_regs = 0x0080, 102 .irq_regs = 0x0118, 103 .debounce_regs = 0x0130, 104 .tolerance_regs = 0x012c, 105 .names = { "Q", "R", "S", "T" }, 106 }, 107 { 108 .val_regs = 0x0088, 109 .irq_regs = 0x0148, 110 .debounce_regs = 0x0160, 111 .tolerance_regs = 0x015c, 112 .names = { "U", "V", "W", "X" }, 113 }, 114 { 115 .val_regs = 0x01E0, 116 .irq_regs = 0x0178, 117 .debounce_regs = 0x0190, 118 .tolerance_regs = 0x018c, 119 .names = { "Y", "Z", "AA", "AB" }, 120 }, 121 { 122 .val_regs = 0x01e8, 123 .irq_regs = 0x01a8, 124 .debounce_regs = 0x01c0, 125 .tolerance_regs = 0x01bc, 126 .names = { "AC", "", "", "" }, 127 }, 128 }; 129 130 #define GPIO_BANK(x) ((x) >> 5) 131 #define GPIO_OFFSET(x) ((x) & 0x1f) 132 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) 133 134 #define GPIO_DATA 0x00 135 #define GPIO_DIR 0x04 136 137 #define GPIO_IRQ_ENABLE 0x00 138 #define GPIO_IRQ_TYPE0 0x04 139 #define GPIO_IRQ_TYPE1 0x08 140 #define GPIO_IRQ_TYPE2 0x0c 141 #define GPIO_IRQ_STATUS 0x10 142 143 #define GPIO_DEBOUNCE_SEL1 0x00 144 #define GPIO_DEBOUNCE_SEL2 0x04 145 146 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o)) 147 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1) 148 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0) 149 150 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) 151 { 152 unsigned int bank = GPIO_BANK(offset); 153 154 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); 155 return &aspeed_gpio_banks[bank]; 156 } 157 158 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) 159 { 160 return !(props->input || props->output); 161 } 162 163 static inline const struct aspeed_bank_props *find_bank_props( 164 struct aspeed_gpio *gpio, unsigned int offset) 165 { 166 const struct aspeed_bank_props *props = gpio->config->props; 167 168 while (!is_bank_props_sentinel(props)) { 169 if (props->bank == GPIO_BANK(offset)) 170 return props; 171 props++; 172 } 173 174 return NULL; 175 } 176 177 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) 178 { 179 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 180 const struct aspeed_gpio_bank *bank = to_bank(offset); 181 unsigned int group = GPIO_OFFSET(offset) / 8; 182 183 return bank->names[group][0] != '\0' && 184 (!props || ((props->input | props->output) & GPIO_BIT(offset))); 185 } 186 187 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) 188 { 189 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 190 191 return !props || (props->input & GPIO_BIT(offset)); 192 } 193 194 #define have_irq(g, o) have_input((g), (o)) 195 #define have_debounce(g, o) have_input((g), (o)) 196 197 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) 198 { 199 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 200 201 return !props || (props->output & GPIO_BIT(offset)); 202 } 203 204 static void __iomem *bank_val_reg(struct aspeed_gpio *gpio, 205 const struct aspeed_gpio_bank *bank, 206 unsigned int reg) 207 { 208 return gpio->base + bank->val_regs + reg; 209 } 210 211 static void __iomem *bank_irq_reg(struct aspeed_gpio *gpio, 212 const struct aspeed_gpio_bank *bank, 213 unsigned int reg) 214 { 215 return gpio->base + bank->irq_regs + reg; 216 } 217 218 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) 219 { 220 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 221 const struct aspeed_gpio_bank *bank = to_bank(offset); 222 223 return !!(ioread32(bank_val_reg(gpio, bank, GPIO_DATA)) 224 & GPIO_BIT(offset)); 225 } 226 227 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 228 int val) 229 { 230 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 231 const struct aspeed_gpio_bank *bank = to_bank(offset); 232 void __iomem *addr; 233 u32 reg; 234 235 addr = bank_val_reg(gpio, bank, GPIO_DATA); 236 reg = gpio->dcache[GPIO_BANK(offset)]; 237 238 if (val) 239 reg |= GPIO_BIT(offset); 240 else 241 reg &= ~GPIO_BIT(offset); 242 gpio->dcache[GPIO_BANK(offset)] = reg; 243 244 iowrite32(reg, addr); 245 } 246 247 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 248 int val) 249 { 250 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 251 unsigned long flags; 252 253 spin_lock_irqsave(&gpio->lock, flags); 254 255 __aspeed_gpio_set(gc, offset, val); 256 257 spin_unlock_irqrestore(&gpio->lock, flags); 258 } 259 260 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 261 { 262 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 263 const struct aspeed_gpio_bank *bank = to_bank(offset); 264 unsigned long flags; 265 u32 reg; 266 267 if (!have_input(gpio, offset)) 268 return -ENOTSUPP; 269 270 spin_lock_irqsave(&gpio->lock, flags); 271 272 reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)); 273 iowrite32(reg & ~GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR)); 274 275 spin_unlock_irqrestore(&gpio->lock, flags); 276 277 return 0; 278 } 279 280 static int aspeed_gpio_dir_out(struct gpio_chip *gc, 281 unsigned int offset, int val) 282 { 283 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 284 const struct aspeed_gpio_bank *bank = to_bank(offset); 285 unsigned long flags; 286 u32 reg; 287 288 if (!have_output(gpio, offset)) 289 return -ENOTSUPP; 290 291 spin_lock_irqsave(&gpio->lock, flags); 292 293 __aspeed_gpio_set(gc, offset, val); 294 reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)); 295 iowrite32(reg | GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR)); 296 297 spin_unlock_irqrestore(&gpio->lock, flags); 298 299 return 0; 300 } 301 302 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 303 { 304 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 305 const struct aspeed_gpio_bank *bank = to_bank(offset); 306 unsigned long flags; 307 u32 val; 308 309 if (!have_input(gpio, offset)) 310 return 0; 311 312 if (!have_output(gpio, offset)) 313 return 1; 314 315 spin_lock_irqsave(&gpio->lock, flags); 316 317 val = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)) & GPIO_BIT(offset); 318 319 spin_unlock_irqrestore(&gpio->lock, flags); 320 321 return !val; 322 323 } 324 325 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, 326 struct aspeed_gpio **gpio, 327 const struct aspeed_gpio_bank **bank, 328 u32 *bit) 329 { 330 int offset; 331 struct aspeed_gpio *internal; 332 333 offset = irqd_to_hwirq(d); 334 335 internal = irq_data_get_irq_chip_data(d); 336 337 /* This might be a bit of a questionable place to check */ 338 if (!have_irq(internal, offset)) 339 return -ENOTSUPP; 340 341 *gpio = internal; 342 *bank = to_bank(offset); 343 *bit = GPIO_BIT(offset); 344 345 return 0; 346 } 347 348 static void aspeed_gpio_irq_ack(struct irq_data *d) 349 { 350 const struct aspeed_gpio_bank *bank; 351 struct aspeed_gpio *gpio; 352 unsigned long flags; 353 void __iomem *status_addr; 354 u32 bit; 355 int rc; 356 357 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); 358 if (rc) 359 return; 360 361 status_addr = bank_irq_reg(gpio, bank, GPIO_IRQ_STATUS); 362 363 spin_lock_irqsave(&gpio->lock, flags); 364 iowrite32(bit, status_addr); 365 spin_unlock_irqrestore(&gpio->lock, flags); 366 } 367 368 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) 369 { 370 const struct aspeed_gpio_bank *bank; 371 struct aspeed_gpio *gpio; 372 unsigned long flags; 373 u32 reg, bit; 374 void __iomem *addr; 375 int rc; 376 377 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); 378 if (rc) 379 return; 380 381 addr = bank_irq_reg(gpio, bank, GPIO_IRQ_ENABLE); 382 383 spin_lock_irqsave(&gpio->lock, flags); 384 385 reg = ioread32(addr); 386 if (set) 387 reg |= bit; 388 else 389 reg &= ~bit; 390 iowrite32(reg, addr); 391 392 spin_unlock_irqrestore(&gpio->lock, flags); 393 } 394 395 static void aspeed_gpio_irq_mask(struct irq_data *d) 396 { 397 aspeed_gpio_irq_set_mask(d, false); 398 } 399 400 static void aspeed_gpio_irq_unmask(struct irq_data *d) 401 { 402 aspeed_gpio_irq_set_mask(d, true); 403 } 404 405 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) 406 { 407 u32 type0 = 0; 408 u32 type1 = 0; 409 u32 type2 = 0; 410 u32 bit, reg; 411 const struct aspeed_gpio_bank *bank; 412 irq_flow_handler_t handler; 413 struct aspeed_gpio *gpio; 414 unsigned long flags; 415 void __iomem *addr; 416 int rc; 417 418 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); 419 if (rc) 420 return -EINVAL; 421 422 switch (type & IRQ_TYPE_SENSE_MASK) { 423 case IRQ_TYPE_EDGE_BOTH: 424 type2 |= bit; 425 /* fall through */ 426 case IRQ_TYPE_EDGE_RISING: 427 type0 |= bit; 428 /* fall through */ 429 case IRQ_TYPE_EDGE_FALLING: 430 handler = handle_edge_irq; 431 break; 432 case IRQ_TYPE_LEVEL_HIGH: 433 type0 |= bit; 434 /* fall through */ 435 case IRQ_TYPE_LEVEL_LOW: 436 type1 |= bit; 437 handler = handle_level_irq; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 spin_lock_irqsave(&gpio->lock, flags); 444 445 addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE0); 446 reg = ioread32(addr); 447 reg = (reg & ~bit) | type0; 448 iowrite32(reg, addr); 449 450 addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE1); 451 reg = ioread32(addr); 452 reg = (reg & ~bit) | type1; 453 iowrite32(reg, addr); 454 455 addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE2); 456 reg = ioread32(addr); 457 reg = (reg & ~bit) | type2; 458 iowrite32(reg, addr); 459 460 spin_unlock_irqrestore(&gpio->lock, flags); 461 462 irq_set_handler_locked(d, handler); 463 464 return 0; 465 } 466 467 static void aspeed_gpio_irq_handler(struct irq_desc *desc) 468 { 469 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 470 struct irq_chip *ic = irq_desc_get_chip(desc); 471 struct aspeed_gpio *data = gpiochip_get_data(gc); 472 unsigned int i, p, girq; 473 unsigned long reg; 474 475 chained_irq_enter(ic, desc); 476 477 for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) { 478 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 479 480 reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS)); 481 482 for_each_set_bit(p, ®, 32) { 483 girq = irq_find_mapping(gc->irq.domain, i * 32 + p); 484 generic_handle_irq(girq); 485 } 486 487 } 488 489 chained_irq_exit(ic, desc); 490 } 491 492 static struct irq_chip aspeed_gpio_irqchip = { 493 .name = "aspeed-gpio", 494 .irq_ack = aspeed_gpio_irq_ack, 495 .irq_mask = aspeed_gpio_irq_mask, 496 .irq_unmask = aspeed_gpio_irq_unmask, 497 .irq_set_type = aspeed_gpio_set_type, 498 }; 499 500 static void set_irq_valid_mask(struct aspeed_gpio *gpio) 501 { 502 const struct aspeed_bank_props *props = gpio->config->props; 503 504 while (!is_bank_props_sentinel(props)) { 505 unsigned int offset; 506 const unsigned long int input = props->input; 507 508 /* Pretty crummy approach, but similar to GPIO core */ 509 for_each_clear_bit(offset, &input, 32) { 510 unsigned int i = props->bank * 32 + offset; 511 512 if (i >= gpio->config->nr_gpios) 513 break; 514 515 clear_bit(i, gpio->chip.irq.valid_mask); 516 } 517 518 props++; 519 } 520 } 521 522 static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, 523 struct platform_device *pdev) 524 { 525 int rc; 526 527 rc = platform_get_irq(pdev, 0); 528 if (rc < 0) 529 return rc; 530 531 gpio->irq = rc; 532 533 set_irq_valid_mask(gpio); 534 535 rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip, 536 0, handle_bad_irq, IRQ_TYPE_NONE); 537 if (rc) { 538 dev_info(&pdev->dev, "Could not add irqchip\n"); 539 return rc; 540 } 541 542 gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip, 543 gpio->irq, aspeed_gpio_irq_handler); 544 545 return 0; 546 } 547 548 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, 549 unsigned int offset, bool enable) 550 { 551 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 552 const struct aspeed_gpio_bank *bank; 553 unsigned long flags; 554 u32 val; 555 556 bank = to_bank(offset); 557 558 spin_lock_irqsave(&gpio->lock, flags); 559 val = readl(gpio->base + bank->tolerance_regs); 560 561 if (enable) 562 val |= GPIO_BIT(offset); 563 else 564 val &= ~GPIO_BIT(offset); 565 566 writel(val, gpio->base + bank->tolerance_regs); 567 spin_unlock_irqrestore(&gpio->lock, flags); 568 569 return 0; 570 } 571 572 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) 573 { 574 if (!have_gpio(gpiochip_get_data(chip), offset)) 575 return -ENODEV; 576 577 return pinctrl_gpio_request(chip->base + offset); 578 } 579 580 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) 581 { 582 pinctrl_gpio_free(chip->base + offset); 583 } 584 585 static inline void __iomem *bank_debounce_reg(struct aspeed_gpio *gpio, 586 const struct aspeed_gpio_bank *bank, 587 unsigned int reg) 588 { 589 return gpio->base + bank->debounce_regs + reg; 590 } 591 592 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, 593 u32 *cycles) 594 { 595 u64 rate; 596 u64 n; 597 u32 r; 598 599 rate = clk_get_rate(gpio->clk); 600 if (!rate) 601 return -ENOTSUPP; 602 603 n = rate * usecs; 604 r = do_div(n, 1000000); 605 606 if (n >= U32_MAX) 607 return -ERANGE; 608 609 /* At least as long as the requested time */ 610 *cycles = n + (!!r); 611 612 return 0; 613 } 614 615 /* Call under gpio->lock */ 616 static int register_allocated_timer(struct aspeed_gpio *gpio, 617 unsigned int offset, unsigned int timer) 618 { 619 if (WARN(gpio->offset_timer[offset] != 0, 620 "Offset %d already allocated timer %d\n", 621 offset, gpio->offset_timer[offset])) 622 return -EINVAL; 623 624 if (WARN(gpio->timer_users[timer] == UINT_MAX, 625 "Timer user count would overflow\n")) 626 return -EPERM; 627 628 gpio->offset_timer[offset] = timer; 629 gpio->timer_users[timer]++; 630 631 return 0; 632 } 633 634 /* Call under gpio->lock */ 635 static int unregister_allocated_timer(struct aspeed_gpio *gpio, 636 unsigned int offset) 637 { 638 if (WARN(gpio->offset_timer[offset] == 0, 639 "No timer allocated to offset %d\n", offset)) 640 return -EINVAL; 641 642 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, 643 "No users recorded for timer %d\n", 644 gpio->offset_timer[offset])) 645 return -EINVAL; 646 647 gpio->timer_users[gpio->offset_timer[offset]]--; 648 gpio->offset_timer[offset] = 0; 649 650 return 0; 651 } 652 653 /* Call under gpio->lock */ 654 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, 655 unsigned int offset) 656 { 657 return gpio->offset_timer[offset] > 0; 658 } 659 660 /* Call under gpio->lock */ 661 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, 662 unsigned int timer) 663 { 664 const struct aspeed_gpio_bank *bank = to_bank(offset); 665 const u32 mask = GPIO_BIT(offset); 666 void __iomem *addr; 667 u32 val; 668 669 addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL1); 670 val = ioread32(addr); 671 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); 672 673 addr = bank_debounce_reg(gpio, bank, GPIO_DEBOUNCE_SEL2); 674 val = ioread32(addr); 675 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); 676 } 677 678 static int enable_debounce(struct gpio_chip *chip, unsigned int offset, 679 unsigned long usecs) 680 { 681 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 682 u32 requested_cycles; 683 unsigned long flags; 684 int rc; 685 int i; 686 687 if (!gpio->clk) 688 return -EINVAL; 689 690 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); 691 if (rc < 0) { 692 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", 693 usecs, clk_get_rate(gpio->clk), rc); 694 return rc; 695 } 696 697 spin_lock_irqsave(&gpio->lock, flags); 698 699 if (timer_allocation_registered(gpio, offset)) { 700 rc = unregister_allocated_timer(gpio, offset); 701 if (rc < 0) 702 goto out; 703 } 704 705 /* Try to find a timer already configured for the debounce period */ 706 for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) { 707 u32 cycles; 708 709 cycles = ioread32(gpio->base + debounce_timers[i]); 710 if (requested_cycles == cycles) 711 break; 712 } 713 714 if (i == ARRAY_SIZE(debounce_timers)) { 715 int j; 716 717 /* 718 * As there are no timers configured for the requested debounce 719 * period, find an unused timer instead 720 */ 721 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { 722 if (gpio->timer_users[j] == 0) 723 break; 724 } 725 726 if (j == ARRAY_SIZE(gpio->timer_users)) { 727 dev_warn(chip->parent, 728 "Debounce timers exhausted, cannot debounce for period %luus\n", 729 usecs); 730 731 rc = -EPERM; 732 733 /* 734 * We already adjusted the accounting to remove @offset 735 * as a user of its previous timer, so also configure 736 * the hardware so @offset has timers disabled for 737 * consistency. 738 */ 739 configure_timer(gpio, offset, 0); 740 goto out; 741 } 742 743 i = j; 744 745 iowrite32(requested_cycles, gpio->base + debounce_timers[i]); 746 } 747 748 if (WARN(i == 0, "Cannot register index of disabled timer\n")) { 749 rc = -EINVAL; 750 goto out; 751 } 752 753 register_allocated_timer(gpio, offset, i); 754 configure_timer(gpio, offset, i); 755 756 out: 757 spin_unlock_irqrestore(&gpio->lock, flags); 758 759 return rc; 760 } 761 762 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) 763 { 764 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 765 unsigned long flags; 766 int rc; 767 768 spin_lock_irqsave(&gpio->lock, flags); 769 770 rc = unregister_allocated_timer(gpio, offset); 771 if (!rc) 772 configure_timer(gpio, offset, 0); 773 774 spin_unlock_irqrestore(&gpio->lock, flags); 775 776 return rc; 777 } 778 779 static int set_debounce(struct gpio_chip *chip, unsigned int offset, 780 unsigned long usecs) 781 { 782 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 783 784 if (!have_debounce(gpio, offset)) 785 return -ENOTSUPP; 786 787 if (usecs) 788 return enable_debounce(chip, offset, usecs); 789 790 return disable_debounce(chip, offset); 791 } 792 793 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 794 unsigned long config) 795 { 796 unsigned long param = pinconf_to_config_param(config); 797 u32 arg = pinconf_to_config_argument(config); 798 799 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 800 return set_debounce(chip, offset, arg); 801 else if (param == PIN_CONFIG_BIAS_DISABLE || 802 param == PIN_CONFIG_BIAS_PULL_DOWN || 803 param == PIN_CONFIG_DRIVE_STRENGTH) 804 return pinctrl_gpio_set_config(offset, config); 805 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || 806 param == PIN_CONFIG_DRIVE_OPEN_SOURCE) 807 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ 808 return -ENOTSUPP; 809 else if (param == PIN_CONFIG_PERSIST_STATE) 810 return aspeed_gpio_reset_tolerance(chip, offset, arg); 811 812 return -ENOTSUPP; 813 } 814 815 /* 816 * Any banks not specified in a struct aspeed_bank_props array are assumed to 817 * have the properties: 818 * 819 * { .input = 0xffffffff, .output = 0xffffffff } 820 */ 821 822 static const struct aspeed_bank_props ast2400_bank_props[] = { 823 /* input output */ 824 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 825 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ 826 { }, 827 }; 828 829 static const struct aspeed_gpio_config ast2400_config = 830 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ 831 { .nr_gpios = 220, .props = ast2400_bank_props, }; 832 833 static const struct aspeed_bank_props ast2500_bank_props[] = { 834 /* input output */ 835 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 836 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ 837 { 7, 0x000000ff, 0x000000ff }, /* AC */ 838 { }, 839 }; 840 841 static const struct aspeed_gpio_config ast2500_config = 842 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ 843 { .nr_gpios = 232, .props = ast2500_bank_props, }; 844 845 static const struct of_device_id aspeed_gpio_of_table[] = { 846 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, 847 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, 848 {} 849 }; 850 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); 851 852 static int __init aspeed_gpio_probe(struct platform_device *pdev) 853 { 854 const struct of_device_id *gpio_id; 855 struct aspeed_gpio *gpio; 856 struct resource *res; 857 int rc, i, banks; 858 859 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 860 if (!gpio) 861 return -ENOMEM; 862 863 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 864 gpio->base = devm_ioremap_resource(&pdev->dev, res); 865 if (IS_ERR(gpio->base)) 866 return PTR_ERR(gpio->base); 867 868 spin_lock_init(&gpio->lock); 869 870 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); 871 if (!gpio_id) 872 return -EINVAL; 873 874 gpio->clk = of_clk_get(pdev->dev.of_node, 0); 875 if (IS_ERR(gpio->clk)) { 876 dev_warn(&pdev->dev, 877 "Failed to get clock from devicetree, debouncing disabled\n"); 878 gpio->clk = NULL; 879 } 880 881 gpio->config = gpio_id->data; 882 883 gpio->chip.parent = &pdev->dev; 884 gpio->chip.ngpio = gpio->config->nr_gpios; 885 gpio->chip.parent = &pdev->dev; 886 gpio->chip.direction_input = aspeed_gpio_dir_in; 887 gpio->chip.direction_output = aspeed_gpio_dir_out; 888 gpio->chip.get_direction = aspeed_gpio_get_direction; 889 gpio->chip.request = aspeed_gpio_request; 890 gpio->chip.free = aspeed_gpio_free; 891 gpio->chip.get = aspeed_gpio_get; 892 gpio->chip.set = aspeed_gpio_set; 893 gpio->chip.set_config = aspeed_gpio_set_config; 894 gpio->chip.label = dev_name(&pdev->dev); 895 gpio->chip.base = -1; 896 gpio->chip.irq.need_valid_mask = true; 897 898 /* Allocate a cache of the output registers */ 899 banks = gpio->config->nr_gpios >> 5; 900 gpio->dcache = devm_kcalloc(&pdev->dev, 901 banks, sizeof(u32), GFP_KERNEL); 902 if (!gpio->dcache) 903 return -ENOMEM; 904 905 /* Populate it with initial values read from the HW */ 906 for (i = 0; i < banks; i++) { 907 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 908 gpio->dcache[i] = ioread32(gpio->base + bank->val_regs + 909 GPIO_DATA); 910 } 911 912 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 913 if (rc < 0) 914 return rc; 915 916 gpio->offset_timer = 917 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); 918 919 return aspeed_gpio_setup_irqs(gpio, pdev); 920 } 921 922 static struct platform_driver aspeed_gpio_driver = { 923 .driver = { 924 .name = KBUILD_MODNAME, 925 .of_match_table = aspeed_gpio_of_table, 926 }, 927 }; 928 929 module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe); 930 931 MODULE_DESCRIPTION("Aspeed GPIO Driver"); 932 MODULE_LICENSE("GPL"); 933