1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright 2015 IBM Corp. 4 * 5 * Joel Stanley <joel@jms.id.au> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/gpio/aspeed.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/hashtable.h> 12 #include <linux/init.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/pinctrl/consumer.h> 17 #include <linux/platform_device.h> 18 #include <linux/spinlock.h> 19 #include <linux/string.h> 20 21 #include <asm/div64.h> 22 23 /* 24 * These two headers aren't meant to be used by GPIO drivers. We need 25 * them in order to access gpio_chip_hwgpio() which we need to implement 26 * the aspeed specific API which allows the coprocessor to request 27 * access to some GPIOs and to arbitrate between coprocessor and ARM. 28 */ 29 #include <linux/gpio/consumer.h> 30 #include "gpiolib.h" 31 32 struct aspeed_bank_props { 33 unsigned int bank; 34 u32 input; 35 u32 output; 36 }; 37 38 struct aspeed_gpio_config { 39 unsigned int nr_gpios; 40 const struct aspeed_bank_props *props; 41 }; 42 43 /* 44 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled 45 * @timer_users: Tracks the number of users for each timer 46 * 47 * The @timer_users has four elements but the first element is unused. This is 48 * to simplify accounting and indexing, as a zero value in @offset_timer 49 * represents disabled debouncing for the GPIO. Any other value for an element 50 * of @offset_timer is used as an index into @timer_users. This behaviour of 51 * the zero value aligns with the behaviour of zero built from the timer 52 * configuration registers (i.e. debouncing is disabled). 53 */ 54 struct aspeed_gpio { 55 struct gpio_chip chip; 56 struct irq_chip irqc; 57 raw_spinlock_t lock; 58 void __iomem *base; 59 int irq; 60 const struct aspeed_gpio_config *config; 61 62 u8 *offset_timer; 63 unsigned int timer_users[4]; 64 struct clk *clk; 65 66 u32 *dcache; 67 u8 *cf_copro_bankmap; 68 }; 69 70 struct aspeed_gpio_bank { 71 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch 72 * +4: Rd/Wr: Direction (0=in, 1=out) 73 */ 74 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */ 75 uint16_t irq_regs; 76 uint16_t debounce_regs; 77 uint16_t tolerance_regs; 78 uint16_t cmdsrc_regs; 79 const char names[4][3]; 80 }; 81 82 /* 83 * Note: The "value" register returns the input value sampled on the 84 * line even when the GPIO is configured as an output. Since 85 * that input goes through synchronizers, writing, then reading 86 * back may not return the written value right away. 87 * 88 * The "rdata" register returns the content of the write latch 89 * and thus can be used to read back what was last written 90 * reliably. 91 */ 92 93 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; 94 95 static const struct aspeed_gpio_copro_ops *copro_ops; 96 static void *copro_data; 97 98 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { 99 { 100 .val_regs = 0x0000, 101 .rdata_reg = 0x00c0, 102 .irq_regs = 0x0008, 103 .debounce_regs = 0x0040, 104 .tolerance_regs = 0x001c, 105 .cmdsrc_regs = 0x0060, 106 .names = { "A", "B", "C", "D" }, 107 }, 108 { 109 .val_regs = 0x0020, 110 .rdata_reg = 0x00c4, 111 .irq_regs = 0x0028, 112 .debounce_regs = 0x0048, 113 .tolerance_regs = 0x003c, 114 .cmdsrc_regs = 0x0068, 115 .names = { "E", "F", "G", "H" }, 116 }, 117 { 118 .val_regs = 0x0070, 119 .rdata_reg = 0x00c8, 120 .irq_regs = 0x0098, 121 .debounce_regs = 0x00b0, 122 .tolerance_regs = 0x00ac, 123 .cmdsrc_regs = 0x0090, 124 .names = { "I", "J", "K", "L" }, 125 }, 126 { 127 .val_regs = 0x0078, 128 .rdata_reg = 0x00cc, 129 .irq_regs = 0x00e8, 130 .debounce_regs = 0x0100, 131 .tolerance_regs = 0x00fc, 132 .cmdsrc_regs = 0x00e0, 133 .names = { "M", "N", "O", "P" }, 134 }, 135 { 136 .val_regs = 0x0080, 137 .rdata_reg = 0x00d0, 138 .irq_regs = 0x0118, 139 .debounce_regs = 0x0130, 140 .tolerance_regs = 0x012c, 141 .cmdsrc_regs = 0x0110, 142 .names = { "Q", "R", "S", "T" }, 143 }, 144 { 145 .val_regs = 0x0088, 146 .rdata_reg = 0x00d4, 147 .irq_regs = 0x0148, 148 .debounce_regs = 0x0160, 149 .tolerance_regs = 0x015c, 150 .cmdsrc_regs = 0x0140, 151 .names = { "U", "V", "W", "X" }, 152 }, 153 { 154 .val_regs = 0x01E0, 155 .rdata_reg = 0x00d8, 156 .irq_regs = 0x0178, 157 .debounce_regs = 0x0190, 158 .tolerance_regs = 0x018c, 159 .cmdsrc_regs = 0x0170, 160 .names = { "Y", "Z", "AA", "AB" }, 161 }, 162 { 163 .val_regs = 0x01e8, 164 .rdata_reg = 0x00dc, 165 .irq_regs = 0x01a8, 166 .debounce_regs = 0x01c0, 167 .tolerance_regs = 0x01bc, 168 .cmdsrc_regs = 0x01a0, 169 .names = { "AC", "", "", "" }, 170 }, 171 }; 172 173 enum aspeed_gpio_reg { 174 reg_val, 175 reg_rdata, 176 reg_dir, 177 reg_irq_enable, 178 reg_irq_type0, 179 reg_irq_type1, 180 reg_irq_type2, 181 reg_irq_status, 182 reg_debounce_sel1, 183 reg_debounce_sel2, 184 reg_tolerance, 185 reg_cmdsrc0, 186 reg_cmdsrc1, 187 }; 188 189 #define GPIO_VAL_VALUE 0x00 190 #define GPIO_VAL_DIR 0x04 191 192 #define GPIO_IRQ_ENABLE 0x00 193 #define GPIO_IRQ_TYPE0 0x04 194 #define GPIO_IRQ_TYPE1 0x08 195 #define GPIO_IRQ_TYPE2 0x0c 196 #define GPIO_IRQ_STATUS 0x10 197 198 #define GPIO_DEBOUNCE_SEL1 0x00 199 #define GPIO_DEBOUNCE_SEL2 0x04 200 201 #define GPIO_CMDSRC_0 0x00 202 #define GPIO_CMDSRC_1 0x04 203 #define GPIO_CMDSRC_ARM 0 204 #define GPIO_CMDSRC_LPC 1 205 #define GPIO_CMDSRC_COLDFIRE 2 206 #define GPIO_CMDSRC_RESERVED 3 207 208 /* This will be resolved at compile time */ 209 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, 210 const struct aspeed_gpio_bank *bank, 211 const enum aspeed_gpio_reg reg) 212 { 213 switch (reg) { 214 case reg_val: 215 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; 216 case reg_rdata: 217 return gpio->base + bank->rdata_reg; 218 case reg_dir: 219 return gpio->base + bank->val_regs + GPIO_VAL_DIR; 220 case reg_irq_enable: 221 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; 222 case reg_irq_type0: 223 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; 224 case reg_irq_type1: 225 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; 226 case reg_irq_type2: 227 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; 228 case reg_irq_status: 229 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; 230 case reg_debounce_sel1: 231 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; 232 case reg_debounce_sel2: 233 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; 234 case reg_tolerance: 235 return gpio->base + bank->tolerance_regs; 236 case reg_cmdsrc0: 237 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; 238 case reg_cmdsrc1: 239 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; 240 } 241 BUG(); 242 } 243 244 #define GPIO_BANK(x) ((x) >> 5) 245 #define GPIO_OFFSET(x) ((x) & 0x1f) 246 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) 247 248 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o)) 249 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1) 250 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0) 251 252 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) 253 { 254 unsigned int bank = GPIO_BANK(offset); 255 256 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); 257 return &aspeed_gpio_banks[bank]; 258 } 259 260 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) 261 { 262 return !(props->input || props->output); 263 } 264 265 static inline const struct aspeed_bank_props *find_bank_props( 266 struct aspeed_gpio *gpio, unsigned int offset) 267 { 268 const struct aspeed_bank_props *props = gpio->config->props; 269 270 while (!is_bank_props_sentinel(props)) { 271 if (props->bank == GPIO_BANK(offset)) 272 return props; 273 props++; 274 } 275 276 return NULL; 277 } 278 279 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) 280 { 281 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 282 const struct aspeed_gpio_bank *bank = to_bank(offset); 283 unsigned int group = GPIO_OFFSET(offset) / 8; 284 285 return bank->names[group][0] != '\0' && 286 (!props || ((props->input | props->output) & GPIO_BIT(offset))); 287 } 288 289 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) 290 { 291 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 292 293 return !props || (props->input & GPIO_BIT(offset)); 294 } 295 296 #define have_irq(g, o) have_input((g), (o)) 297 #define have_debounce(g, o) have_input((g), (o)) 298 299 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) 300 { 301 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 302 303 return !props || (props->output & GPIO_BIT(offset)); 304 } 305 306 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, 307 const struct aspeed_gpio_bank *bank, 308 int bindex, int cmdsrc) 309 { 310 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0); 311 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1); 312 u32 bit, reg; 313 314 /* 315 * Each register controls 4 banks, so take the bottom 2 316 * bits of the bank index, and use them to select the 317 * right control bit (0, 8, 16 or 24). 318 */ 319 bit = BIT((bindex & 3) << 3); 320 321 /* Source 1 first to avoid illegal 11 combination */ 322 reg = ioread32(c1); 323 if (cmdsrc & 2) 324 reg |= bit; 325 else 326 reg &= ~bit; 327 iowrite32(reg, c1); 328 329 /* Then Source 0 */ 330 reg = ioread32(c0); 331 if (cmdsrc & 1) 332 reg |= bit; 333 else 334 reg &= ~bit; 335 iowrite32(reg, c0); 336 } 337 338 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, 339 unsigned int offset) 340 { 341 const struct aspeed_gpio_bank *bank = to_bank(offset); 342 343 if (!copro_ops || !gpio->cf_copro_bankmap) 344 return false; 345 if (!gpio->cf_copro_bankmap[offset >> 3]) 346 return false; 347 if (!copro_ops->request_access) 348 return false; 349 350 /* Pause the coprocessor */ 351 copro_ops->request_access(copro_data); 352 353 /* Change command source back to ARM */ 354 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM); 355 356 /* Update cache */ 357 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); 358 359 return true; 360 } 361 362 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, 363 unsigned int offset) 364 { 365 const struct aspeed_gpio_bank *bank = to_bank(offset); 366 367 if (!copro_ops || !gpio->cf_copro_bankmap) 368 return; 369 if (!gpio->cf_copro_bankmap[offset >> 3]) 370 return; 371 if (!copro_ops->release_access) 372 return; 373 374 /* Change command source back to ColdFire */ 375 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, 376 GPIO_CMDSRC_COLDFIRE); 377 378 /* Restart the coprocessor */ 379 copro_ops->release_access(copro_data); 380 } 381 382 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) 383 { 384 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 385 const struct aspeed_gpio_bank *bank = to_bank(offset); 386 387 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); 388 } 389 390 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 391 int val) 392 { 393 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 394 const struct aspeed_gpio_bank *bank = to_bank(offset); 395 void __iomem *addr; 396 u32 reg; 397 398 addr = bank_reg(gpio, bank, reg_val); 399 reg = gpio->dcache[GPIO_BANK(offset)]; 400 401 if (val) 402 reg |= GPIO_BIT(offset); 403 else 404 reg &= ~GPIO_BIT(offset); 405 gpio->dcache[GPIO_BANK(offset)] = reg; 406 407 iowrite32(reg, addr); 408 } 409 410 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 411 int val) 412 { 413 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 414 unsigned long flags; 415 bool copro; 416 417 raw_spin_lock_irqsave(&gpio->lock, flags); 418 copro = aspeed_gpio_copro_request(gpio, offset); 419 420 __aspeed_gpio_set(gc, offset, val); 421 422 if (copro) 423 aspeed_gpio_copro_release(gpio, offset); 424 raw_spin_unlock_irqrestore(&gpio->lock, flags); 425 } 426 427 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 428 { 429 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 430 const struct aspeed_gpio_bank *bank = to_bank(offset); 431 void __iomem *addr = bank_reg(gpio, bank, reg_dir); 432 unsigned long flags; 433 bool copro; 434 u32 reg; 435 436 if (!have_input(gpio, offset)) 437 return -ENOTSUPP; 438 439 raw_spin_lock_irqsave(&gpio->lock, flags); 440 441 reg = ioread32(addr); 442 reg &= ~GPIO_BIT(offset); 443 444 copro = aspeed_gpio_copro_request(gpio, offset); 445 iowrite32(reg, addr); 446 if (copro) 447 aspeed_gpio_copro_release(gpio, offset); 448 449 raw_spin_unlock_irqrestore(&gpio->lock, flags); 450 451 return 0; 452 } 453 454 static int aspeed_gpio_dir_out(struct gpio_chip *gc, 455 unsigned int offset, int val) 456 { 457 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 458 const struct aspeed_gpio_bank *bank = to_bank(offset); 459 void __iomem *addr = bank_reg(gpio, bank, reg_dir); 460 unsigned long flags; 461 bool copro; 462 u32 reg; 463 464 if (!have_output(gpio, offset)) 465 return -ENOTSUPP; 466 467 raw_spin_lock_irqsave(&gpio->lock, flags); 468 469 reg = ioread32(addr); 470 reg |= GPIO_BIT(offset); 471 472 copro = aspeed_gpio_copro_request(gpio, offset); 473 __aspeed_gpio_set(gc, offset, val); 474 iowrite32(reg, addr); 475 476 if (copro) 477 aspeed_gpio_copro_release(gpio, offset); 478 raw_spin_unlock_irqrestore(&gpio->lock, flags); 479 480 return 0; 481 } 482 483 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 484 { 485 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 486 const struct aspeed_gpio_bank *bank = to_bank(offset); 487 unsigned long flags; 488 u32 val; 489 490 if (!have_input(gpio, offset)) 491 return GPIO_LINE_DIRECTION_OUT; 492 493 if (!have_output(gpio, offset)) 494 return GPIO_LINE_DIRECTION_IN; 495 496 raw_spin_lock_irqsave(&gpio->lock, flags); 497 498 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); 499 500 raw_spin_unlock_irqrestore(&gpio->lock, flags); 501 502 return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 503 } 504 505 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, 506 struct aspeed_gpio **gpio, 507 const struct aspeed_gpio_bank **bank, 508 u32 *bit, int *offset) 509 { 510 struct aspeed_gpio *internal; 511 512 *offset = irqd_to_hwirq(d); 513 514 internal = irq_data_get_irq_chip_data(d); 515 516 /* This might be a bit of a questionable place to check */ 517 if (!have_irq(internal, *offset)) 518 return -ENOTSUPP; 519 520 *gpio = internal; 521 *bank = to_bank(*offset); 522 *bit = GPIO_BIT(*offset); 523 524 return 0; 525 } 526 527 static void aspeed_gpio_irq_ack(struct irq_data *d) 528 { 529 const struct aspeed_gpio_bank *bank; 530 struct aspeed_gpio *gpio; 531 unsigned long flags; 532 void __iomem *status_addr; 533 int rc, offset; 534 bool copro; 535 u32 bit; 536 537 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 538 if (rc) 539 return; 540 541 status_addr = bank_reg(gpio, bank, reg_irq_status); 542 543 raw_spin_lock_irqsave(&gpio->lock, flags); 544 copro = aspeed_gpio_copro_request(gpio, offset); 545 546 iowrite32(bit, status_addr); 547 548 if (copro) 549 aspeed_gpio_copro_release(gpio, offset); 550 raw_spin_unlock_irqrestore(&gpio->lock, flags); 551 } 552 553 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) 554 { 555 const struct aspeed_gpio_bank *bank; 556 struct aspeed_gpio *gpio; 557 unsigned long flags; 558 u32 reg, bit; 559 void __iomem *addr; 560 int rc, offset; 561 bool copro; 562 563 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 564 if (rc) 565 return; 566 567 addr = bank_reg(gpio, bank, reg_irq_enable); 568 569 raw_spin_lock_irqsave(&gpio->lock, flags); 570 copro = aspeed_gpio_copro_request(gpio, offset); 571 572 reg = ioread32(addr); 573 if (set) 574 reg |= bit; 575 else 576 reg &= ~bit; 577 iowrite32(reg, addr); 578 579 if (copro) 580 aspeed_gpio_copro_release(gpio, offset); 581 raw_spin_unlock_irqrestore(&gpio->lock, flags); 582 } 583 584 static void aspeed_gpio_irq_mask(struct irq_data *d) 585 { 586 aspeed_gpio_irq_set_mask(d, false); 587 } 588 589 static void aspeed_gpio_irq_unmask(struct irq_data *d) 590 { 591 aspeed_gpio_irq_set_mask(d, true); 592 } 593 594 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) 595 { 596 u32 type0 = 0; 597 u32 type1 = 0; 598 u32 type2 = 0; 599 u32 bit, reg; 600 const struct aspeed_gpio_bank *bank; 601 irq_flow_handler_t handler; 602 struct aspeed_gpio *gpio; 603 unsigned long flags; 604 void __iomem *addr; 605 int rc, offset; 606 bool copro; 607 608 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 609 if (rc) 610 return -EINVAL; 611 612 switch (type & IRQ_TYPE_SENSE_MASK) { 613 case IRQ_TYPE_EDGE_BOTH: 614 type2 |= bit; 615 fallthrough; 616 case IRQ_TYPE_EDGE_RISING: 617 type0 |= bit; 618 fallthrough; 619 case IRQ_TYPE_EDGE_FALLING: 620 handler = handle_edge_irq; 621 break; 622 case IRQ_TYPE_LEVEL_HIGH: 623 type0 |= bit; 624 fallthrough; 625 case IRQ_TYPE_LEVEL_LOW: 626 type1 |= bit; 627 handler = handle_level_irq; 628 break; 629 default: 630 return -EINVAL; 631 } 632 633 raw_spin_lock_irqsave(&gpio->lock, flags); 634 copro = aspeed_gpio_copro_request(gpio, offset); 635 636 addr = bank_reg(gpio, bank, reg_irq_type0); 637 reg = ioread32(addr); 638 reg = (reg & ~bit) | type0; 639 iowrite32(reg, addr); 640 641 addr = bank_reg(gpio, bank, reg_irq_type1); 642 reg = ioread32(addr); 643 reg = (reg & ~bit) | type1; 644 iowrite32(reg, addr); 645 646 addr = bank_reg(gpio, bank, reg_irq_type2); 647 reg = ioread32(addr); 648 reg = (reg & ~bit) | type2; 649 iowrite32(reg, addr); 650 651 if (copro) 652 aspeed_gpio_copro_release(gpio, offset); 653 raw_spin_unlock_irqrestore(&gpio->lock, flags); 654 655 irq_set_handler_locked(d, handler); 656 657 return 0; 658 } 659 660 static void aspeed_gpio_irq_handler(struct irq_desc *desc) 661 { 662 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 663 struct irq_chip *ic = irq_desc_get_chip(desc); 664 struct aspeed_gpio *data = gpiochip_get_data(gc); 665 unsigned int i, p, banks; 666 unsigned long reg; 667 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 668 669 chained_irq_enter(ic, desc); 670 671 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); 672 for (i = 0; i < banks; i++) { 673 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 674 675 reg = ioread32(bank_reg(data, bank, reg_irq_status)); 676 677 for_each_set_bit(p, ®, 32) 678 generic_handle_domain_irq(gc->irq.domain, i * 32 + p); 679 } 680 681 chained_irq_exit(ic, desc); 682 } 683 684 static void aspeed_init_irq_valid_mask(struct gpio_chip *gc, 685 unsigned long *valid_mask, 686 unsigned int ngpios) 687 { 688 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 689 const struct aspeed_bank_props *props = gpio->config->props; 690 691 while (!is_bank_props_sentinel(props)) { 692 unsigned int offset; 693 const unsigned long int input = props->input; 694 695 /* Pretty crummy approach, but similar to GPIO core */ 696 for_each_clear_bit(offset, &input, 32) { 697 unsigned int i = props->bank * 32 + offset; 698 699 if (i >= gpio->chip.ngpio) 700 break; 701 702 clear_bit(i, valid_mask); 703 } 704 705 props++; 706 } 707 } 708 709 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, 710 unsigned int offset, bool enable) 711 { 712 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 713 unsigned long flags; 714 void __iomem *treg; 715 bool copro; 716 u32 val; 717 718 treg = bank_reg(gpio, to_bank(offset), reg_tolerance); 719 720 raw_spin_lock_irqsave(&gpio->lock, flags); 721 copro = aspeed_gpio_copro_request(gpio, offset); 722 723 val = readl(treg); 724 725 if (enable) 726 val |= GPIO_BIT(offset); 727 else 728 val &= ~GPIO_BIT(offset); 729 730 writel(val, treg); 731 732 if (copro) 733 aspeed_gpio_copro_release(gpio, offset); 734 raw_spin_unlock_irqrestore(&gpio->lock, flags); 735 736 return 0; 737 } 738 739 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) 740 { 741 if (!have_gpio(gpiochip_get_data(chip), offset)) 742 return -ENODEV; 743 744 return pinctrl_gpio_request(chip->base + offset); 745 } 746 747 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) 748 { 749 pinctrl_gpio_free(chip->base + offset); 750 } 751 752 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, 753 u32 *cycles) 754 { 755 u64 rate; 756 u64 n; 757 u32 r; 758 759 rate = clk_get_rate(gpio->clk); 760 if (!rate) 761 return -ENOTSUPP; 762 763 n = rate * usecs; 764 r = do_div(n, 1000000); 765 766 if (n >= U32_MAX) 767 return -ERANGE; 768 769 /* At least as long as the requested time */ 770 *cycles = n + (!!r); 771 772 return 0; 773 } 774 775 /* Call under gpio->lock */ 776 static int register_allocated_timer(struct aspeed_gpio *gpio, 777 unsigned int offset, unsigned int timer) 778 { 779 if (WARN(gpio->offset_timer[offset] != 0, 780 "Offset %d already allocated timer %d\n", 781 offset, gpio->offset_timer[offset])) 782 return -EINVAL; 783 784 if (WARN(gpio->timer_users[timer] == UINT_MAX, 785 "Timer user count would overflow\n")) 786 return -EPERM; 787 788 gpio->offset_timer[offset] = timer; 789 gpio->timer_users[timer]++; 790 791 return 0; 792 } 793 794 /* Call under gpio->lock */ 795 static int unregister_allocated_timer(struct aspeed_gpio *gpio, 796 unsigned int offset) 797 { 798 if (WARN(gpio->offset_timer[offset] == 0, 799 "No timer allocated to offset %d\n", offset)) 800 return -EINVAL; 801 802 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, 803 "No users recorded for timer %d\n", 804 gpio->offset_timer[offset])) 805 return -EINVAL; 806 807 gpio->timer_users[gpio->offset_timer[offset]]--; 808 gpio->offset_timer[offset] = 0; 809 810 return 0; 811 } 812 813 /* Call under gpio->lock */ 814 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, 815 unsigned int offset) 816 { 817 return gpio->offset_timer[offset] > 0; 818 } 819 820 /* Call under gpio->lock */ 821 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, 822 unsigned int timer) 823 { 824 const struct aspeed_gpio_bank *bank = to_bank(offset); 825 const u32 mask = GPIO_BIT(offset); 826 void __iomem *addr; 827 u32 val; 828 829 /* Note: Debounce timer isn't under control of the command 830 * source registers, so no need to sync with the coprocessor 831 */ 832 addr = bank_reg(gpio, bank, reg_debounce_sel1); 833 val = ioread32(addr); 834 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); 835 836 addr = bank_reg(gpio, bank, reg_debounce_sel2); 837 val = ioread32(addr); 838 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); 839 } 840 841 static int enable_debounce(struct gpio_chip *chip, unsigned int offset, 842 unsigned long usecs) 843 { 844 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 845 u32 requested_cycles; 846 unsigned long flags; 847 int rc; 848 int i; 849 850 if (!gpio->clk) 851 return -EINVAL; 852 853 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); 854 if (rc < 0) { 855 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", 856 usecs, clk_get_rate(gpio->clk), rc); 857 return rc; 858 } 859 860 raw_spin_lock_irqsave(&gpio->lock, flags); 861 862 if (timer_allocation_registered(gpio, offset)) { 863 rc = unregister_allocated_timer(gpio, offset); 864 if (rc < 0) 865 goto out; 866 } 867 868 /* Try to find a timer already configured for the debounce period */ 869 for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) { 870 u32 cycles; 871 872 cycles = ioread32(gpio->base + debounce_timers[i]); 873 if (requested_cycles == cycles) 874 break; 875 } 876 877 if (i == ARRAY_SIZE(debounce_timers)) { 878 int j; 879 880 /* 881 * As there are no timers configured for the requested debounce 882 * period, find an unused timer instead 883 */ 884 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { 885 if (gpio->timer_users[j] == 0) 886 break; 887 } 888 889 if (j == ARRAY_SIZE(gpio->timer_users)) { 890 dev_warn(chip->parent, 891 "Debounce timers exhausted, cannot debounce for period %luus\n", 892 usecs); 893 894 rc = -EPERM; 895 896 /* 897 * We already adjusted the accounting to remove @offset 898 * as a user of its previous timer, so also configure 899 * the hardware so @offset has timers disabled for 900 * consistency. 901 */ 902 configure_timer(gpio, offset, 0); 903 goto out; 904 } 905 906 i = j; 907 908 iowrite32(requested_cycles, gpio->base + debounce_timers[i]); 909 } 910 911 if (WARN(i == 0, "Cannot register index of disabled timer\n")) { 912 rc = -EINVAL; 913 goto out; 914 } 915 916 register_allocated_timer(gpio, offset, i); 917 configure_timer(gpio, offset, i); 918 919 out: 920 raw_spin_unlock_irqrestore(&gpio->lock, flags); 921 922 return rc; 923 } 924 925 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) 926 { 927 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 928 unsigned long flags; 929 int rc; 930 931 raw_spin_lock_irqsave(&gpio->lock, flags); 932 933 rc = unregister_allocated_timer(gpio, offset); 934 if (!rc) 935 configure_timer(gpio, offset, 0); 936 937 raw_spin_unlock_irqrestore(&gpio->lock, flags); 938 939 return rc; 940 } 941 942 static int set_debounce(struct gpio_chip *chip, unsigned int offset, 943 unsigned long usecs) 944 { 945 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 946 947 if (!have_debounce(gpio, offset)) 948 return -ENOTSUPP; 949 950 if (usecs) 951 return enable_debounce(chip, offset, usecs); 952 953 return disable_debounce(chip, offset); 954 } 955 956 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 957 unsigned long config) 958 { 959 unsigned long param = pinconf_to_config_param(config); 960 u32 arg = pinconf_to_config_argument(config); 961 962 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 963 return set_debounce(chip, offset, arg); 964 else if (param == PIN_CONFIG_BIAS_DISABLE || 965 param == PIN_CONFIG_BIAS_PULL_DOWN || 966 param == PIN_CONFIG_DRIVE_STRENGTH) 967 return pinctrl_gpio_set_config(offset, config); 968 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || 969 param == PIN_CONFIG_DRIVE_OPEN_SOURCE) 970 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ 971 return -ENOTSUPP; 972 else if (param == PIN_CONFIG_PERSIST_STATE) 973 return aspeed_gpio_reset_tolerance(chip, offset, arg); 974 975 return -ENOTSUPP; 976 } 977 978 /** 979 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with 980 * the coprocessor for shared GPIO banks 981 * @ops: The callbacks 982 * @data: Pointer passed back to the callbacks 983 */ 984 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data) 985 { 986 copro_data = data; 987 copro_ops = ops; 988 989 return 0; 990 } 991 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops); 992 993 /** 994 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire 995 * bank gets marked and any access from the ARM will 996 * result in handshaking via callbacks. 997 * @desc: The GPIO to be marked 998 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space 999 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space 1000 * @bit: If non-NULL, returns the bit number of the GPIO in the registers 1001 */ 1002 int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, 1003 u16 *vreg_offset, u16 *dreg_offset, u8 *bit) 1004 { 1005 struct gpio_chip *chip = gpiod_to_chip(desc); 1006 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 1007 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 1008 const struct aspeed_gpio_bank *bank = to_bank(offset); 1009 unsigned long flags; 1010 1011 if (!gpio->cf_copro_bankmap) 1012 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); 1013 if (!gpio->cf_copro_bankmap) 1014 return -ENOMEM; 1015 if (offset < 0 || offset > gpio->chip.ngpio) 1016 return -EINVAL; 1017 bindex = offset >> 3; 1018 1019 raw_spin_lock_irqsave(&gpio->lock, flags); 1020 1021 /* Sanity check, this shouldn't happen */ 1022 if (gpio->cf_copro_bankmap[bindex] == 0xff) { 1023 rc = -EIO; 1024 goto bail; 1025 } 1026 gpio->cf_copro_bankmap[bindex]++; 1027 1028 /* Switch command source */ 1029 if (gpio->cf_copro_bankmap[bindex] == 1) 1030 aspeed_gpio_change_cmd_source(gpio, bank, bindex, 1031 GPIO_CMDSRC_COLDFIRE); 1032 1033 if (vreg_offset) 1034 *vreg_offset = bank->val_regs; 1035 if (dreg_offset) 1036 *dreg_offset = bank->rdata_reg; 1037 if (bit) 1038 *bit = GPIO_OFFSET(offset); 1039 bail: 1040 raw_spin_unlock_irqrestore(&gpio->lock, flags); 1041 return rc; 1042 } 1043 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio); 1044 1045 /** 1046 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor. 1047 * @desc: The GPIO to be marked 1048 */ 1049 int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) 1050 { 1051 struct gpio_chip *chip = gpiod_to_chip(desc); 1052 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 1053 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 1054 const struct aspeed_gpio_bank *bank = to_bank(offset); 1055 unsigned long flags; 1056 1057 if (!gpio->cf_copro_bankmap) 1058 return -ENXIO; 1059 1060 if (offset < 0 || offset > gpio->chip.ngpio) 1061 return -EINVAL; 1062 bindex = offset >> 3; 1063 1064 raw_spin_lock_irqsave(&gpio->lock, flags); 1065 1066 /* Sanity check, this shouldn't happen */ 1067 if (gpio->cf_copro_bankmap[bindex] == 0) { 1068 rc = -EIO; 1069 goto bail; 1070 } 1071 gpio->cf_copro_bankmap[bindex]--; 1072 1073 /* Switch command source */ 1074 if (gpio->cf_copro_bankmap[bindex] == 0) 1075 aspeed_gpio_change_cmd_source(gpio, bank, bindex, 1076 GPIO_CMDSRC_ARM); 1077 bail: 1078 raw_spin_unlock_irqrestore(&gpio->lock, flags); 1079 return rc; 1080 } 1081 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); 1082 1083 /* 1084 * Any banks not specified in a struct aspeed_bank_props array are assumed to 1085 * have the properties: 1086 * 1087 * { .input = 0xffffffff, .output = 0xffffffff } 1088 */ 1089 1090 static const struct aspeed_bank_props ast2400_bank_props[] = { 1091 /* input output */ 1092 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1093 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ 1094 { }, 1095 }; 1096 1097 static const struct aspeed_gpio_config ast2400_config = 1098 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ 1099 { .nr_gpios = 220, .props = ast2400_bank_props, }; 1100 1101 static const struct aspeed_bank_props ast2500_bank_props[] = { 1102 /* input output */ 1103 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1104 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ 1105 { 7, 0x000000ff, 0x000000ff }, /* AC */ 1106 { }, 1107 }; 1108 1109 static const struct aspeed_gpio_config ast2500_config = 1110 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ 1111 { .nr_gpios = 232, .props = ast2500_bank_props, }; 1112 1113 static const struct aspeed_bank_props ast2600_bank_props[] = { 1114 /* input output */ 1115 {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */ 1116 {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */ 1117 {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */ 1118 { }, 1119 }; 1120 1121 static const struct aspeed_gpio_config ast2600_config = 1122 /* 1123 * ast2600 has two controllers one with 208 GPIOs and one with 36 GPIOs. 1124 * We expect ngpio being set in the device tree and this is a fallback 1125 * option. 1126 */ 1127 { .nr_gpios = 208, .props = ast2600_bank_props, }; 1128 1129 static const struct of_device_id aspeed_gpio_of_table[] = { 1130 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, 1131 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, 1132 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, }, 1133 {} 1134 }; 1135 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); 1136 1137 static int __init aspeed_gpio_probe(struct platform_device *pdev) 1138 { 1139 const struct of_device_id *gpio_id; 1140 struct aspeed_gpio *gpio; 1141 int rc, i, banks, err; 1142 u32 ngpio; 1143 1144 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 1145 if (!gpio) 1146 return -ENOMEM; 1147 1148 gpio->base = devm_platform_ioremap_resource(pdev, 0); 1149 if (IS_ERR(gpio->base)) 1150 return PTR_ERR(gpio->base); 1151 1152 raw_spin_lock_init(&gpio->lock); 1153 1154 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); 1155 if (!gpio_id) 1156 return -EINVAL; 1157 1158 gpio->clk = of_clk_get(pdev->dev.of_node, 0); 1159 if (IS_ERR(gpio->clk)) { 1160 dev_warn(&pdev->dev, 1161 "Failed to get clock from devicetree, debouncing disabled\n"); 1162 gpio->clk = NULL; 1163 } 1164 1165 gpio->config = gpio_id->data; 1166 1167 gpio->chip.parent = &pdev->dev; 1168 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); 1169 gpio->chip.ngpio = (u16) ngpio; 1170 if (err) 1171 gpio->chip.ngpio = gpio->config->nr_gpios; 1172 gpio->chip.direction_input = aspeed_gpio_dir_in; 1173 gpio->chip.direction_output = aspeed_gpio_dir_out; 1174 gpio->chip.get_direction = aspeed_gpio_get_direction; 1175 gpio->chip.request = aspeed_gpio_request; 1176 gpio->chip.free = aspeed_gpio_free; 1177 gpio->chip.get = aspeed_gpio_get; 1178 gpio->chip.set = aspeed_gpio_set; 1179 gpio->chip.set_config = aspeed_gpio_set_config; 1180 gpio->chip.label = dev_name(&pdev->dev); 1181 gpio->chip.base = -1; 1182 1183 /* Allocate a cache of the output registers */ 1184 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); 1185 gpio->dcache = devm_kcalloc(&pdev->dev, 1186 banks, sizeof(u32), GFP_KERNEL); 1187 if (!gpio->dcache) 1188 return -ENOMEM; 1189 1190 /* 1191 * Populate it with initial values read from the HW and switch 1192 * all command sources to the ARM by default 1193 */ 1194 for (i = 0; i < banks; i++) { 1195 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 1196 void __iomem *addr = bank_reg(gpio, bank, reg_rdata); 1197 gpio->dcache[i] = ioread32(addr); 1198 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM); 1199 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM); 1200 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM); 1201 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM); 1202 } 1203 1204 /* Optionally set up an irqchip if there is an IRQ */ 1205 rc = platform_get_irq(pdev, 0); 1206 if (rc > 0) { 1207 struct gpio_irq_chip *girq; 1208 1209 gpio->irq = rc; 1210 girq = &gpio->chip.irq; 1211 girq->chip = &gpio->irqc; 1212 girq->chip->name = dev_name(&pdev->dev); 1213 girq->chip->irq_ack = aspeed_gpio_irq_ack; 1214 girq->chip->irq_mask = aspeed_gpio_irq_mask; 1215 girq->chip->irq_unmask = aspeed_gpio_irq_unmask; 1216 girq->chip->irq_set_type = aspeed_gpio_set_type; 1217 girq->parent_handler = aspeed_gpio_irq_handler; 1218 girq->num_parents = 1; 1219 girq->parents = devm_kcalloc(&pdev->dev, 1, 1220 sizeof(*girq->parents), 1221 GFP_KERNEL); 1222 if (!girq->parents) 1223 return -ENOMEM; 1224 girq->parents[0] = gpio->irq; 1225 girq->default_type = IRQ_TYPE_NONE; 1226 girq->handler = handle_bad_irq; 1227 girq->init_valid_mask = aspeed_init_irq_valid_mask; 1228 } 1229 1230 gpio->offset_timer = 1231 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); 1232 if (!gpio->offset_timer) 1233 return -ENOMEM; 1234 1235 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 1236 if (rc < 0) 1237 return rc; 1238 1239 return 0; 1240 } 1241 1242 static struct platform_driver aspeed_gpio_driver = { 1243 .driver = { 1244 .name = KBUILD_MODNAME, 1245 .of_match_table = aspeed_gpio_of_table, 1246 }, 1247 }; 1248 1249 module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe); 1250 1251 MODULE_DESCRIPTION("Aspeed GPIO Driver"); 1252 MODULE_LICENSE("GPL"); 1253