1 /* 2 * Copyright 2015 IBM Corp. 3 * 4 * Joel Stanley <joel@jms.id.au> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/init.h> 15 #include <linux/io.h> 16 #include <linux/spinlock.h> 17 #include <linux/platform_device.h> 18 #include <linux/gpio/driver.h> 19 #include <linux/pinctrl/consumer.h> 20 21 struct aspeed_bank_props { 22 unsigned int bank; 23 u32 input; 24 u32 output; 25 }; 26 27 struct aspeed_gpio_config { 28 unsigned int nr_gpios; 29 const struct aspeed_bank_props *props; 30 }; 31 32 struct aspeed_gpio { 33 struct gpio_chip chip; 34 spinlock_t lock; 35 void __iomem *base; 36 int irq; 37 const struct aspeed_gpio_config *config; 38 }; 39 40 struct aspeed_gpio_bank { 41 uint16_t val_regs; 42 uint16_t irq_regs; 43 const char names[4][3]; 44 }; 45 46 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { 47 { 48 .val_regs = 0x0000, 49 .irq_regs = 0x0008, 50 .names = { "A", "B", "C", "D" }, 51 }, 52 { 53 .val_regs = 0x0020, 54 .irq_regs = 0x0028, 55 .names = { "E", "F", "G", "H" }, 56 }, 57 { 58 .val_regs = 0x0070, 59 .irq_regs = 0x0098, 60 .names = { "I", "J", "K", "L" }, 61 }, 62 { 63 .val_regs = 0x0078, 64 .irq_regs = 0x00e8, 65 .names = { "M", "N", "O", "P" }, 66 }, 67 { 68 .val_regs = 0x0080, 69 .irq_regs = 0x0118, 70 .names = { "Q", "R", "S", "T" }, 71 }, 72 { 73 .val_regs = 0x0088, 74 .irq_regs = 0x0148, 75 .names = { "U", "V", "W", "X" }, 76 }, 77 { 78 .val_regs = 0x01E0, 79 .irq_regs = 0x0178, 80 .names = { "Y", "Z", "AA", "AB" }, 81 }, 82 { 83 .val_regs = 0x01E8, 84 .irq_regs = 0x01A8, 85 .names = { "AC", "", "", "" }, 86 }, 87 }; 88 89 #define GPIO_BANK(x) ((x) >> 5) 90 #define GPIO_OFFSET(x) ((x) & 0x1f) 91 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) 92 93 #define GPIO_DATA 0x00 94 #define GPIO_DIR 0x04 95 96 #define GPIO_IRQ_ENABLE 0x00 97 #define GPIO_IRQ_TYPE0 0x04 98 #define GPIO_IRQ_TYPE1 0x08 99 #define GPIO_IRQ_TYPE2 0x0c 100 #define GPIO_IRQ_STATUS 0x10 101 102 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) 103 { 104 unsigned int bank = GPIO_BANK(offset); 105 106 WARN_ON(bank > ARRAY_SIZE(aspeed_gpio_banks)); 107 return &aspeed_gpio_banks[bank]; 108 } 109 110 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) 111 { 112 return !(props->input || props->output); 113 } 114 115 static inline const struct aspeed_bank_props *find_bank_props( 116 struct aspeed_gpio *gpio, unsigned int offset) 117 { 118 const struct aspeed_bank_props *props = gpio->config->props; 119 120 while (!is_bank_props_sentinel(props)) { 121 if (props->bank == GPIO_BANK(offset)) 122 return props; 123 props++; 124 } 125 126 return NULL; 127 } 128 129 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) 130 { 131 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 132 const struct aspeed_gpio_bank *bank = to_bank(offset); 133 unsigned int group = GPIO_OFFSET(offset) / 8; 134 135 return bank->names[group][0] != '\0' && 136 (!props || ((props->input | props->output) & GPIO_BIT(offset))); 137 } 138 139 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) 140 { 141 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 142 143 return !props || (props->input & GPIO_BIT(offset)); 144 } 145 146 #define have_irq(g, o) have_input((g), (o)) 147 148 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) 149 { 150 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 151 152 return !props || (props->output & GPIO_BIT(offset)); 153 } 154 155 static void __iomem *bank_val_reg(struct aspeed_gpio *gpio, 156 const struct aspeed_gpio_bank *bank, 157 unsigned int reg) 158 { 159 return gpio->base + bank->val_regs + reg; 160 } 161 162 static void __iomem *bank_irq_reg(struct aspeed_gpio *gpio, 163 const struct aspeed_gpio_bank *bank, 164 unsigned int reg) 165 { 166 return gpio->base + bank->irq_regs + reg; 167 } 168 169 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) 170 { 171 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 172 const struct aspeed_gpio_bank *bank = to_bank(offset); 173 174 return !!(ioread32(bank_val_reg(gpio, bank, GPIO_DATA)) 175 & GPIO_BIT(offset)); 176 } 177 178 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 179 int val) 180 { 181 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 182 const struct aspeed_gpio_bank *bank = to_bank(offset); 183 void __iomem *addr; 184 u32 reg; 185 186 addr = bank_val_reg(gpio, bank, GPIO_DATA); 187 reg = ioread32(addr); 188 189 if (val) 190 reg |= GPIO_BIT(offset); 191 else 192 reg &= ~GPIO_BIT(offset); 193 194 iowrite32(reg, addr); 195 } 196 197 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 198 int val) 199 { 200 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 201 unsigned long flags; 202 203 spin_lock_irqsave(&gpio->lock, flags); 204 205 __aspeed_gpio_set(gc, offset, val); 206 207 spin_unlock_irqrestore(&gpio->lock, flags); 208 } 209 210 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 211 { 212 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 213 const struct aspeed_gpio_bank *bank = to_bank(offset); 214 unsigned long flags; 215 u32 reg; 216 217 if (!have_input(gpio, offset)) 218 return -ENOTSUPP; 219 220 spin_lock_irqsave(&gpio->lock, flags); 221 222 reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)); 223 iowrite32(reg & ~GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR)); 224 225 spin_unlock_irqrestore(&gpio->lock, flags); 226 227 return 0; 228 } 229 230 static int aspeed_gpio_dir_out(struct gpio_chip *gc, 231 unsigned int offset, int val) 232 { 233 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 234 const struct aspeed_gpio_bank *bank = to_bank(offset); 235 unsigned long flags; 236 u32 reg; 237 238 if (!have_output(gpio, offset)) 239 return -ENOTSUPP; 240 241 spin_lock_irqsave(&gpio->lock, flags); 242 243 reg = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)); 244 iowrite32(reg | GPIO_BIT(offset), bank_val_reg(gpio, bank, GPIO_DIR)); 245 246 __aspeed_gpio_set(gc, offset, val); 247 248 spin_unlock_irqrestore(&gpio->lock, flags); 249 250 return 0; 251 } 252 253 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 254 { 255 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 256 const struct aspeed_gpio_bank *bank = to_bank(offset); 257 unsigned long flags; 258 u32 val; 259 260 if (!have_input(gpio, offset)) 261 return 0; 262 263 if (!have_output(gpio, offset)) 264 return 1; 265 266 spin_lock_irqsave(&gpio->lock, flags); 267 268 val = ioread32(bank_val_reg(gpio, bank, GPIO_DIR)) & GPIO_BIT(offset); 269 270 spin_unlock_irqrestore(&gpio->lock, flags); 271 272 return !val; 273 274 } 275 276 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, 277 struct aspeed_gpio **gpio, 278 const struct aspeed_gpio_bank **bank, 279 u32 *bit) 280 { 281 int offset; 282 struct aspeed_gpio *internal; 283 284 offset = irqd_to_hwirq(d); 285 286 internal = irq_data_get_irq_chip_data(d); 287 288 /* This might be a bit of a questionable place to check */ 289 if (!have_irq(internal, offset)) 290 return -ENOTSUPP; 291 292 *gpio = internal; 293 *bank = to_bank(offset); 294 *bit = GPIO_BIT(offset); 295 296 return 0; 297 } 298 299 static void aspeed_gpio_irq_ack(struct irq_data *d) 300 { 301 const struct aspeed_gpio_bank *bank; 302 struct aspeed_gpio *gpio; 303 unsigned long flags; 304 void __iomem *status_addr; 305 u32 bit; 306 int rc; 307 308 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); 309 if (rc) 310 return; 311 312 status_addr = bank_irq_reg(gpio, bank, GPIO_IRQ_STATUS); 313 314 spin_lock_irqsave(&gpio->lock, flags); 315 iowrite32(bit, status_addr); 316 spin_unlock_irqrestore(&gpio->lock, flags); 317 } 318 319 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) 320 { 321 const struct aspeed_gpio_bank *bank; 322 struct aspeed_gpio *gpio; 323 unsigned long flags; 324 u32 reg, bit; 325 void __iomem *addr; 326 int rc; 327 328 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); 329 if (rc) 330 return; 331 332 addr = bank_irq_reg(gpio, bank, GPIO_IRQ_ENABLE); 333 334 spin_lock_irqsave(&gpio->lock, flags); 335 336 reg = ioread32(addr); 337 if (set) 338 reg |= bit; 339 else 340 reg &= bit; 341 iowrite32(reg, addr); 342 343 spin_unlock_irqrestore(&gpio->lock, flags); 344 } 345 346 static void aspeed_gpio_irq_mask(struct irq_data *d) 347 { 348 aspeed_gpio_irq_set_mask(d, false); 349 } 350 351 static void aspeed_gpio_irq_unmask(struct irq_data *d) 352 { 353 aspeed_gpio_irq_set_mask(d, true); 354 } 355 356 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) 357 { 358 u32 type0 = 0; 359 u32 type1 = 0; 360 u32 type2 = 0; 361 u32 bit, reg; 362 const struct aspeed_gpio_bank *bank; 363 irq_flow_handler_t handler; 364 struct aspeed_gpio *gpio; 365 unsigned long flags; 366 void __iomem *addr; 367 int rc; 368 369 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit); 370 if (rc) 371 return -EINVAL; 372 373 switch (type & IRQ_TYPE_SENSE_MASK) { 374 case IRQ_TYPE_EDGE_BOTH: 375 type2 |= bit; 376 case IRQ_TYPE_EDGE_RISING: 377 type0 |= bit; 378 case IRQ_TYPE_EDGE_FALLING: 379 handler = handle_edge_irq; 380 break; 381 case IRQ_TYPE_LEVEL_HIGH: 382 type0 |= bit; 383 case IRQ_TYPE_LEVEL_LOW: 384 type1 |= bit; 385 handler = handle_level_irq; 386 break; 387 default: 388 return -EINVAL; 389 } 390 391 spin_lock_irqsave(&gpio->lock, flags); 392 393 addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE0); 394 reg = ioread32(addr); 395 reg = (reg & ~bit) | type0; 396 iowrite32(reg, addr); 397 398 addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE1); 399 reg = ioread32(addr); 400 reg = (reg & ~bit) | type1; 401 iowrite32(reg, addr); 402 403 addr = bank_irq_reg(gpio, bank, GPIO_IRQ_TYPE2); 404 reg = ioread32(addr); 405 reg = (reg & ~bit) | type2; 406 iowrite32(reg, addr); 407 408 spin_unlock_irqrestore(&gpio->lock, flags); 409 410 irq_set_handler_locked(d, handler); 411 412 return 0; 413 } 414 415 static void aspeed_gpio_irq_handler(struct irq_desc *desc) 416 { 417 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 418 struct irq_chip *ic = irq_desc_get_chip(desc); 419 struct aspeed_gpio *data = gpiochip_get_data(gc); 420 unsigned int i, p, girq; 421 unsigned long reg; 422 423 chained_irq_enter(ic, desc); 424 425 for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) { 426 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 427 428 reg = ioread32(bank_irq_reg(data, bank, GPIO_IRQ_STATUS)); 429 430 for_each_set_bit(p, ®, 32) { 431 girq = irq_find_mapping(gc->irqdomain, i * 32 + p); 432 generic_handle_irq(girq); 433 } 434 435 } 436 437 chained_irq_exit(ic, desc); 438 } 439 440 static struct irq_chip aspeed_gpio_irqchip = { 441 .name = "aspeed-gpio", 442 .irq_ack = aspeed_gpio_irq_ack, 443 .irq_mask = aspeed_gpio_irq_mask, 444 .irq_unmask = aspeed_gpio_irq_unmask, 445 .irq_set_type = aspeed_gpio_set_type, 446 }; 447 448 static void set_irq_valid_mask(struct aspeed_gpio *gpio) 449 { 450 const struct aspeed_bank_props *props = gpio->config->props; 451 452 while (!is_bank_props_sentinel(props)) { 453 unsigned int offset; 454 const unsigned long int input = props->input; 455 456 /* Pretty crummy approach, but similar to GPIO core */ 457 for_each_clear_bit(offset, &input, 32) { 458 unsigned int i = props->bank * 32 + offset; 459 460 if (i >= gpio->config->nr_gpios) 461 break; 462 463 clear_bit(i, gpio->chip.irq_valid_mask); 464 } 465 466 props++; 467 } 468 } 469 470 static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, 471 struct platform_device *pdev) 472 { 473 int rc; 474 475 rc = platform_get_irq(pdev, 0); 476 if (rc < 0) 477 return rc; 478 479 gpio->irq = rc; 480 481 set_irq_valid_mask(gpio); 482 483 rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip, 484 0, handle_bad_irq, IRQ_TYPE_NONE); 485 if (rc) { 486 dev_info(&pdev->dev, "Could not add irqchip\n"); 487 return rc; 488 } 489 490 gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip, 491 gpio->irq, aspeed_gpio_irq_handler); 492 493 return 0; 494 } 495 496 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) 497 { 498 if (!have_gpio(gpiochip_get_data(chip), offset)) 499 return -ENODEV; 500 501 return pinctrl_request_gpio(chip->base + offset); 502 } 503 504 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) 505 { 506 pinctrl_free_gpio(chip->base + offset); 507 } 508 509 /* 510 * Any banks not specified in a struct aspeed_bank_props array are assumed to 511 * have the properties: 512 * 513 * { .input = 0xffffffff, .output = 0xffffffff } 514 */ 515 516 static const struct aspeed_bank_props ast2400_bank_props[] = { 517 /* input output */ 518 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 519 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ 520 { }, 521 }; 522 523 static const struct aspeed_gpio_config ast2400_config = 524 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ 525 { .nr_gpios = 220, .props = ast2400_bank_props, }; 526 527 static const struct aspeed_bank_props ast2500_bank_props[] = { 528 /* input output */ 529 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 530 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ 531 { 7, 0x000000ff, 0x000000ff }, /* AC */ 532 { }, 533 }; 534 535 static const struct aspeed_gpio_config ast2500_config = 536 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ 537 { .nr_gpios = 232, .props = ast2500_bank_props, }; 538 539 static const struct of_device_id aspeed_gpio_of_table[] = { 540 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, 541 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, 542 {} 543 }; 544 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); 545 546 static int __init aspeed_gpio_probe(struct platform_device *pdev) 547 { 548 const struct of_device_id *gpio_id; 549 struct aspeed_gpio *gpio; 550 struct resource *res; 551 int rc; 552 553 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 554 if (!gpio) 555 return -ENOMEM; 556 557 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 558 gpio->base = devm_ioremap_resource(&pdev->dev, res); 559 if (IS_ERR(gpio->base)) 560 return PTR_ERR(gpio->base); 561 562 spin_lock_init(&gpio->lock); 563 564 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); 565 if (!gpio_id) 566 return -EINVAL; 567 568 gpio->config = gpio_id->data; 569 570 gpio->chip.ngpio = gpio->config->nr_gpios; 571 gpio->chip.parent = &pdev->dev; 572 gpio->chip.direction_input = aspeed_gpio_dir_in; 573 gpio->chip.direction_output = aspeed_gpio_dir_out; 574 gpio->chip.get_direction = aspeed_gpio_get_direction; 575 gpio->chip.request = aspeed_gpio_request; 576 gpio->chip.free = aspeed_gpio_free; 577 gpio->chip.get = aspeed_gpio_get; 578 gpio->chip.set = aspeed_gpio_set; 579 gpio->chip.label = dev_name(&pdev->dev); 580 gpio->chip.base = -1; 581 gpio->chip.irq_need_valid_mask = true; 582 583 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 584 if (rc < 0) 585 return rc; 586 587 return aspeed_gpio_setup_irqs(gpio, pdev); 588 } 589 590 static struct platform_driver aspeed_gpio_driver = { 591 .driver = { 592 .name = KBUILD_MODNAME, 593 .of_match_table = aspeed_gpio_of_table, 594 }, 595 }; 596 597 module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe); 598 599 MODULE_DESCRIPTION("Aspeed GPIO Driver"); 600 MODULE_LICENSE("GPL"); 601