1 /* 2 * Copyright 2015 IBM Corp. 3 * 4 * Joel Stanley <joel@jms.id.au> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 9 * 2 of the License, or (at your option) any later version. 10 */ 11 12 #include <asm/div64.h> 13 #include <linux/clk.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/gpio/aspeed.h> 16 #include <linux/hashtable.h> 17 #include <linux/init.h> 18 #include <linux/io.h> 19 #include <linux/kernel.h> 20 #include <linux/module.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/platform_device.h> 23 #include <linux/spinlock.h> 24 #include <linux/string.h> 25 26 /* 27 * These two headers aren't meant to be used by GPIO drivers. We need 28 * them in order to access gpio_chip_hwgpio() which we need to implement 29 * the aspeed specific API which allows the coprocessor to request 30 * access to some GPIOs and to arbitrate between coprocessor and ARM. 31 */ 32 #include <linux/gpio/consumer.h> 33 #include "gpiolib.h" 34 35 struct aspeed_bank_props { 36 unsigned int bank; 37 u32 input; 38 u32 output; 39 }; 40 41 struct aspeed_gpio_config { 42 unsigned int nr_gpios; 43 const struct aspeed_bank_props *props; 44 }; 45 46 /* 47 * @offset_timer: Maps an offset to an @timer_users index, or zero if disabled 48 * @timer_users: Tracks the number of users for each timer 49 * 50 * The @timer_users has four elements but the first element is unused. This is 51 * to simplify accounting and indexing, as a zero value in @offset_timer 52 * represents disabled debouncing for the GPIO. Any other value for an element 53 * of @offset_timer is used as an index into @timer_users. This behaviour of 54 * the zero value aligns with the behaviour of zero built from the timer 55 * configuration registers (i.e. debouncing is disabled). 56 */ 57 struct aspeed_gpio { 58 struct gpio_chip chip; 59 spinlock_t lock; 60 void __iomem *base; 61 int irq; 62 const struct aspeed_gpio_config *config; 63 64 u8 *offset_timer; 65 unsigned int timer_users[4]; 66 struct clk *clk; 67 68 u32 *dcache; 69 u8 *cf_copro_bankmap; 70 }; 71 72 struct aspeed_gpio_bank { 73 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch 74 * +4: Rd/Wr: Direction (0=in, 1=out) 75 */ 76 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */ 77 uint16_t irq_regs; 78 uint16_t debounce_regs; 79 uint16_t tolerance_regs; 80 uint16_t cmdsrc_regs; 81 const char names[4][3]; 82 }; 83 84 /* 85 * Note: The "value" register returns the input value sampled on the 86 * line even when the GPIO is configured as an output. Since 87 * that input goes through synchronizers, writing, then reading 88 * back may not return the written value right away. 89 * 90 * The "rdata" register returns the content of the write latch 91 * and thus can be used to read back what was last written 92 * reliably. 93 */ 94 95 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 }; 96 97 static const struct aspeed_gpio_copro_ops *copro_ops; 98 static void *copro_data; 99 100 static const struct aspeed_gpio_bank aspeed_gpio_banks[] = { 101 { 102 .val_regs = 0x0000, 103 .rdata_reg = 0x00c0, 104 .irq_regs = 0x0008, 105 .debounce_regs = 0x0040, 106 .tolerance_regs = 0x001c, 107 .cmdsrc_regs = 0x0060, 108 .names = { "A", "B", "C", "D" }, 109 }, 110 { 111 .val_regs = 0x0020, 112 .rdata_reg = 0x00c4, 113 .irq_regs = 0x0028, 114 .debounce_regs = 0x0048, 115 .tolerance_regs = 0x003c, 116 .cmdsrc_regs = 0x0068, 117 .names = { "E", "F", "G", "H" }, 118 }, 119 { 120 .val_regs = 0x0070, 121 .rdata_reg = 0x00c8, 122 .irq_regs = 0x0098, 123 .debounce_regs = 0x00b0, 124 .tolerance_regs = 0x00ac, 125 .cmdsrc_regs = 0x0090, 126 .names = { "I", "J", "K", "L" }, 127 }, 128 { 129 .val_regs = 0x0078, 130 .rdata_reg = 0x00cc, 131 .irq_regs = 0x00e8, 132 .debounce_regs = 0x0100, 133 .tolerance_regs = 0x00fc, 134 .cmdsrc_regs = 0x00e0, 135 .names = { "M", "N", "O", "P" }, 136 }, 137 { 138 .val_regs = 0x0080, 139 .rdata_reg = 0x00d0, 140 .irq_regs = 0x0118, 141 .debounce_regs = 0x0130, 142 .tolerance_regs = 0x012c, 143 .cmdsrc_regs = 0x0110, 144 .names = { "Q", "R", "S", "T" }, 145 }, 146 { 147 .val_regs = 0x0088, 148 .rdata_reg = 0x00d4, 149 .irq_regs = 0x0148, 150 .debounce_regs = 0x0160, 151 .tolerance_regs = 0x015c, 152 .cmdsrc_regs = 0x0140, 153 .names = { "U", "V", "W", "X" }, 154 }, 155 { 156 .val_regs = 0x01E0, 157 .rdata_reg = 0x00d8, 158 .irq_regs = 0x0178, 159 .debounce_regs = 0x0190, 160 .tolerance_regs = 0x018c, 161 .cmdsrc_regs = 0x0170, 162 .names = { "Y", "Z", "AA", "AB" }, 163 }, 164 { 165 .val_regs = 0x01e8, 166 .rdata_reg = 0x00dc, 167 .irq_regs = 0x01a8, 168 .debounce_regs = 0x01c0, 169 .tolerance_regs = 0x01bc, 170 .cmdsrc_regs = 0x01a0, 171 .names = { "AC", "", "", "" }, 172 }, 173 }; 174 175 enum aspeed_gpio_reg { 176 reg_val, 177 reg_rdata, 178 reg_dir, 179 reg_irq_enable, 180 reg_irq_type0, 181 reg_irq_type1, 182 reg_irq_type2, 183 reg_irq_status, 184 reg_debounce_sel1, 185 reg_debounce_sel2, 186 reg_tolerance, 187 reg_cmdsrc0, 188 reg_cmdsrc1, 189 }; 190 191 #define GPIO_VAL_VALUE 0x00 192 #define GPIO_VAL_DIR 0x04 193 194 #define GPIO_IRQ_ENABLE 0x00 195 #define GPIO_IRQ_TYPE0 0x04 196 #define GPIO_IRQ_TYPE1 0x08 197 #define GPIO_IRQ_TYPE2 0x0c 198 #define GPIO_IRQ_STATUS 0x10 199 200 #define GPIO_DEBOUNCE_SEL1 0x00 201 #define GPIO_DEBOUNCE_SEL2 0x04 202 203 #define GPIO_CMDSRC_0 0x00 204 #define GPIO_CMDSRC_1 0x04 205 #define GPIO_CMDSRC_ARM 0 206 #define GPIO_CMDSRC_LPC 1 207 #define GPIO_CMDSRC_COLDFIRE 2 208 #define GPIO_CMDSRC_RESERVED 3 209 210 /* This will be resolved at compile time */ 211 static inline void __iomem *bank_reg(struct aspeed_gpio *gpio, 212 const struct aspeed_gpio_bank *bank, 213 const enum aspeed_gpio_reg reg) 214 { 215 switch (reg) { 216 case reg_val: 217 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; 218 case reg_rdata: 219 return gpio->base + bank->rdata_reg; 220 case reg_dir: 221 return gpio->base + bank->val_regs + GPIO_VAL_DIR; 222 case reg_irq_enable: 223 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; 224 case reg_irq_type0: 225 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; 226 case reg_irq_type1: 227 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; 228 case reg_irq_type2: 229 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; 230 case reg_irq_status: 231 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; 232 case reg_debounce_sel1: 233 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; 234 case reg_debounce_sel2: 235 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; 236 case reg_tolerance: 237 return gpio->base + bank->tolerance_regs; 238 case reg_cmdsrc0: 239 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; 240 case reg_cmdsrc1: 241 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; 242 } 243 BUG(); 244 } 245 246 #define GPIO_BANK(x) ((x) >> 5) 247 #define GPIO_OFFSET(x) ((x) & 0x1f) 248 #define GPIO_BIT(x) BIT(GPIO_OFFSET(x)) 249 250 #define _GPIO_SET_DEBOUNCE(t, o, i) ((!!((t) & BIT(i))) << GPIO_OFFSET(o)) 251 #define GPIO_SET_DEBOUNCE1(t, o) _GPIO_SET_DEBOUNCE(t, o, 1) 252 #define GPIO_SET_DEBOUNCE2(t, o) _GPIO_SET_DEBOUNCE(t, o, 0) 253 254 static const struct aspeed_gpio_bank *to_bank(unsigned int offset) 255 { 256 unsigned int bank = GPIO_BANK(offset); 257 258 WARN_ON(bank >= ARRAY_SIZE(aspeed_gpio_banks)); 259 return &aspeed_gpio_banks[bank]; 260 } 261 262 static inline bool is_bank_props_sentinel(const struct aspeed_bank_props *props) 263 { 264 return !(props->input || props->output); 265 } 266 267 static inline const struct aspeed_bank_props *find_bank_props( 268 struct aspeed_gpio *gpio, unsigned int offset) 269 { 270 const struct aspeed_bank_props *props = gpio->config->props; 271 272 while (!is_bank_props_sentinel(props)) { 273 if (props->bank == GPIO_BANK(offset)) 274 return props; 275 props++; 276 } 277 278 return NULL; 279 } 280 281 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) 282 { 283 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 284 const struct aspeed_gpio_bank *bank = to_bank(offset); 285 unsigned int group = GPIO_OFFSET(offset) / 8; 286 287 return bank->names[group][0] != '\0' && 288 (!props || ((props->input | props->output) & GPIO_BIT(offset))); 289 } 290 291 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) 292 { 293 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 294 295 return !props || (props->input & GPIO_BIT(offset)); 296 } 297 298 #define have_irq(g, o) have_input((g), (o)) 299 #define have_debounce(g, o) have_input((g), (o)) 300 301 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) 302 { 303 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); 304 305 return !props || (props->output & GPIO_BIT(offset)); 306 } 307 308 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, 309 const struct aspeed_gpio_bank *bank, 310 int bindex, int cmdsrc) 311 { 312 void __iomem *c0 = bank_reg(gpio, bank, reg_cmdsrc0); 313 void __iomem *c1 = bank_reg(gpio, bank, reg_cmdsrc1); 314 u32 bit, reg; 315 316 /* 317 * Each register controls 4 banks, so take the bottom 2 318 * bits of the bank index, and use them to select the 319 * right control bit (0, 8, 16 or 24). 320 */ 321 bit = BIT((bindex & 3) << 3); 322 323 /* Source 1 first to avoid illegal 11 combination */ 324 reg = ioread32(c1); 325 if (cmdsrc & 2) 326 reg |= bit; 327 else 328 reg &= ~bit; 329 iowrite32(reg, c1); 330 331 /* Then Source 0 */ 332 reg = ioread32(c0); 333 if (cmdsrc & 1) 334 reg |= bit; 335 else 336 reg &= ~bit; 337 iowrite32(reg, c0); 338 } 339 340 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, 341 unsigned int offset) 342 { 343 const struct aspeed_gpio_bank *bank = to_bank(offset); 344 345 if (!copro_ops || !gpio->cf_copro_bankmap) 346 return false; 347 if (!gpio->cf_copro_bankmap[offset >> 3]) 348 return false; 349 if (!copro_ops->request_access) 350 return false; 351 352 /* Pause the coprocessor */ 353 copro_ops->request_access(copro_data); 354 355 /* Change command source back to ARM */ 356 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, GPIO_CMDSRC_ARM); 357 358 /* Update cache */ 359 gpio->dcache[GPIO_BANK(offset)] = ioread32(bank_reg(gpio, bank, reg_rdata)); 360 361 return true; 362 } 363 364 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, 365 unsigned int offset) 366 { 367 const struct aspeed_gpio_bank *bank = to_bank(offset); 368 369 if (!copro_ops || !gpio->cf_copro_bankmap) 370 return; 371 if (!gpio->cf_copro_bankmap[offset >> 3]) 372 return; 373 if (!copro_ops->release_access) 374 return; 375 376 /* Change command source back to ColdFire */ 377 aspeed_gpio_change_cmd_source(gpio, bank, offset >> 3, 378 GPIO_CMDSRC_COLDFIRE); 379 380 /* Restart the coprocessor */ 381 copro_ops->release_access(copro_data); 382 } 383 384 static int aspeed_gpio_get(struct gpio_chip *gc, unsigned int offset) 385 { 386 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 387 const struct aspeed_gpio_bank *bank = to_bank(offset); 388 389 return !!(ioread32(bank_reg(gpio, bank, reg_val)) & GPIO_BIT(offset)); 390 } 391 392 static void __aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 393 int val) 394 { 395 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 396 const struct aspeed_gpio_bank *bank = to_bank(offset); 397 void __iomem *addr; 398 u32 reg; 399 400 addr = bank_reg(gpio, bank, reg_val); 401 reg = gpio->dcache[GPIO_BANK(offset)]; 402 403 if (val) 404 reg |= GPIO_BIT(offset); 405 else 406 reg &= ~GPIO_BIT(offset); 407 gpio->dcache[GPIO_BANK(offset)] = reg; 408 409 iowrite32(reg, addr); 410 } 411 412 static void aspeed_gpio_set(struct gpio_chip *gc, unsigned int offset, 413 int val) 414 { 415 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 416 unsigned long flags; 417 bool copro; 418 419 spin_lock_irqsave(&gpio->lock, flags); 420 copro = aspeed_gpio_copro_request(gpio, offset); 421 422 __aspeed_gpio_set(gc, offset, val); 423 424 if (copro) 425 aspeed_gpio_copro_release(gpio, offset); 426 spin_unlock_irqrestore(&gpio->lock, flags); 427 } 428 429 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) 430 { 431 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 432 const struct aspeed_gpio_bank *bank = to_bank(offset); 433 void __iomem *addr = bank_reg(gpio, bank, reg_dir); 434 unsigned long flags; 435 bool copro; 436 u32 reg; 437 438 if (!have_input(gpio, offset)) 439 return -ENOTSUPP; 440 441 spin_lock_irqsave(&gpio->lock, flags); 442 443 reg = ioread32(addr); 444 reg &= ~GPIO_BIT(offset); 445 446 copro = aspeed_gpio_copro_request(gpio, offset); 447 iowrite32(reg, addr); 448 if (copro) 449 aspeed_gpio_copro_release(gpio, offset); 450 451 spin_unlock_irqrestore(&gpio->lock, flags); 452 453 return 0; 454 } 455 456 static int aspeed_gpio_dir_out(struct gpio_chip *gc, 457 unsigned int offset, int val) 458 { 459 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 460 const struct aspeed_gpio_bank *bank = to_bank(offset); 461 void __iomem *addr = bank_reg(gpio, bank, reg_dir); 462 unsigned long flags; 463 bool copro; 464 u32 reg; 465 466 if (!have_output(gpio, offset)) 467 return -ENOTSUPP; 468 469 spin_lock_irqsave(&gpio->lock, flags); 470 471 reg = ioread32(addr); 472 reg |= GPIO_BIT(offset); 473 474 copro = aspeed_gpio_copro_request(gpio, offset); 475 __aspeed_gpio_set(gc, offset, val); 476 iowrite32(reg, addr); 477 478 if (copro) 479 aspeed_gpio_copro_release(gpio, offset); 480 spin_unlock_irqrestore(&gpio->lock, flags); 481 482 return 0; 483 } 484 485 static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 486 { 487 struct aspeed_gpio *gpio = gpiochip_get_data(gc); 488 const struct aspeed_gpio_bank *bank = to_bank(offset); 489 unsigned long flags; 490 u32 val; 491 492 if (!have_input(gpio, offset)) 493 return 0; 494 495 if (!have_output(gpio, offset)) 496 return 1; 497 498 spin_lock_irqsave(&gpio->lock, flags); 499 500 val = ioread32(bank_reg(gpio, bank, reg_dir)) & GPIO_BIT(offset); 501 502 spin_unlock_irqrestore(&gpio->lock, flags); 503 504 return !val; 505 506 } 507 508 static inline int irqd_to_aspeed_gpio_data(struct irq_data *d, 509 struct aspeed_gpio **gpio, 510 const struct aspeed_gpio_bank **bank, 511 u32 *bit, int *offset) 512 { 513 struct aspeed_gpio *internal; 514 515 *offset = irqd_to_hwirq(d); 516 517 internal = irq_data_get_irq_chip_data(d); 518 519 /* This might be a bit of a questionable place to check */ 520 if (!have_irq(internal, *offset)) 521 return -ENOTSUPP; 522 523 *gpio = internal; 524 *bank = to_bank(*offset); 525 *bit = GPIO_BIT(*offset); 526 527 return 0; 528 } 529 530 static void aspeed_gpio_irq_ack(struct irq_data *d) 531 { 532 const struct aspeed_gpio_bank *bank; 533 struct aspeed_gpio *gpio; 534 unsigned long flags; 535 void __iomem *status_addr; 536 int rc, offset; 537 bool copro; 538 u32 bit; 539 540 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 541 if (rc) 542 return; 543 544 status_addr = bank_reg(gpio, bank, reg_irq_status); 545 546 spin_lock_irqsave(&gpio->lock, flags); 547 copro = aspeed_gpio_copro_request(gpio, offset); 548 549 iowrite32(bit, status_addr); 550 551 if (copro) 552 aspeed_gpio_copro_release(gpio, offset); 553 spin_unlock_irqrestore(&gpio->lock, flags); 554 } 555 556 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) 557 { 558 const struct aspeed_gpio_bank *bank; 559 struct aspeed_gpio *gpio; 560 unsigned long flags; 561 u32 reg, bit; 562 void __iomem *addr; 563 int rc, offset; 564 bool copro; 565 566 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 567 if (rc) 568 return; 569 570 addr = bank_reg(gpio, bank, reg_irq_enable); 571 572 spin_lock_irqsave(&gpio->lock, flags); 573 copro = aspeed_gpio_copro_request(gpio, offset); 574 575 reg = ioread32(addr); 576 if (set) 577 reg |= bit; 578 else 579 reg &= ~bit; 580 iowrite32(reg, addr); 581 582 if (copro) 583 aspeed_gpio_copro_release(gpio, offset); 584 spin_unlock_irqrestore(&gpio->lock, flags); 585 } 586 587 static void aspeed_gpio_irq_mask(struct irq_data *d) 588 { 589 aspeed_gpio_irq_set_mask(d, false); 590 } 591 592 static void aspeed_gpio_irq_unmask(struct irq_data *d) 593 { 594 aspeed_gpio_irq_set_mask(d, true); 595 } 596 597 static int aspeed_gpio_set_type(struct irq_data *d, unsigned int type) 598 { 599 u32 type0 = 0; 600 u32 type1 = 0; 601 u32 type2 = 0; 602 u32 bit, reg; 603 const struct aspeed_gpio_bank *bank; 604 irq_flow_handler_t handler; 605 struct aspeed_gpio *gpio; 606 unsigned long flags; 607 void __iomem *addr; 608 int rc, offset; 609 bool copro; 610 611 rc = irqd_to_aspeed_gpio_data(d, &gpio, &bank, &bit, &offset); 612 if (rc) 613 return -EINVAL; 614 615 switch (type & IRQ_TYPE_SENSE_MASK) { 616 case IRQ_TYPE_EDGE_BOTH: 617 type2 |= bit; 618 /* fall through */ 619 case IRQ_TYPE_EDGE_RISING: 620 type0 |= bit; 621 /* fall through */ 622 case IRQ_TYPE_EDGE_FALLING: 623 handler = handle_edge_irq; 624 break; 625 case IRQ_TYPE_LEVEL_HIGH: 626 type0 |= bit; 627 /* fall through */ 628 case IRQ_TYPE_LEVEL_LOW: 629 type1 |= bit; 630 handler = handle_level_irq; 631 break; 632 default: 633 return -EINVAL; 634 } 635 636 spin_lock_irqsave(&gpio->lock, flags); 637 copro = aspeed_gpio_copro_request(gpio, offset); 638 639 addr = bank_reg(gpio, bank, reg_irq_type0); 640 reg = ioread32(addr); 641 reg = (reg & ~bit) | type0; 642 iowrite32(reg, addr); 643 644 addr = bank_reg(gpio, bank, reg_irq_type1); 645 reg = ioread32(addr); 646 reg = (reg & ~bit) | type1; 647 iowrite32(reg, addr); 648 649 addr = bank_reg(gpio, bank, reg_irq_type2); 650 reg = ioread32(addr); 651 reg = (reg & ~bit) | type2; 652 iowrite32(reg, addr); 653 654 if (copro) 655 aspeed_gpio_copro_release(gpio, offset); 656 spin_unlock_irqrestore(&gpio->lock, flags); 657 658 irq_set_handler_locked(d, handler); 659 660 return 0; 661 } 662 663 static void aspeed_gpio_irq_handler(struct irq_desc *desc) 664 { 665 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 666 struct irq_chip *ic = irq_desc_get_chip(desc); 667 struct aspeed_gpio *data = gpiochip_get_data(gc); 668 unsigned int i, p, girq; 669 unsigned long reg; 670 671 chained_irq_enter(ic, desc); 672 673 for (i = 0; i < ARRAY_SIZE(aspeed_gpio_banks); i++) { 674 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 675 676 reg = ioread32(bank_reg(data, bank, reg_irq_status)); 677 678 for_each_set_bit(p, ®, 32) { 679 girq = irq_find_mapping(gc->irq.domain, i * 32 + p); 680 generic_handle_irq(girq); 681 } 682 683 } 684 685 chained_irq_exit(ic, desc); 686 } 687 688 static struct irq_chip aspeed_gpio_irqchip = { 689 .name = "aspeed-gpio", 690 .irq_ack = aspeed_gpio_irq_ack, 691 .irq_mask = aspeed_gpio_irq_mask, 692 .irq_unmask = aspeed_gpio_irq_unmask, 693 .irq_set_type = aspeed_gpio_set_type, 694 }; 695 696 static void set_irq_valid_mask(struct aspeed_gpio *gpio) 697 { 698 const struct aspeed_bank_props *props = gpio->config->props; 699 700 while (!is_bank_props_sentinel(props)) { 701 unsigned int offset; 702 const unsigned long int input = props->input; 703 704 /* Pretty crummy approach, but similar to GPIO core */ 705 for_each_clear_bit(offset, &input, 32) { 706 unsigned int i = props->bank * 32 + offset; 707 708 if (i >= gpio->config->nr_gpios) 709 break; 710 711 clear_bit(i, gpio->chip.irq.valid_mask); 712 } 713 714 props++; 715 } 716 } 717 718 static int aspeed_gpio_setup_irqs(struct aspeed_gpio *gpio, 719 struct platform_device *pdev) 720 { 721 int rc; 722 723 rc = platform_get_irq(pdev, 0); 724 if (rc < 0) 725 return rc; 726 727 gpio->irq = rc; 728 729 set_irq_valid_mask(gpio); 730 731 rc = gpiochip_irqchip_add(&gpio->chip, &aspeed_gpio_irqchip, 732 0, handle_bad_irq, IRQ_TYPE_NONE); 733 if (rc) { 734 dev_info(&pdev->dev, "Could not add irqchip\n"); 735 return rc; 736 } 737 738 gpiochip_set_chained_irqchip(&gpio->chip, &aspeed_gpio_irqchip, 739 gpio->irq, aspeed_gpio_irq_handler); 740 741 return 0; 742 } 743 744 static int aspeed_gpio_reset_tolerance(struct gpio_chip *chip, 745 unsigned int offset, bool enable) 746 { 747 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 748 unsigned long flags; 749 void __iomem *treg; 750 bool copro; 751 u32 val; 752 753 treg = bank_reg(gpio, to_bank(offset), reg_tolerance); 754 755 spin_lock_irqsave(&gpio->lock, flags); 756 copro = aspeed_gpio_copro_request(gpio, offset); 757 758 val = readl(treg); 759 760 if (enable) 761 val |= GPIO_BIT(offset); 762 else 763 val &= ~GPIO_BIT(offset); 764 765 writel(val, treg); 766 767 if (copro) 768 aspeed_gpio_copro_release(gpio, offset); 769 spin_unlock_irqrestore(&gpio->lock, flags); 770 771 return 0; 772 } 773 774 static int aspeed_gpio_request(struct gpio_chip *chip, unsigned int offset) 775 { 776 if (!have_gpio(gpiochip_get_data(chip), offset)) 777 return -ENODEV; 778 779 return pinctrl_gpio_request(chip->base + offset); 780 } 781 782 static void aspeed_gpio_free(struct gpio_chip *chip, unsigned int offset) 783 { 784 pinctrl_gpio_free(chip->base + offset); 785 } 786 787 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, 788 u32 *cycles) 789 { 790 u64 rate; 791 u64 n; 792 u32 r; 793 794 rate = clk_get_rate(gpio->clk); 795 if (!rate) 796 return -ENOTSUPP; 797 798 n = rate * usecs; 799 r = do_div(n, 1000000); 800 801 if (n >= U32_MAX) 802 return -ERANGE; 803 804 /* At least as long as the requested time */ 805 *cycles = n + (!!r); 806 807 return 0; 808 } 809 810 /* Call under gpio->lock */ 811 static int register_allocated_timer(struct aspeed_gpio *gpio, 812 unsigned int offset, unsigned int timer) 813 { 814 if (WARN(gpio->offset_timer[offset] != 0, 815 "Offset %d already allocated timer %d\n", 816 offset, gpio->offset_timer[offset])) 817 return -EINVAL; 818 819 if (WARN(gpio->timer_users[timer] == UINT_MAX, 820 "Timer user count would overflow\n")) 821 return -EPERM; 822 823 gpio->offset_timer[offset] = timer; 824 gpio->timer_users[timer]++; 825 826 return 0; 827 } 828 829 /* Call under gpio->lock */ 830 static int unregister_allocated_timer(struct aspeed_gpio *gpio, 831 unsigned int offset) 832 { 833 if (WARN(gpio->offset_timer[offset] == 0, 834 "No timer allocated to offset %d\n", offset)) 835 return -EINVAL; 836 837 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, 838 "No users recorded for timer %d\n", 839 gpio->offset_timer[offset])) 840 return -EINVAL; 841 842 gpio->timer_users[gpio->offset_timer[offset]]--; 843 gpio->offset_timer[offset] = 0; 844 845 return 0; 846 } 847 848 /* Call under gpio->lock */ 849 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, 850 unsigned int offset) 851 { 852 return gpio->offset_timer[offset] > 0; 853 } 854 855 /* Call under gpio->lock */ 856 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, 857 unsigned int timer) 858 { 859 const struct aspeed_gpio_bank *bank = to_bank(offset); 860 const u32 mask = GPIO_BIT(offset); 861 void __iomem *addr; 862 u32 val; 863 864 /* Note: Debounce timer isn't under control of the command 865 * source registers, so no need to sync with the coprocessor 866 */ 867 addr = bank_reg(gpio, bank, reg_debounce_sel1); 868 val = ioread32(addr); 869 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE1(timer, offset), addr); 870 871 addr = bank_reg(gpio, bank, reg_debounce_sel2); 872 val = ioread32(addr); 873 iowrite32((val & ~mask) | GPIO_SET_DEBOUNCE2(timer, offset), addr); 874 } 875 876 static int enable_debounce(struct gpio_chip *chip, unsigned int offset, 877 unsigned long usecs) 878 { 879 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 880 u32 requested_cycles; 881 unsigned long flags; 882 int rc; 883 int i; 884 885 if (!gpio->clk) 886 return -EINVAL; 887 888 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); 889 if (rc < 0) { 890 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", 891 usecs, clk_get_rate(gpio->clk), rc); 892 return rc; 893 } 894 895 spin_lock_irqsave(&gpio->lock, flags); 896 897 if (timer_allocation_registered(gpio, offset)) { 898 rc = unregister_allocated_timer(gpio, offset); 899 if (rc < 0) 900 goto out; 901 } 902 903 /* Try to find a timer already configured for the debounce period */ 904 for (i = 1; i < ARRAY_SIZE(debounce_timers); i++) { 905 u32 cycles; 906 907 cycles = ioread32(gpio->base + debounce_timers[i]); 908 if (requested_cycles == cycles) 909 break; 910 } 911 912 if (i == ARRAY_SIZE(debounce_timers)) { 913 int j; 914 915 /* 916 * As there are no timers configured for the requested debounce 917 * period, find an unused timer instead 918 */ 919 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { 920 if (gpio->timer_users[j] == 0) 921 break; 922 } 923 924 if (j == ARRAY_SIZE(gpio->timer_users)) { 925 dev_warn(chip->parent, 926 "Debounce timers exhausted, cannot debounce for period %luus\n", 927 usecs); 928 929 rc = -EPERM; 930 931 /* 932 * We already adjusted the accounting to remove @offset 933 * as a user of its previous timer, so also configure 934 * the hardware so @offset has timers disabled for 935 * consistency. 936 */ 937 configure_timer(gpio, offset, 0); 938 goto out; 939 } 940 941 i = j; 942 943 iowrite32(requested_cycles, gpio->base + debounce_timers[i]); 944 } 945 946 if (WARN(i == 0, "Cannot register index of disabled timer\n")) { 947 rc = -EINVAL; 948 goto out; 949 } 950 951 register_allocated_timer(gpio, offset, i); 952 configure_timer(gpio, offset, i); 953 954 out: 955 spin_unlock_irqrestore(&gpio->lock, flags); 956 957 return rc; 958 } 959 960 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) 961 { 962 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 963 unsigned long flags; 964 int rc; 965 966 spin_lock_irqsave(&gpio->lock, flags); 967 968 rc = unregister_allocated_timer(gpio, offset); 969 if (!rc) 970 configure_timer(gpio, offset, 0); 971 972 spin_unlock_irqrestore(&gpio->lock, flags); 973 974 return rc; 975 } 976 977 static int set_debounce(struct gpio_chip *chip, unsigned int offset, 978 unsigned long usecs) 979 { 980 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 981 982 if (!have_debounce(gpio, offset)) 983 return -ENOTSUPP; 984 985 if (usecs) 986 return enable_debounce(chip, offset, usecs); 987 988 return disable_debounce(chip, offset); 989 } 990 991 static int aspeed_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 992 unsigned long config) 993 { 994 unsigned long param = pinconf_to_config_param(config); 995 u32 arg = pinconf_to_config_argument(config); 996 997 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 998 return set_debounce(chip, offset, arg); 999 else if (param == PIN_CONFIG_BIAS_DISABLE || 1000 param == PIN_CONFIG_BIAS_PULL_DOWN || 1001 param == PIN_CONFIG_DRIVE_STRENGTH) 1002 return pinctrl_gpio_set_config(offset, config); 1003 else if (param == PIN_CONFIG_DRIVE_OPEN_DRAIN || 1004 param == PIN_CONFIG_DRIVE_OPEN_SOURCE) 1005 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ 1006 return -ENOTSUPP; 1007 else if (param == PIN_CONFIG_PERSIST_STATE) 1008 return aspeed_gpio_reset_tolerance(chip, offset, arg); 1009 1010 return -ENOTSUPP; 1011 } 1012 1013 /** 1014 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handhsaking with 1015 * the coprocessor for shared GPIO banks 1016 * @ops: The callbacks 1017 * @data: Pointer passed back to the callbacks 1018 */ 1019 int aspeed_gpio_copro_set_ops(const struct aspeed_gpio_copro_ops *ops, void *data) 1020 { 1021 copro_data = data; 1022 copro_ops = ops; 1023 1024 return 0; 1025 } 1026 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_set_ops); 1027 1028 /** 1029 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire 1030 * bank gets marked and any access from the ARM will 1031 * result in handshaking via callbacks. 1032 * @desc: The GPIO to be marked 1033 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space 1034 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space 1035 * @bit: If non-NULL, returns the bit number of the GPIO in the registers 1036 */ 1037 int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, 1038 u16 *vreg_offset, u16 *dreg_offset, u8 *bit) 1039 { 1040 struct gpio_chip *chip = gpiod_to_chip(desc); 1041 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 1042 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 1043 const struct aspeed_gpio_bank *bank = to_bank(offset); 1044 unsigned long flags; 1045 1046 if (!gpio->cf_copro_bankmap) 1047 gpio->cf_copro_bankmap = kzalloc(gpio->config->nr_gpios >> 3, GFP_KERNEL); 1048 if (!gpio->cf_copro_bankmap) 1049 return -ENOMEM; 1050 if (offset < 0 || offset > gpio->config->nr_gpios) 1051 return -EINVAL; 1052 bindex = offset >> 3; 1053 1054 spin_lock_irqsave(&gpio->lock, flags); 1055 1056 /* Sanity check, this shouldn't happen */ 1057 if (gpio->cf_copro_bankmap[bindex] == 0xff) { 1058 rc = -EIO; 1059 goto bail; 1060 } 1061 gpio->cf_copro_bankmap[bindex]++; 1062 1063 /* Switch command source */ 1064 if (gpio->cf_copro_bankmap[bindex] == 1) 1065 aspeed_gpio_change_cmd_source(gpio, bank, bindex, 1066 GPIO_CMDSRC_COLDFIRE); 1067 1068 if (vreg_offset) 1069 *vreg_offset = bank->val_regs; 1070 if (dreg_offset) 1071 *dreg_offset = bank->rdata_reg; 1072 if (bit) 1073 *bit = GPIO_OFFSET(offset); 1074 bail: 1075 spin_unlock_irqrestore(&gpio->lock, flags); 1076 return rc; 1077 } 1078 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio); 1079 1080 /** 1081 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor. 1082 * @desc: The GPIO to be marked 1083 */ 1084 int aspeed_gpio_copro_release_gpio(struct gpio_desc *desc) 1085 { 1086 struct gpio_chip *chip = gpiod_to_chip(desc); 1087 struct aspeed_gpio *gpio = gpiochip_get_data(chip); 1088 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); 1089 const struct aspeed_gpio_bank *bank = to_bank(offset); 1090 unsigned long flags; 1091 1092 if (!gpio->cf_copro_bankmap) 1093 return -ENXIO; 1094 1095 if (offset < 0 || offset > gpio->config->nr_gpios) 1096 return -EINVAL; 1097 bindex = offset >> 3; 1098 1099 spin_lock_irqsave(&gpio->lock, flags); 1100 1101 /* Sanity check, this shouldn't happen */ 1102 if (gpio->cf_copro_bankmap[bindex] == 0) { 1103 rc = -EIO; 1104 goto bail; 1105 } 1106 gpio->cf_copro_bankmap[bindex]--; 1107 1108 /* Switch command source */ 1109 if (gpio->cf_copro_bankmap[bindex] == 0) 1110 aspeed_gpio_change_cmd_source(gpio, bank, bindex, 1111 GPIO_CMDSRC_ARM); 1112 bail: 1113 spin_unlock_irqrestore(&gpio->lock, flags); 1114 return rc; 1115 } 1116 EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); 1117 1118 /* 1119 * Any banks not specified in a struct aspeed_bank_props array are assumed to 1120 * have the properties: 1121 * 1122 * { .input = 0xffffffff, .output = 0xffffffff } 1123 */ 1124 1125 static const struct aspeed_bank_props ast2400_bank_props[] = { 1126 /* input output */ 1127 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1128 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */ 1129 { }, 1130 }; 1131 1132 static const struct aspeed_gpio_config ast2400_config = 1133 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */ 1134 { .nr_gpios = 220, .props = ast2400_bank_props, }; 1135 1136 static const struct aspeed_bank_props ast2500_bank_props[] = { 1137 /* input output */ 1138 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */ 1139 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */ 1140 { 7, 0x000000ff, 0x000000ff }, /* AC */ 1141 { }, 1142 }; 1143 1144 static const struct aspeed_gpio_config ast2500_config = 1145 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */ 1146 { .nr_gpios = 232, .props = ast2500_bank_props, }; 1147 1148 static const struct of_device_id aspeed_gpio_of_table[] = { 1149 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, }, 1150 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, }, 1151 {} 1152 }; 1153 MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table); 1154 1155 static int __init aspeed_gpio_probe(struct platform_device *pdev) 1156 { 1157 const struct of_device_id *gpio_id; 1158 struct aspeed_gpio *gpio; 1159 struct resource *res; 1160 int rc, i, banks; 1161 1162 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); 1163 if (!gpio) 1164 return -ENOMEM; 1165 1166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1167 gpio->base = devm_ioremap_resource(&pdev->dev, res); 1168 if (IS_ERR(gpio->base)) 1169 return PTR_ERR(gpio->base); 1170 1171 spin_lock_init(&gpio->lock); 1172 1173 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); 1174 if (!gpio_id) 1175 return -EINVAL; 1176 1177 gpio->clk = of_clk_get(pdev->dev.of_node, 0); 1178 if (IS_ERR(gpio->clk)) { 1179 dev_warn(&pdev->dev, 1180 "Failed to get clock from devicetree, debouncing disabled\n"); 1181 gpio->clk = NULL; 1182 } 1183 1184 gpio->config = gpio_id->data; 1185 1186 gpio->chip.parent = &pdev->dev; 1187 gpio->chip.ngpio = gpio->config->nr_gpios; 1188 gpio->chip.direction_input = aspeed_gpio_dir_in; 1189 gpio->chip.direction_output = aspeed_gpio_dir_out; 1190 gpio->chip.get_direction = aspeed_gpio_get_direction; 1191 gpio->chip.request = aspeed_gpio_request; 1192 gpio->chip.free = aspeed_gpio_free; 1193 gpio->chip.get = aspeed_gpio_get; 1194 gpio->chip.set = aspeed_gpio_set; 1195 gpio->chip.set_config = aspeed_gpio_set_config; 1196 gpio->chip.label = dev_name(&pdev->dev); 1197 gpio->chip.base = -1; 1198 gpio->chip.irq.need_valid_mask = true; 1199 1200 /* Allocate a cache of the output registers */ 1201 banks = gpio->config->nr_gpios >> 5; 1202 gpio->dcache = devm_kcalloc(&pdev->dev, 1203 banks, sizeof(u32), GFP_KERNEL); 1204 if (!gpio->dcache) 1205 return -ENOMEM; 1206 1207 /* 1208 * Populate it with initial values read from the HW and switch 1209 * all command sources to the ARM by default 1210 */ 1211 for (i = 0; i < banks; i++) { 1212 const struct aspeed_gpio_bank *bank = &aspeed_gpio_banks[i]; 1213 void __iomem *addr = bank_reg(gpio, bank, reg_rdata); 1214 gpio->dcache[i] = ioread32(addr); 1215 aspeed_gpio_change_cmd_source(gpio, bank, 0, GPIO_CMDSRC_ARM); 1216 aspeed_gpio_change_cmd_source(gpio, bank, 1, GPIO_CMDSRC_ARM); 1217 aspeed_gpio_change_cmd_source(gpio, bank, 2, GPIO_CMDSRC_ARM); 1218 aspeed_gpio_change_cmd_source(gpio, bank, 3, GPIO_CMDSRC_ARM); 1219 } 1220 1221 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); 1222 if (rc < 0) 1223 return rc; 1224 1225 gpio->offset_timer = 1226 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); 1227 if (!gpio->offset_timer) 1228 return -ENOMEM; 1229 1230 return aspeed_gpio_setup_irqs(gpio, pdev); 1231 } 1232 1233 static struct platform_driver aspeed_gpio_driver = { 1234 .driver = { 1235 .name = KBUILD_MODNAME, 1236 .of_match_table = aspeed_gpio_of_table, 1237 }, 1238 }; 1239 1240 module_platform_driver_probe(aspeed_gpio_driver, aspeed_gpio_probe); 1241 1242 MODULE_DESCRIPTION("Aspeed GPIO Driver"); 1243 MODULE_LICENSE("GPL"); 1244